CN106855995A - A kind of primitive pixels data window write control circuit - Google Patents
A kind of primitive pixels data window write control circuit Download PDFInfo
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- CN106855995A CN106855995A CN201611122139.9A CN201611122139A CN106855995A CN 106855995 A CN106855995 A CN 106855995A CN 201611122139 A CN201611122139 A CN 201611122139A CN 106855995 A CN106855995 A CN 106855995A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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Abstract
A kind of window write control circuit of primitive pixels data of the present invention belongs to figure generation technology field.The window write control circuit includes DSP, FPGA PLDs and SRAM memory.FPGA PLDs include first window coordinate registers, first comparator, windowing writing controller, the second window coordinates register, the second comparator, close window writing controller.Wherein, DSP and first window coordinate registers, first comparator, windowing writing controller, the second window coordinates register, the second comparator, close window writing controller and be connected；First comparator is connected with first window coordinate registers and windowing writing controller；Second comparator and the second window coordinates register and close window writing controller and be connected；SRAM memory and windowing writing controller and close window writing controller and be connected.Multiple windows can be carried out write-in control by window write control circuit strong adaptability of the present invention, efficiency high.
Description
Technical field
A kind of primitive pixels data window write control circuit of the present invention belongs to figure generation technology field, is related to a kind of figure
The window write control circuit of first pixel data.
Background technology
Primitive pixels data window write control circuit is a subfunction of liquid crystal display inside figure generative circuit
Circuit, in the rectangular window that sets on the liquid crystal display equipment screen and window external position, entering to frame memory device will be write
The graph data of row display carries out selection control process, and pel pixel data can be controlled to allow to prohibit outside write-in window in window
Only write, namely windowing function；Pel pixel data can also be controlled to forbid write-in in window, write-in is allowed outside window,
Close window function.Typically the method for software computing is taken to realize function above, by software to the primitive pixels that frame is deposited will be write
The address information and window position information of data are compared judgement, and each pixel count of pel is determined further according to judged result
According to whether writing frame and deposit.
Window interior is completely in when pel (such as line segment, letter, numeral, symbol) location of pixels that frame deposits will be write
Or when outside, this computing is relatively easy, but when single pel is split by window, namely in whole pixels of composition pel
A part in window interior,, in window-external, this computing will become complicated for remaining, and software operation efficiency will be reduced,
So as to cause the decline of view picture graphic hotsopt efficiency.
The content of the invention
The purpose of the present invention：A kind of window write control circuit of efficient primitive pixels data is provided.In order to meet
The windowing that is shown to pel during liquid crystal display graphic hotsopt, window demand is closed, propose a kind of hard-wired primitive pixels
Window writes control realization scheme, and SRAM will be write to DSP 1 using FPGA PLDs 2
The primitive pixels data of memory 9 are selected, judged and control process, realized to presetting rectangular window region pel
Write-in is allowed or writing prohibition function.The program realize it is simple and easy to apply, can to multiple windows simultaneously be controlled, adaptability
By force, efficiency high.
Technical scheme：A kind of window write control circuit of primitive pixels data, including at DSP data signals
Reason device 1, FPGA PLDs 2 and SRAM memory 9, it is characterised in that：The FPGA PLDs 2 include
First window coordinate registers 3, first comparator 4, windowing writing controller 5, the second window coordinates register 8, second are compared
Device 7, close window writing controller 6.
Wherein, DSP 1 and first window coordinate registers 3, first comparator 4, windowing write-in control
Device 5, the second window coordinates register 8, the second comparator 7, close window writing controller 6 be connected；
First comparator 4 is also connected with first window coordinate registers 3 and windowing writing controller 5 simultaneously；
Second comparator 7 simultaneously also with the second window coordinates register 8 and close window writing controller 6 and be connected；
SRAM memory 9 and windowing writing controller 5 and close window writing controller 6 and be connected.
It is described that the DSP 1 will need the window's position coordinate information for carrying out write-in control to be sent to
FPGA PLDs 2, wherein it is desired to the window's position coordinate information for carrying out windowing write-in control is sent to first window
Coordinate registers 3 are, it is necessary to the window's position coordinate information for close window write-in control is sent to the second window coordinates register 8.
The windowing write-in control model is that during fenestration procedure, DSP 1 is only in rectangular window
Inside write-in graphics pixel data, the data for writing window-external are shielded；The window write-in control model of closing is to close window behaviour
During work, DSP 1 only writes graphics pixel data outside rectangular window, writes the number of window interior
According to being shielded.
When windowing is operated, windowing enable signal is placed in effective status and sent by the DSP 1
To windowing writing controller 5, it would be desirable to which the address information and data message for writing the graph data of SRAM memory 9 are sent to opening
Window writing controller 5, it would be desirable to which the address information for writing the graph data of SRAM memory 9 is sent to the first comparator 4.
The address information and DSP 1 that the first window coordinate registers 3 of the first comparator 4 pairs are sent will
The primitive pixels address information for writing SRAM memory 9 is compared treatment, and comparative result forms 1 binary signal and sends
To the windowing writing controller 5.The comparative result that the windowing writing controller 5 is given according to first comparator 4, control
Whether the primitive pixels data that DSP 1 sends write SRAM memory 9.
When window operation is closed, the DSP 1 will close window enable signal and be placed in effective status and send
To closing window writing controller 6, it would be desirable to which the address information and data message for writing the graph data of SRAM memory 9 are sent to closing
Window writing controller 6, it would be desirable to which the address information for writing the graph data of SRAM memory 9 is sent to the second comparator 7.Second
The address information and DSP 1 that 7 pairs of the second window coordinates registers 8 of comparator are sent will write SRAM and deposit
The primitive pixels address information of reservoir 9 is compared treatment, and comparative result forms 1 binary signal and sends to closing window write-in control
Device processed 6.It is described to close the comparative result that window writing controller 6 is provided according to the second comparator 7, control DSP 1
Whether the primitive pixels data for sending write SRAM memory 9.
Beneficial effects of the present invention：Primitive pixels data window write control circuit of the present invention, patrols using FPGA is programmable
The internal logic resource of device 2 is collected, to the pel picture that will write SRAM memory 9 of the computing of DSP 1 generation
Plain address information and the window's position coordinate information set in advance are compared, according to comparative result by the figure of exterior domain in window
First pixel data carries out differentiation write-in control process, to obtain the windowing of figure shows, close window effect.This programme uses FPGA
PLD 2 carries out the window write-in control process of primitive pixels, and scheme is simple and easy to apply, and accessible window number can
Increased and decreased as needed, figure windowing is realized using hardware mode, window is closed and is shown, can significantly be mitigated DSP Digital Signal Processing
The workload that the software of device 1 is calculated, so as to improve the efficiency of graphic hotsopt, increases the fluency that picture shows, improves figure shows
Effect.
Brief description of the drawings
Fig. 1 is the theory diagram of primitive pixels data window write control circuit of the present invention；
Wherein, 1-DSP digital signal processors, 2-FPGA PLDs, 3- first windows coordinate registers, 4-
First comparator, 5- windowings writing controller, 6- close window writing controller, the comparators of 7- second, the deposit of the window coordinates of 8- second
Device, 9-SRAM memories.
Fig. 2 is liquid crystal display viewing area window schematic diagram.
Specific embodiment
The present invention is described in detail below by specific embodiment：
Fig. 1 is referred to, it is the theory diagram of primitive pixels data window write control circuit of the present invention.
A kind of window write control circuit of primitive pixels data, including connected DSP 1, FPGA
PLD 2 and SRAM memory part 9, it is characterised in that：The FPGA PLDs 2 include first window
Coordinate registers 3, first comparator 4, windowing writing controller 5, the second window coordinates register 8, the second comparator 7, close window
Writing controller 6.
Wherein, DSP 1 and first window coordinate registers 3, first comparator 4, windowing write-in control
Device 5, the second window coordinates register 8, the second comparator 7, close window writing controller 6 be connected；
First comparator 4 is also connected with first window coordinate registers 3 and windowing writing controller 5 simultaneously；
Second comparator 7 simultaneously also with the second window coordinates register 8 and close window writing controller 6 and be connected；
SRAM memory 9 simultaneously with windowing writing controller 5 and close window writing controller 6 and be connected.
Described DSP 1, for carrying out pel rendering algorithm computing, obtains the address sum of pel
It is believed that breath, sends to FPGA PLDs 2.When thering is pel to open a window, closing window display demand, by the window's position coordinate letter
Breath and windowing, close window enable control signal send to FPGA PLDs 2.
Described first window coordinate registers 3, the windowing position for receiving the transmission of DSP 1 is sat
Mark data, and deposit treatment is carried out to coordinate data.With liquid crystal display on-screen display (osd) area as two-dimensional coordinate system, it is with screen summit
The origin of coordinates, the coordinate for window positioning includes two diagonal apex coordinates (x1, y1), (x2, y2).Fig. 2 is referred to, wherein
x2>x1,y2>y1。
Described first comparator 4, the address date of the primitive pixels for receiving SRAM memory to be written 9, by it
Coordinate data (x, y) is converted to, and the window coordinates data (x1, y1) sent with first window coordinate registers, (x2, y2) are entered
Row multilevel iudge, x1 is met when simultaneously<x<x2、y1<y<During y2 conditions, judge that primitive pixels, in window interior, otherwise, judge figure
First pixel is in window-external.Primitive pixels location comparison result is sent to windowing and write by first comparator 4 with 1 binary mode
Enter controller 5.
Described windowing writing controller 5, the address of the primitive pixels for receiving the transmission of DSP 1
And data message, 1 binary system windowing enable signal that monitoring DSP 1 sends, there is pel windowing demand
When, according to 1 binary system comparative result that first comparator 4 sends, the write operation to primitive pixels is controlled treatment.When
When primitive pixels are located at window interior, the write-in control end of SRAM memory 9 is placed in enabled state, primitive pixels address sum
It is believed that breath is able to normal transmission to the address of SRAM memory 9 and data/address bus, primitive pixels data write-in SRAM memory 9.
When primitive pixels are located at window-external or window edge, the write-in control end of SRAM memory 9 is placed in off, pel
Pixel data is forbidden writing SRAM memory 9.
The second described window coordinates register 8, the window position that closes for receiving the transmission of DSP 1 is sat
Mark data, and deposit treatment is carried out to coordinate data.With liquid crystal display on-screen display (osd) area as two-dimensional coordinate system, for the window for positioning
Mouth coordinate includes two diagonal vertex point coordinate informations (x3, y3), (x4, y4).Refer to Fig. 2, wherein x4>x3,y4>y3.
The second described comparator 7, the address date of the primitive pixels for receiving SRAM memory to be written 9, by it
Coordinate data (x, y) is converted to, and window coordinates data (x3, y3), (x4, the y4) sent with the second window coordinates register 8
Judgement is compared, x3=is met when simultaneously<x<=x4, y3<=y<During=y4 conditions, primitive pixels are judged in window interior,
Otherwise, judge primitive pixels in window-external.Second comparator 7 is by primitive pixels location comparison result with 1 binary mode
Send to closing window writing controller 6.
Described closes window writing controller 6, the address of the primitive pixels for receiving the transmission of DSP 1
And data message, monitoring 1 binary system sending of DSP 1 closes window and enables signal, and window demand is closed there is pel
When, according to 1 binary system comparative result that the second comparator 7 sends, the write operation to primitive pixels is controlled treatment.When
When primitive pixels are located at window interior or window edge, the write-in control end of SRAM memory 9 is placed in off, pel picture
Prime number evidence forbids writing SRAM memory 9, when primitive pixels are located at window-external, by the write-in control end of SRAM memory 9
Enabled state is placed in, primitive pixels address and data message are able to normally send to the address of SRAM memory 9 and data/address bus,
Primitive pixels data allow to write SRAM memory 9.
Described SRAM memory 9, the primitive pixels data for accessing the computing of DSP 1 generation,
The address signal of SRAM memory 9, data-signal and control signal are all given by FPGA PLDs 2.
Described windowing write control circuit 5 and window write control circuit 6 is closed, using in FPGA PLDs
Multiple windows can be carried out write-in control by portion's resource simultaneously, and window number is not limited to this programme.Each window corresponds to 1
Window enable signal is closed in the binary windowing in position, is sent to FPGA PLDs 2 by DSP 1.
Described coordinate origin and change in coordinate axis direction, is not limited to this programme mask method, and definable liquid crystal display shows
Any one corner position of region is origin, and coordinate position is converted by dsp software.
Described DSP 1, during implementation, can select the DSP devices of AD companies or TI companies.It is described
FPGA PLDs 2, during implementation, can select any Series FPGA of altera corp or Xilinx companies.
After selected PLD, first window coordinate registers 3, first comparator 4, windowing writing controller 5, the second window
Coordinate registers 8, the second comparator 7, close window writing controller 6 VHDL is used by the programmable logic resource that FPGA is internally integrated
Or Verilog hardware description language programming realizations, can also be realized using pattern input mode.Described SRAM device 9, it is optional
The static RAM of the standard produced with different company.
Claims (3)
1. a kind of window write control circuit of primitive pixels data, including DSP (1), FPGA are programmable
Logical device (2) and SRAM memory part (9), it is characterised in that：The FPGA PLDs (2) are including first window
Coordinate registers (3), first comparator (4), windowing writing controller (5), the second window coordinates register (8), second are compared
Device (7), close window writing controller (6)；
Wherein, DSP (1) and first window coordinate registers (3), first comparator (4), windowing write-in control
Device (5) processed, the second window coordinates register (8), the second comparator (7), close window writing controller (6) be connected；
First comparator (4) with first window coordinate registers (3) and windowing writing controller (5) while be also connected；
Second comparator (7) at the same also with the second window coordinates register (8) and close window writing controller (6) and be connected；
SRAM memory (9) and windowing writing controller (5) and close window writing controller (6) and be connected；
It is described that the DSP (1) will need the window's position coordinate information for carrying out write-in control to be sent to
FPGA PLDs (2), wherein it is desired to the window's position coordinate information for carrying out windowing write-in control is sent to the first window
Mouth coordinate registers (3) is, it is necessary to the window's position coordinate information for close window write-in control is sent to the deposit of the second window coordinates
Device (8)；
The windowing write-in control model is that during fenestration procedure, DSP (1) is only in rectangular window
Portion writes graphics pixel data, and the data for writing window-external are shielded；The window write-in control model of closing is to close window operation
Period, DSP (1) only writes graphics pixel data outside rectangular window, writes the number of window interior
According to being shielded.
2. primitive pixels data window write control circuit according to claim 1, it is characterised in that：In windowing operation
When, windowing enable signal is placed in effective status and sent to windowing writing controller by the DSP (1)
(5), it would be desirable to which the address information and data message for writing the graph data of SRAM memory (9) are sent to windowing writing controller
(5), it would be desirable to which the address information for writing the graph data of SRAM memory (9) is sent to the first comparator (4)；Described
The address information and DSP (1) that one comparator (4) is sent to the first window coordinate registers (3) will
The primitive pixels address information for writing SRAM memory (9) is compared treatment, and comparative result forms 1 binary signal hair
Deliver to windowing writing controller (5)；The comparing knot that windowing writing controller (5) is given according to first comparator (4)
Really, whether the primitive pixels data that control DSP (1) sends write SRAM memory (9).
3. primitive pixels data window write control circuit according to claim 1, it is characterised in that：Closing window operation
When, the DSP (1) will close window and enable signal and be placed in effective status and send to closing window writing controller
(6), it would be desirable to which the address information and data message for writing the graph data of SRAM memory (9) are sent to closing window writing controller
(6), it would be desirable to which the address information for writing the graph data of SRAM memory (9) is sent to the second comparator (7)；Second comparator
(7) address information and DSP (1) sent to the second window coordinates register (8) will write SRAM and deposit
The primitive pixels address information of reservoir (9) is compared treatment, and comparative result forms 1 binary signal and sends to closing window write-in
Controller (6)；It is described to close the comparative result that window writing controller (6) is provided according to the second comparator (7), control DSP numeral letters
Whether the primitive pixels data that number processor (1) sends write SRAM memory (9).
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| CN201611122139.9A CN106855995A (en) | 2016-12-08 | 2016-12-08 | A kind of primitive pixels data window write control circuit |
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| CN201611122139.9A CN106855995A (en) | 2016-12-08 | 2016-12-08 | A kind of primitive pixels data window write control circuit |
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| CN104202513A (en) * | 2014-06-30 | 2014-12-10 | 北京控制工程研究所 | FPGA based star-sensor multimode image preprocessing method |
| CN104299550A (en) * | 2013-11-27 | 2015-01-21 | 中国航空工业集团公司洛阳电光设备研究所 | FPGA-based vector character generator |
| CN105573991A (en) * | 2015-12-15 | 2016-05-11 | 英业达科技有限公司 | Translation system and translation method |
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2016
- 2016-12-08 CN CN201611122139.9A patent/CN106855995A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1862654A (en) * | 2005-05-12 | 2006-11-15 | 逐点半导体（上海）有限公司 | Display for dynamic contrast of image processing effect and display method |
| US7673188B2 (en) * | 2007-08-09 | 2010-03-02 | Globalfoundries Inc. | System and method for controlling synchronous functional microprocessor redundancy during test and method for determining results |
| CN103297730A (en) * | 2013-06-14 | 2013-09-11 | 无锡华润矽科微电子有限公司 | On screen display controller and corresponding on display control method |
| CN104299550A (en) * | 2013-11-27 | 2015-01-21 | 中国航空工业集团公司洛阳电光设备研究所 | FPGA-based vector character generator |
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Application publication date: 20170616 |
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