CN1068459C - Static random access storage and its manufacturing method - Google Patents
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Abstract
The present invention relates to an SRAM memory unit with the function of increasing stability. Grids of pass transistors contained in the SRAM memory unit are shaped by an oxidizing procedure, so that the lower edges of the grids are lifted and separated from the surface of a substrate. Because grids of load and pull-down transistors are shielded in the oxidizing procedure, the grids of load and pull-down transistors can have the known rectangular shape. In relation to an electric current flowing across the pull-down transistors, an electric current flowing across the pass transistors are reduced because the shape of the grids of the pass transistors are reformed, and thus, the inappropriate loss of data in the SRAM memory unit is reduced.
Description
(static random access memory SRAM), particularly relates to a kind of SRAM with improved stability and preparation method thereof to the present invention relates to a kind of static RAM.
Component density within the integrated circuit can be utilized integrated circuit (IC) design (the reducedgeometry integrated circuit designs) principle in reduction space, increases performance of integrated circuits and reduces its actual cost.Comprise dynamic random access memory (DRAM), static RAM (SRAM), read-only memory (ROM), the modern integrated circuits memory device of Erasable Programmable Read Only Memory EPROM (EEPROM) etc. all is the obvious example that utilizes this tactful principle.The density of the memory cell in the integrated circuit memory devices just constantly increases, and what follow is the corresponding reduction of the unit bit carrying cost of this class device.The increase of density is to utilize to make small construction in device, and utilizes between the reduction device or the compartment that constitutes between the structure of device realizes.Usually, the design criterion of this class reduced size (design rules) can be attended by the correction of layout, design and structure.When using the design criterion of this class reduced size, these are revised and change and will just may carry out by the size of reduction device, but also will keep the performance of device.As an example, the reduction of its operating voltage is because such as the reduction gate oxide thicknesses among multiple existing integrated circuits, and promotes that error on little shadow extent control just may finish.On the other hand, the design criterion of size reduction also makes and is necessary to reduce operating voltage, so that if small size device is during with existing higher operation voltage operation, and the hot carrier (hotcarriers) that restriction is produced.
Design criterion according to the reduction space is made static RAM (SRAM), and during with the builtin voltage operation that reduces, may lower the stability of SRAM memory cell.The reduction of operating voltage, and the change in other designs, may be with during the data message read operation, in order to guarantee that the voltage range that SRAM can keep stablizing the data message state is reduced, and the increase read operation is read the median that is stored in the data in the SRAM memory cell, even the possibility of complete loss of information, typical SRAM design includes and is coupled in two or four MOS transistor that become a kind of breech lock (latch) structure together, and it has two charge-storage node (charge storage node) for the charged state of storage corresponding to data.Utilize one of the correspondence optionally each charge-storage node is coupled among a pair of paratope line, just can be in a kind of mode of non-damageability, with data by reading in the existing SRAM memory cell, this optionally coupling is to utilize a pair of transfering transistor (passtransistor), also claim what conversioning transistor was finished, each transfering transistor one of then be connected in two charge-storage node with and one of corresponding paratope line between the two.Word-line signal is provided for the grid of transfering transistor, transfering transistor is opened for the ON state during data read operation.Electric charge can be flowed through and is in the transfering transistor that is opened for the ON state and arrive charge-storage node, or is flowed out to arrive by charge-storage node and be in the transfering transistor that is opened for the ON state, so that in the bit line discharges, and makes another bit lines charging.Variation in voltage on the bit line just can be responded to by a differential amplifier (differential amplifier).
Keep stablely for the memory cell breech lock that during this data read operation, makes SRAM, will have the charge-storage node must be among the SRAM at least to carry out charge or discharge than flow of charge turnover corresponding bit lines faster rate.In the past, this control is to utilize the passage that transfering transistor is connected to the specific charge memory node, makes to such an extent that to be connected to transistorized at least one passage of SRAM memory cell of specific charge memory node than its drain electrode narrow and/or grow.The flow through transistorized electric current of at least one SRAM memory cell of this geometry designs tolerable is bigger than the electric current of the corresponding transfering transistor of flowing through; Its result, the charge or discharge of charge-storage node are carried out sooner than the bit line discharges or the charging of correspondence.
But, this geometry designs but has some shortcoming and restriction.For example, the passage of transfering transistor is made to such an extent that narrowlyer can make reading of data slack-off with write activity than length.In addition, the relative geometrical construction meeting of different memory cell and transfering transistor can accurately make to cause some restrictions on which kind of degree for a short time a specific SRAM memory cell.
Therefore one object of the present invention is to provide a kind of SRAM, and it has the stability of enhancement, can operate under the voltage that reduces, and perhaps can use the design criterion of reduced size to make.Read the grid of an employed transfering transistor of SRAM memory cell, compared with memory cell transistor, its configuration preferably can provide the mutual conductance (transconductance) of attenuating, can increase stability for the SRAM memory cell.A specific embodiment of a kind of method of the present invention can be allowed the mode of promoting stability of utilizing, and makes the cross section appearance of the grid of transfering transistor.
According to one embodiment of present invention, provide a kind of SRAM, it has a plurality of SRAM memory cell of carrying out addressing with bit line, and these SRAM memory cell comprise: a height is with reference to an electric potential contact and a low reference potential contact; One charge-storage node; One pull-down transistor, it is connected to this charge-storage node and should hangs down the reference potential contact, and this pull-down transistor has one source pole, a drain electrode and a pull-down transistor grid; An and transfering transistor, it is connected to this charge-storage node and a bit lines, and this transfering transistor has one source pole, a drain electrode and a transfer transistor gate, transfer transistor gate has a lower surface, and this lower surface is bent with respect to the lower surface of the grid of this pull-down transistor.
Another embodiment of SRAM of the present invention has a plurality of SRAM memory cell with the bit line addressing, comprising: a height is with reference to an electric potential contact and a low reference potential contact; One charge-storage node; One pull-down transistor, it is connected to this charge-storage node and should hangs down the reference potential contact, and this pull-down transistor has one source pole, a drain electrode and a pull-down transistor grid; An and transfering transistor, it is connected to this charge-storage node and a bit lines, this transfering transistor has one source pole, one drain electrode, one passage and a transfer transistor gate, this transfer transistor gate is arranged to produce the electric field of a specified configuration in the channel region of this transfering transistor, this electric field that is wherein produced in channel region and then the source electrode of transfering transistor with the drain electrode part lowered intensity.
The method of a kind of SRAM of making is provided according to a further aspect in the invention, comprise: a substrate is provided and is formed at this suprabasil lead that constitutes by doped polycrystalline silicon, wherein one first lead is formed on the channel region of a pull-down transistor, and one second lead is formed on the channel region of a transfering transistor; Cover this first lead in a kind of mode of protecting this first lead to avoid oxidation; And this second lead is exposed in the oxidation environment, the then crested of first lead is so that first and second lead has different cross-sectional configuration; At least one below part of this first and second lead is a doped polycrystalline silicon.
For allow above-mentioned and other purposes of the present invention, feature, and advantage can become apparent some preferred embodiments cited below particularly, and conjunction with figs. elaborates.In the accompanying drawing:
Fig. 1 represents the circuit diagram of a specific embodiment of the present invention;
Fig. 2 is the partial sectional view of the part of SRAM represented among Fig. 1;
Fig. 3 and Fig. 4 are partial sectional view, in order to show the flow process of the device in the construction drawing 2.
The preferred embodiments of the present invention can be utilized the mutual conductance of the transfering transistor that optionally forms a SRAM memory cell, with the flow through electric current of transfering transistor of restriction, but do not change transistorized geometric modelling of SRAM and layout, and promote the stability of SRAM memory cell.A concrete preferred embodiment of the present invention can utilize the configuration that changes transfer transistor gate to be adjusted the mutual conductance of transfering transistor.For example, the oxidation technology of a species diversity formula can be with the gate oxidation of transfering transistor, and to produce the grid of a kind of its lower limb by the substrate lifting, this mode can lower the electric current of the passage of the transfering transistor of flowing through.The PROCESS FOR TREATMENT of this oxidation; because the grid of some memory cell transistor is protected among the oxidation technology step at least; so that the configuration of transfer transistor gate has been changed; configuration with the transistorized grid that is protected then not oxidized technology changes, thereby is the design that belongs to a species diversity formula.
Show a SRAM memory cell (memory cell of hexad transistor or 6T) among Fig. 1, it includes two PMOS load transistors 10,12 and two NMOS pull-down transistors (pull-downtransistor) 14,16 link up to constitute cross-linked inverter (inverter).The grid of each PMOS load transistor 10,12 is connected to the NMOS pull- down transistor 14,16 of a correspondence respectively.The drain electrode of PMOS load transistor 10,12 is connected to the drain electrode of corresponding nmos pass transistor 14,16 respectively, has the inverter of existing structure with formation.The source electrode of load transistor is connected to a high reference potential, Vcc normally, and the source electrode of pull-down transistor then is connected to lower reference potential, normally a Vss.The PMOS transistor 10 that constitutes an inverter and the grid of nmos pass transistor 14 then are connected to the drain electrode of another inverter transistor 12,16.Similarly, the PMOS transistor 12 that constitutes another inverter and the grid of nmos pass transistor 16 then are connected to the drain electrode of transistor 10,14.Therefore, the current potential that appears at the drain electrode (node N1) of first inverter transistor 10,14 promptly is supplied to the grid of second inverter transistor 12,16, and electric charge then is used to second inverter is remained on out the state of (ON) or pass (OFF).An opposite current potential of logic appears at the drain electrode (node N2) of second inverter transistor 12,16, and appears at the grid of first inverter transistor 10,14, first inverter is remained on complementary OFF or ON state.Like this, the breech lock of the SRAM memory cell shown in the figure (also claim latch) promptly can have two kinds of stable status: predetermined current potential appears at charge-storage node N1 and electronegative potential appears at a kind of state of charge-storage node N2, and electronegative potential appears at charge-storage node N1 and predetermined current potential appears at second kind of state of charge-storage node N2.Binary data just can be utilized conversion between the two states of this breech lock and go on record.Enough charge storage must be arranged on charge-storage node, and coupling on the grid at relevant inverter, so that can under unambiguous situation, an inverter be remained on the ON state, and another inverter is remained under the OFF state, thereby kept store status.The stability of a SRAM memory cell, in the time of can utilizing current potential on its charge-storage node with respect to its nominal value (nominal value) change, and the scope that still the SRAM memory cell can be remained in its reset condition is simultaneously measured.
The state of SRAM memory cell normally utilizes two charge-storage node N1 with memory cell, and N2 optionally is connected to a pair of complementary bit lines, and (BL BL) reads.A pair of transfering transistor 18,20 is connected charge-storage node N1 respectively, and N2 and corresponding bit lines BL are between the BL.Before carrying out a read operation, bit line BL, BL be prior to being generally 1/2 (Vcc-Vss), a voltage midpoint grade between the high and low reference voltage, and a signal on the word line WL switches to transfering transistor the ON state more afterwards.For example, consider to be charged to a predetermined current potential Vcc as N1, N2 then is a kind of situation of electronegative potential Vss by discharge.When transfering transistor 18,20 was switched to the ON state, electric charge promptly began to be flowed through transfering transistor 18 and arrived bit line BL by node N1.Electric charge on the node N1 begins by spilling on the bit line BL, and the electric current of the node N1 that arrives is replenished by flowing through load transistor 10.At the same time, electric charge can be by flow through transfering transistor 20 and arrive node N2 of bit line BL, and also has electric charge by the node N2 pull-down transistor 16 of flowing through.The flow through electric current of transistor 10 of the current ratio of transfering transistor 18 is many if flow through, and electric charge just can begin by spilling on the node N1, and when being reduced to a certain level, just pull-down transistor 16 can be switched to the OFF state.The flow through electric current of transistor 16 of the current ratio of transfering transistor 20 is many if flow through, and electric charge just can begin to accumulate in node N2, and when charging to a certain level, just load transistor 10 can be switched to the state of OFF.
Charge-storage node N1, the discharge of N2 and charging can cause the SRAM memory cell to be switched between store status, thereby the data that make the mistake are stored in the result in the SRAM memory cell.Therefore just needing can be with the Current Control of the transfering transistor of can flowing through on a relative level, and this relative level must be lower than the level of some memory cell transistor at least of flowing through.That is a higher relatively electric current should be flowed through, and each one of is connected in the load of each charge-storage node or the pull-down transistor.Usually, the making of six transistorized SRAM memory cell be with two load transistor 10 and 12 be made into thin-film transistor (thin-film transistor, TFT).With regard to the structure of this double T FT SRAM memory cell, load transistor 10,12 source electrode, drain electrode and channel region and grid, all be to make by the polysilicon that is deposited on one deck insulating material, and this insulating material is covered with the SRAM of a lower floor circuit, and this circuit comprises transfering transistor and is formed at pull-down transistor on the substrate surface.Usually can need to make load transistor,, make the TFT load transistor of high transconductance consume the electric power that can't make us accepting because polysilicon transistors tends to leakage current with high transconductance degree.Therefore, pull-down transistor preferably can be easier to the more electric current of conducting than transfering transistor, and its degree wants to reach the degree that operation that sufficient to guarantee once reads is unlikely the data mode that changes the SRAM memory cell.
Owing to provide and have relative narrower and than the transfering transistor of long-channel, and provide and have relative broad and than the pull-down transistor of jitty, among the application of existing SRAM, lead (conductance) existing institute difference by the electricity of transfering transistor and pull-down transistor.But, adopt the design criterion of reduced size, or design is when using the operating voltage that reduces, owing to comprised technologic restriction such as minimum compact mechanism, this strategy performed to that to surpass the degree of using at present be infeasible in reality.Will keep a fixing ratio between the mutual conductance of pull-down transistor and transfering transistor, the size of reducing memory cell simultaneously again further is extremely difficult.Similarly, if operating voltage reduces,, otherwise to guarantee to have enough voltage ranges so that memory cell can stable operation also be very difficult unless the size of memory cell is made greatlyyer in unfavorable mode.Therefore, embodiments of the invention just provide a kind of diverse ways, can reduce the electricity of transfering transistor and lead, but the electricity that does not reduce pull-down transistor is led.
Fig. 2 shows the cross section part of a SRAM according to a preferred embodiment of the present invention, particularly, manifests the configuration of pull-down transistor 14 and transfering transistor 18 of the preferred embodiment of a SRAM in the mode of schematic diagram in Fig. 2.Embodiment shown in the figure comprises a transfer transistor gate 44 that can produce electric field in the transfering transistor passage, the electric field that it produced is different from the electric field that transfer transistor gate produced of existing shape significantly, the enforcement of Fig. 2 the electric field that produced of routine transfer transistor gate 44, its the most difference be in the channel region of transfering transistor, in connection with source electrode and drain electrode.The electric field strength of hanging down in this zone is only compared with existing transfer transistor gate and can be attracted less free carrier, thereby has lowered by the electricity of transfering transistor and lead.If strengthen the electric field that is produced in the channel region, preferably should be able to make the lower surface edge slynessization of transfer transistor gate, outside the source/drain regions that extends to periphery, and cover channel region itself.Like this, the lower surface edge of transfer transistor gate just can give rise on the surface of substrate, and the channel region at the bottom of the transcendence basis is between the range of scatter of source/ drain electrodes 40,42.
Existing transfer transistor gate has the plane formula lower surface that separates with an average distance with channel region.With regard to the similar current potential that puts on similar channel region, grid 44 among Fig. 2 can be at the edge of channel region or produce more low intensive electric field in source/drain electrodes, and the channel region electricity that causes the conductance ratio of channel region to have the transfering transistor of existing plane formula gate electrode is led low.No matter which kind of situation has less conductor can appear at transfering transistor and then in the zone of source/drain regions.Therefore, the not same electric field that transfer transistor gate produced that shows among the figure just can lower the mutual conductance by the passage of transfering transistor, with respect to the magnitude of current of the pull-down transistor 14 of flowing through, has lowered the magnitude of current of the transfering transistor 18 of flowing through.As shown among Fig. 2, the cross-sectional configuration of the grid 38 of pull-down transistor 14, do not change with respect to the configuration of made in existing SRAM is significant, make the redjustment and modification of cross-sectional configuration of grid 44 of transfering transistor 18, can utilize the mode that can increase SRAM memory cell stability, the electricity that lowers transfering transistor 18 is led.
SRAM among Fig. 2 is made on a silicon base 30, and 32 of an oxidation cell isolation region is formed on the surface of substrate 30.Pull-down transistor 14 is by being formed at substrate 30 lip-deep source/ drain regions 34,36, and is formed at that a grid 38 on the substrate 30 lip-deep gate oxide level (not shown)s constituted.18 of transfering transistors are by being formed at source/ drain regions 40,42 on the substrate surface, and are formed at that a grid 44 on the gate oxide layers (not shown) constituted.Drop-down grid 38,44 with transfering transistor is made of the polysilicon that mixes at least partly.When grid was made formation with the conductive material of multilayer, the lowermost layer of grid part was made of one deck doped polycrystalline silicon at least.Lowermost layer in the grid 38,44 of drop-down and transfering transistor can be made by the polysilicon of independent one deck, and perhaps, among other SRAM memory cell structure, different polysilicon layers can be incorporated in the grid of drop-down and transfering transistor.
Shown structure can utilize a species diversity formula oxidation technology process to make among Fig. 2, in this technology, and the grid of pull-down transistor; and load transistor; if also be made on the standard of substrate position, all covered by a layer mask, avoid oxidized with the protection grid.Outside the grid of transfering transistor then kept being exposed to, perhaps, the mask that is covered on the transfering transistor was removed, so that the grid of transfering transistor is come out.Polysilicon gate then just is exposed among a kind of environment of oxidation, for example, is exposed to temperature among 950 to 1050 ℃ oxygen, and the lower edge that its open-assembly time continues to be enough to grid is oxidized to needed degree.The upper limb of transfer transistor gate is oxidized in this technical process through regular meeting.But, if the grid of transfering transistor forms with a kind of structure of multilayer, such as being formed at the layer of metal silicide on the surface of polysilicon electrode, then the upper limb of transfer transistor gate just can be not oxidized, or just oxidized a little.In this case, the upper limb of transfer transistor gate promptly can be kept general shape, shown shape among the embodiment such as Fig. 2.The grid 38 of pull-down transistor 14 then normally has common rectangle appearance.Certain part slynessization of the upper limb of grid 38 can take place when different oxide layers forms around grid, but this slynessization is less important, can't change formed Electric Field Distribution situation in the passage of pull-down transistor significantly.Though show drop-down and transfering transistor among the figure, the passage between its source/drain regions separately has length about equally, under multiple situation, it is longer than the passage of pull-down transistor that the passage of transfering transistor can be made.After oxidation, then promptly carry out once etched program, to remove polysilicon oxide, carry out further PROCESS FOR TREATMENT with existing mode more afterwards, so that finish the making of SRAM.
The mutual conductance of transfering transistor is by the degree that technology lowered of difference oxidation, is that lower edge according to transfer transistor gate has and how much is removed and fixed.Like this, just must determine the time of polysilicon oxidation technology, and thereby can determine the electricity relatively of transfering transistor to lead the degree that can lower.And this can utilize between judgement transfering transistor and the pull-down transistor, if will be at a given transistor size and geometric modelling, and other transistor and memory cell characteristic and obtain a kind of stable memory cell, how much difference that flows of electric current has and determines therebetween.Certainly, attenuating can be flowed through the magnitude of current of transfering transistor can be to other performance characteristicses of SRAM, impact to some extent such as access speed etc., therefore just the current capacity of transfering transistor should not reduced too many.
If the edge of transfer transistor gate is made by the material of the work function that has the employed N type of the middle body that is different from transfer transistor gate polysilicon with respect to silicon (work function), just can obtain a kind of effect similar to the embodiment among Fig. 2.For example, transfer transistor gate can be made by P type polysilicon, and it has and the different work function of N type polysilicon with respect to silicon.In so a kind of embodiment, be formed at the lip-deep one deck tungsten silicide of transfer transistor gate, can contact with P type marginal portion with the N type middle body of polysilicon gate, so that whole grid is kept as an equipotential surface.The difference of the work function at transfer transistor gate edge can be in a kind of mode of mutual conductance of remarkable change transfering transistor, substantially changes in the passage and the electric field that the edge produced in the source/drain contact zone.But the width and the doping change of the P type marginal portion of grid are adjusted to needed degree with the mutual conductance with transfering transistor with respect to the pull-down transistor crystalline substance.Embodiment among Fig. 2 is than this variation better implement example, because the embodiment among Fig. 2 utilizes less processing step, and looser design criterion, just can create.
Shownly among Fig. 3 and Fig. 4 be and make a kind of SRAM that adjusts the memory cell of transfering transistor according to mode shown among Fig. 2 that includes, and some relevant processing step.Because the major part of SRAM structure all is known with technology, so will not go through at this.At first with reference to figure 3, what wherein show is the situation of the memory cell of SRAM in the interstage of technical process.Field oxide cell isolation region 32 has been formed on the substrate 30, and one deck gate oxide (not shown) also has been formed on the substrate 30, and one deck doped polycrystalline silicon also is formed on the gate oxide level.Doped polysilicon layer has utilized a kind of existing mode to carry out imaging, so that the pull-down transistor grid with common structure is provided, and provides one without the electrode that is shaped on the passage of transfering transistor 18.The implantation of source/drain is automatically in alignment with grid 38,44.If these transistors will adopt the structure of the source/drain of a low-doped drain, so, have only low-doped drain (LDD) part of implantation can carry out at this moment usually.
With reference to figure 4, after grid was patterned as shown in Figure 3ly, a layer mask 46 just was formed on the grid of pull-down transistor, so that the polysilicon layer in the protection grid.There are several different mask materials can be used for protecting the grid of pull-down transistor.For example; utilize TEOS (tetra-ethyl-ortho-silicate) to carry out the silica of the formed layer thickness of chemical vapour deposition (CVD) 50 to 500 ; perhaps utilize the formed one deck high-temperature oxide of similar mode layer all can; with one deck silicon nitride or drop-down formed protectiveness mask, can provide preferable resistance to further oxidation.After mask 46 formed, any oxide or the mask material that are formed on the grid of transfering transistor 18 all were removed.This can utilize on the grid at least of pull-down transistor the photoresist mask that forms one deck protectiveness, and, when load transistor is formed in the substrate of SRAM, also is formed on the load transistor and finishes.Utilize the HF solution of dilution, or utilize oxide dry etch (the isotropic fluoride-based oxide dry etch) technology of isotropism fluorine containing etchant agent, all any oxide skin(coating) on the gate surface of transfering transistor can be removed.Other mask material is also removed as required and in addition.Certainly, the photoresist mask of front production process step all can be by ashing (ashed) in any oxidation technology step, so just may not need to comprise that a special step removes photoresist mask more again.Then, the oxidation operation that once prolongs again is oxidized to needed degree with the polysilicon layer with transfer transistor gate.
Further processing step then just can be proceeded, so that finish the making of SRAM.If some or all SRAM transistor all adopts the LDD source/drain regions, then the oxide on the grid or other mask layers just all are removed.Divided oxide interlayer now one of is formed at the operation of general CVD oxidate and etch-back in the two sides of grid again, then forms the heavy doping part of LDD electrode again.Do not mix if must not carry out further source drain district, the process of constructing among Fig. 4 is just proceeded the deposition of one deck thick dielectric layer.No matter which kind of situation all needs further existing processing step to finish the making of this device.
Though disclose the preferred embodiments of the present invention, these embodiment are not in order to limit the present invention.Those skilled in the art can make and changing and retouching, so protection scope of the present invention should be defined by the accompanying Claim book without departing from the spirit and scope of the present invention.
Claims (6)
1, a kind of SRAM, it has a plurality of SRAM memory cell of carrying out addressing with bit line, and these SRAM memory cell comprise:
One height is with reference to an electric potential contact and a low reference potential contact;
One charge-storage node;
One pull-down transistor, it is connected to this charge-storage node and should hangs down the reference potential contact, and this pull-down transistor has one source pole, a drain electrode and a pull-down transistor grid; And
One transfering transistor, it is connected to this charge-storage node and a bit lines, and this transfering transistor has one source pole, a drain electrode and a transfer transistor gate,
It is characterized in that transfer transistor gate has a lower surface, this lower surface is bent with respect to the lower surface of the grid of this pull-down transistor.
2, SRAM as claimed in claim 1 is characterized in that, the lower edge of this transfer transistor gate is set on the surface of a substrate with the position higher than the lower edge of this pull-down transistor grid.
3, SRAM as claimed in claim 2, it is characterized in that, the lower edge of this transfer transistor gate is set on the surface of this substrate with enough height, make the electric field that transfering transistor produced that has smooth bottom electrode than, it can change formed electric field in this transfering transistor one channel region, in order to change the mutual conductance of this transfering transistor.
4, SRAM as claimed in claim 2 is characterized in that, the lower edge of this transfer transistor gate is left the substrate surface of the channel region part of this transfering transistor by lifting, and the degree of its lifting is greater than the core at the lower surface of this transfer transistor gate.
5, a kind of SRAM, it has a plurality of SRAM memory cell with the bit line addressing, and these SRAM memory cell comprise:
One height is with reference to an electric potential contact and a low reference potential contact;
One charge-storage node;
One pull-down transistor, it is connected to this charge-storage node and should hangs down the reference potential contact, and this pull-down transistor has one source pole, a drain electrode and a pull-down transistor grid; And
One transfering transistor, it is connected to this charge-storage node and a bit lines, and this transfering transistor has one source pole, a drain electrode, a passage and a transfer transistor gate,
It is characterized in that this transfer transistor gate is arranged to produce the electric field of a specified configuration in the channel region of this transfering transistor, this electric field that is wherein produced in channel region and then the source electrode of transfering transistor with the drain electrode part lowered intensity.
6, a kind of method of making SRAM is characterized in that, this method comprises the steps:
One substrate is provided and is formed at this suprabasil lead that is made of doped polycrystalline silicon, wherein one first lead is formed on the channel region of a pull-down transistor, and one second lead is formed on the channel region of a transfering transistor;
Cover this first lead in a kind of mode of protecting this first lead to avoid oxidation; And
This second lead is exposed in the oxidation environment, and this then crested of first lead is so that this first and second lead has different cross-sectional configuration;
At least one below part of this first and second lead is a doped polycrystalline silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN96112726A CN1068459C (en) | 1996-10-14 | 1996-10-14 | Static random access storage and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN96112726A CN1068459C (en) | 1996-10-14 | 1996-10-14 | Static random access storage and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1180246A CN1180246A (en) | 1998-04-29 |
| CN1068459C true CN1068459C (en) | 2001-07-11 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96112726A Expired - Fee Related CN1068459C (en) | 1996-10-14 | 1996-10-14 | Static random access storage and its manufacturing method |
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| Country | Link |
|---|---|
| CN (1) | CN1068459C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100352163C (en) * | 2002-12-18 | 2007-11-28 | 中颖电子(上海)有限公司 | Static selection circuit with high reliability and cow-power consumption |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG115742A1 (en) * | 2004-04-05 | 2005-10-28 | Taiwan Semiconductor Mfg | Sram device having high aspect ratio cell boundary |
| US8773940B2 (en) * | 2012-01-17 | 2014-07-08 | Freescale Semiconductor, Inc. | Skewed SRAM cell |
| US8514007B1 (en) | 2012-01-27 | 2013-08-20 | Freescale Semiconductor, Inc. | Adjustable power splitter and corresponding methods and apparatus |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4118642A (en) * | 1975-06-26 | 1978-10-03 | Motorola, Inc. | Higher density insulated gate field effect circuit |
| JPS6226859A (en) * | 1985-07-29 | 1987-02-04 | Tdk Corp | Vertical semiconductor device and manufacture thereof |
| CN1043587A (en) * | 1985-05-01 | 1990-07-04 | 得克萨斯仪器公司 | Vlsi static random access memory |
| JPH053299A (en) * | 1991-02-08 | 1993-01-08 | Nec Corp | Static memory |
-
1996
- 1996-10-14 CN CN96112726A patent/CN1068459C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4118642A (en) * | 1975-06-26 | 1978-10-03 | Motorola, Inc. | Higher density insulated gate field effect circuit |
| CN1043587A (en) * | 1985-05-01 | 1990-07-04 | 得克萨斯仪器公司 | Vlsi static random access memory |
| JPS6226859A (en) * | 1985-07-29 | 1987-02-04 | Tdk Corp | Vertical semiconductor device and manufacture thereof |
| JPH053299A (en) * | 1991-02-08 | 1993-01-08 | Nec Corp | Static memory |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100352163C (en) * | 2002-12-18 | 2007-11-28 | 中颖电子(上海)有限公司 | Static selection circuit with high reliability and cow-power consumption |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1180246A (en) | 1998-04-29 |
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