CN106843127A - A kind of Medium PLC system - Google Patents
A kind of Medium PLC system Download PDFInfo
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- CN106843127A CN106843127A CN201710110108.XA CN201710110108A CN106843127A CN 106843127 A CN106843127 A CN 106843127A CN 201710110108 A CN201710110108 A CN 201710110108A CN 106843127 A CN106843127 A CN 106843127A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/11—Plc I-O input output
- G05B2219/1136—Canbus
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
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Abstract
The invention discloses a kind of Medium PLC system, including processor, processor includes a CPU, the 2nd CPU and FPGA, CPU operation linux system softwares, Manage Peripheral Device, treatment communication data and is interacted with host computer；PLC software systems are run in 2nd CPU, PLC user programs, administration extensions module is performed and is carried out motion control trajectory planning；FPGA is responsible for motion control instruction execution, local IO management, expansion bus management and EtherCat protocol analysis.Medium PLC system power dissipation of the invention is small, systematic function is good, the construction cycle is short, and product cost is relatively low.
Description
[technical field]
The present invention relates to programmable logic controller (PLC), more particularly to a kind of Medium PLC system.
[background technology]
With the hair at full speed of electronic technology, computer technology, communication network control technology and industrial automatic control technology
Open up and become increasingly popular, in industrial control system field, the programmable logic controller (PLC) (PLC) for being born in the sixties in last century
Function is become stronger day by day, and is developed towards the extensive PLC system of networking via traditional unit PLC control/network services, in-orbit
Have there are more than the 10000 points application demands of extensive PLC system in the fields such as road traffic, petrochemical industry.
Medium PLC is except with the function such as basic operation ability, i.e. logical operation, timing, counting, displacement, typically also having
There are integer and floating-point operation, number system transition, PID regulations, interruption control and network savvy, can be used for the logical operation of complexity and close
Ring controls occasion.Part Medium PLC can also carry out matrix operation and functional operation, data management work be completed, with stronger
Data processing, analog regulation, specific function functional operation, monitoring, record, printing, communication networking, interrupt control, intelligence control
The function such as system and remote control, can constitute distributed production process comprehensive control management system with other computers.
Because Medium PLC system is to the arithmetic speed of CPU, the data throughout of bus bandwidth, interrupt response time delay, task
The key indexs such as dispatching cycle have the requirement of harshness, and the solution of common embedded system is difficult to be competent at.Medium PLC system
, except requiring high serial data operational capability, because system bandwidth is higher, the data throughout in the monocycle is high for system, because
This is higher to parallel processing capability requirement.
Under normal circumstances, Medium PLC system is all cooperated using discrete multiprocessor, and computing, instruction are performed, communication
The tasks such as task treatment, motion control, expansion module management are responsible for by different processors respectively, the communication between multiprocessor
Expense is larger, and the complexity of system hardware and software is very high.
Traditional Medium PLC system has the following disadvantages：
Due to the serial arithmetic characteristic of ordinary processor, traditional uniprocessor framework be difficult to and meanwhile meet high-speed computation,
The multinomial harsh demands such as high bandwidth, quick response are interrupted, task switching is timely, extension periodic refreshing, accurate motion control；
Connection signal between multiple processor structure processor and processor is very more, and hardware circuit design is extremely complex,
Hardware reliability is substantially reduced；
Communication overhead between multiple processor structure processor and processor is very big, and the communication bandwidth between processor has
Limit, it is difficult to meet demand；The significance arithmetic load of system is relatively low, and Software for Design is extremely complex, and system reliability drops significantly
It is low；
Hardware system be difficult to carry the high-throughputs such as the popular communication protocol of industrial circle, particularly EtherCat,
The minimum EPA communication of communication delay.
[content of the invention]
The technical problem to be solved in the present invention is to provide that a kind of system power dissipation is low, systematic function is good, the construction cycle is short, product
The Medium PLC system of low cost.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention is, a kind of Medium PLC system, including treatment
Device, processor includes a CPU, the 2nd CPU and FPGA, CPU operation linux system softwares, Manage Peripheral Device, treatment communication
Data and interacted with host computer；PLC software systems are run in 2nd CPU, PLC user programs, administration extensions module is performed and is entered
Row motion control trajectory planning；FPGA is responsible for motion control instruction execution, local IO management, expansion bus management and EtherCat
Protocol analysis.
Above-described Medium PLC system, the high speed AXI buses between a CPU and the 2nd CPU by 128 bit wides are mutual
Connection.
Above-described Medium PLC system, including Ethernet interface, USB interface, RS485 interfaces, SD card interface, high speed
I/O interface and CAN interface, Ethernet interface, USB interface, RS485 interfaces, SD card interface, high-speed I/O interface and CAN interface connect
One CPU.
Above-described Medium PLC system, including DDR3 memories and Qspi Flsh memories, the mounting of DDR3 memories
Under the DDR controller of Altera SoC processors, code and data storage are performed as a CPU and the 2nd CPU, while
As a CPU and the buffer area of the 2nd CPU interaction datas；Qspi flash storages are articulated in Altera SoC processors
Under Flash controllers, for storing all of systems soft ware, system bootstrap routine is deposited from Qspi Flash automatically after system electrification
Loading system software in reservoir.
Above-described Medium PLC system, FPGA includes motion-control module, expansion bus protocol resolution module, communication
Protocol resolution module, I/O interface module and cpu i/f module；Motion-control module receive the movement locus that issues of the 2nd CPU and
Speed, acceleration, acceleration and between centers interpolation relation data, carry out the accurate planning of movement velocity, movement locus, and control
Multiple axles are while single step or cooperative motion, the current motion state of feedback locating shaft, carry out abnormality processing；Expansion bus agreement solution
Analysis module in system electrification by expansion bus to expansion module address, then after the configuration information for receiving the 2nd CPU according to
The secondary configuring area for configuring each expansion module makes its normal work, just by periodic refresh expansion module workspace after the completion of configuration
Data, read in the RAM buffer areas that the last state of expansion module is stored in FPGA for the 2nd CPU；I/O interface module tubes
The local I/O interface of processor is managed, input and output filtering is carried out, or initiates to interrupt to the 2nd CPU；Cpu i/f module is responsible for
FPGA and a CPU, the data interaction of the 2nd CPU, peripheral hardware Sharing Management.
Above-described Medium PLC system, including expansion module and expansion bus, expansion module include I/O expansion module,
Locating shaft expansion module, high-speed counting expansion module, AD/DA special functional modules and communication extension module；Expansion bus is used
High-speed-differential Qspi buses combine single addressing line, line synchro and reset line composition, and expansion bus is managed by FPGA.
Above-described Medium PLC system, described processor is Altera SoC processors.
Medium PLC system power dissipation of the invention is small, systematic function is good, the construction cycle is short, and product cost is relatively low.
[brief description of the drawings]
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description.
Fig. 1 is the structured flowchart of embodiment of the present invention Medium PLC system.
[specific embodiment]
The embodiment of the present invention as shown in figure 1, be the Medium PLC system based on Altera SoC frameworks, using AMP schemes；
CPU1 operation linux systems in two ARM cores of HPS sides, main Manage Peripheral Device, treatment communication data and host computer are handed over
Mutually etc.；PLC software systems are run in CPU2, it is main to perform PLC user programs, administration extensions module, carry out motion control rail
Mark planning etc.；FPGA sides are substantially carried out motion control instruction execution, local IO management, expansion bus management, EtherCat agreements
Parsing.
The Medium PLC system of the embodiment of the present invention includes ALTERA SOC processors and high-speed expansion module, ALTERA
It is connected by high speed spi buses between SOC processors and expansion module, ALTERA SOC processors are provided to high-speed expansion module
Working power, ALTERA SOC processors manage all expansion modules being articulated in bus as main website, at most may be used in bus
32 high-speed expansion modules of mounting.ALTERA SOC processors be integrated with two Cortex-A9 ARM kernels CPU1, CPU2 and
One FPGA, by the high speed AXI bus bars of 128 bit wides between kernel CPU1 and CPU2.
CPU1 runs (SuSE) Linux OS, the user program of runtime level, Manage Peripheral Device, treatment serial ports, CAN mouthful it is logical
Letter data, (user program up/down load, monitoring, online modification), record system operation information etc. are interacted with host computer；CPU2 is transported
Row PLC kernels, are responsible for the execution of PLC user programs, logical process, expansion module management, motion control trajectory planning；DDR3 is mounted
Under the DDR controller of Soc chips, as the execution code and data storage of CPU1, CPU2, while as CPU1 and CPU2
The buffer area of interaction data；Qspi Flash are articulated under the Flash controllers of Soc chips, soft for storing all of system
Part (includes Preloader, u-boot, DeviceTree, linux kernel and file system, PLC kernels, FPGA softwares), system
The automatic loading system software from Qspi Flash of system bootstrap routine after upper electricity；SD card is articulated in the SD card control of Soc chips
Under device, it is mainly used to storage system daily record, PLC user programs, user data etc.；USB port is articulated in the USB controls of Soc chips
Under device, it is mainly used to be interacted with host computer (user program up/down load, monitoring, online modification)；Two Ethernet interfaces are mounted respectively
Under two mac controllers, mac controller is realized by hardware description language in the hard wire logic of FPGA sides, is mainly used to
EPA communication protocol is realized, EtherCat, EtherNet/ can be realized with timesharing by the part reconfiguration technology of FPGA
The agreements such as IP, ProfiNet, MODBUS TCP；Serial ports and the CAN mouthfuls of peripheral hardware as ARM, serial ports be mainly used to realize Free,
MODBUS communicates, and CAN mouthfuls is mainly used to realize Free, CANOPEN communications.
The core circuit of Altera SoC processor FPGA sides includes motion-control module, expansion bus protocol analysis mould
Block, communication protocol parsing module, I/O interface module, cpu i/f module；Motion-control module receives the fortune that ARM side CPU2 are issued
The data such as dynamic rail mark and speed, acceleration, acceleration, between centers interpolation relation, carry out the accurate rule of movement velocity, movement locus
Draw, and control multiple axles single step or cooperative motion simultaneously, the current motion state of feedback locating shaft carries out abnormality processing；Extension
Bus protocol analysis module in system electrification by expansion bus to expansion module address, then receive CPU2 with confidence
The configuring area for configuring each expansion module after breath successively makes its normal work, and periodic refresh expansion module work is just pressed after the completion of configuration
Make the data (reading or writing) in area, read for CPU2 in the RAM buffer areas that the last state of expansion module is stored in FPGA；IO
Interface module manages the local IO of ALTERA SOC processors, carries out input and output filtering, or initiates to interrupt to CPU2；CPU
Interface module is responsible for data interaction, peripheral hardware Sharing Management of FPGA and CPU1, CPU2 etc.；
Altera SoC processors use part reconfiguration technology, by ARM sides part weight in the case of system is unbroken
Configuration FPGA, realizes support (such as EtherCat, EtherNet/IP, ProfiNet, MODBUS TCP to different communication protocol
Deng)；
As a universal product, it is necessary to meet various differentiated demands.Expansion module is mainly used as Function Extension, comprising
I/O expansion module, locating shaft expansion module, high-speed counting expansion module, AD/DA special functional modules, communication extension module (bag
Include serial ports, CAN, Ethernet) etc..The system combines single addressing line, line synchro, reset line conduct using high-speed-differential Qspi buses
Expansion bus, by FPGA administration extensions buses, dynamic addressing, failure is broken from whole, and minimum refresh cycle 1us, expansion bus refreshes
The PLC scan periods are not take up, PLC user programs are greatly improved and is performed speed.
The Altera SoC chips that above example of the present invention is used are interconnected using broadband main line, integrated in FPGA architecture
Hard nucleus management device system (HPS) based on ARM, hard nucleus management device system includes processor, peripheral hardware and memory interface, FPGA
In integrated discrete processors and Digital Signal Processing (DSP) function, reduce system power dissipation and cost, reduce board area；HPS
Big throughput data path and FPGA architecture between realizes the interconnection performance that dual chip solution cannot be provided.FPGA framves
The peak bandwidth for being closely integrated support 100-Gbps of framework structure, realizes the uniformity of data.Between processor and FPGA not
Exterior I/O paths are needed, system power dissipation is considerably reduced.
Fpga logic framework in the Altera Soc chips that above example of the present invention is used, can rapidly adapt to various
The change of interface and communication protocol standard, increases custom hardware in FPGA, accelerates the algorithm higher to time requirement, rapid real
Arm processor is now customized, there is no ASIC designs expensive like that, checking and flow (NRE) cost, greatly improve systematicness
Energy；
Above example of the present invention realizes asymmetric multiprocessing (AMP) system schema based on Altera Soc technologies,
The parallel running of two operating systems and FPGA user logics is realized on single-chip, full parellel computing is truly realized, fully
The potential of Altera Soc has been excavated, rigors of the Medium PLC system to performance have been fully met；
Above example of the present invention uses Altera Soc schemes, and hardware complexity is greatly reduced while improving performance
With software systems complexity, the construction cycle is shortened, reduce product cost.
Above example of the present invention solves the demand of traditional Medium PLC implacable higher performance of embedded scheme,
The solution for integrating multiprocessor for customizing, significant increase intercore communication bandwidth, by hardware-accelerated algorithm are provided
The arithmetic speed of processor is greatly improved, high-speed computation, high bandwidth, quick response interruption, the task of Medium PLC system is met
The multinomial harsh demands such as switching is timely, extension periodic refreshing, accurate motion control；
It is extremely complex that above example of the present invention solves multicomputer system hardware design using Altera Soc technologies
Problem, two ARM cores, peripheral hardware, memory interface and FPGA are integrated on single-chip, and core circuit design is very simple, greatly
Reduce board area greatly；
Above example of the present invention uses Altera Soc technologies, by asymmetric multiprocessor system system schema, using height
Fast memory carries out intercore communication, the superfast bus in coupling system inside so that internuclear interaction becomes very simple, and communication is opened
Pin is substantially reduced, and software complexity is substantially reduced；
Above example of the present invention uses Altera Soc technologies, using fpga logic framework therein, can fit rapidly
The change of various interfaces and communication protocol standard is answered, various instantly popular industrial ethernet protocols is easily supported, such as
EtherCat, EtherNet/IP and MODBUS/TCP etc..
Claims (7)
1. a kind of Medium PLC system, it is characterised in that including processor, processor includes a CPU, the 2nd CPU and FPGA,
First CPU runs linux system software, and Manage Peripheral Device, treatment and are interacted communication data with host computer；PLC is run in 2nd CPU
Software systems, perform PLC user programs, administration extensions module and carry out motion control trajectory planning；FPGA is responsible for motion control
Instruction is performed, local IO is managed, expansion bus is managed and EtherCat protocol analysis.
2. Medium PLC system according to claim 1, it is characterised in that pass through 128 between a CPU and the 2nd CPU
High speed AXI bus bars wide.
3. Medium PLC system according to claim 1, it is characterised in that including Ethernet interface, USB interface, RS485
Interface, SD card interface, high-speed I/O interface and CAN interface, Ethernet interface, USB interface, RS485 interfaces, SD card interface, high speed
I/O interface and CAN interface meet a CPU.
4. Medium PLC system according to claim 1, it is characterised in that deposited including DDR3 memories and Qspi Flash
Reservoir, DDR3 memories are articulated under the DDR controller of Altera SoC processors, and generation is performed as a CPU and the 2nd CPU
Code and data storage, while as a CPU and the buffer area of the 2nd CPU interaction datas；Qspi flash storages are mounted
Under the Flash controllers of Altera SoC processors, for storing all of systems soft ware, System guides journey after system electrification
The automatic loading system software from Qspi flash storages of sequence.
5. Medium PLC system according to claim 1, it is characterised in that FPGA includes motion-control module, expansion bus
Protocol resolution module, communication protocol parsing module, I/O interface module and cpu i/f module；Motion-control module receives the 2nd CPU
Movement locus and speed, acceleration, acceleration and the between centers interpolation relation data for issuing, carry out movement velocity, movement locus
Accurate planning, and control multiple axles single step or cooperative motion simultaneously, the feedback current motion state of locating shaft carries out exception
Reason；Expansion bus protocol resolution module is addressed by expansion bus in system electrification to expansion module, is then receiving second
The configuring area for configuring each expansion module after the configuration information of CPU successively makes its normal work, is just brushed by the cycle after the completion of configuration
The data of new expansion module workspace, supply the 2nd CPU in the RAM buffer areas that the last state of expansion module is stored in FPGA
Read；The local I/O interface of I/O interface module management processor, carries out input and output filtering, or initiates to interrupt to the 2nd CPU；
Cpu i/f module is responsible for FPGA and a CPU, the data interaction of the 2nd CPU, peripheral hardware Sharing Management.
6. Medium PLC system according to claim 1, it is characterised in that including expansion module and expansion bus, expanded mode
Block includes I/O expansion module, locating shaft expansion module, high-speed counting expansion module, AD/DA special functional modules and communication extension
Module；Expansion bus combines single addressing line, line synchro and reset line composition using high-speed-differential Qspi buses, expansion bus by
FPGA is managed.
7. Medium PLC system according to claim 1, it is characterised in that described processor is Altera SoC treatment
Device.
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Cited By (8)
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| CN108710587A (en) * | 2018-06-04 | 2018-10-26 | 中国电子科技集团公司第十四研究所 | Signal processing FPGA general procedures architecture system based on AXI buses and method |
| CN109412897A (en) * | 2018-11-15 | 2019-03-01 | 紫光测控有限公司 | System and method is realized based on the shared MAC of multi-core processor and FPGA |
| CN109932997A (en) * | 2019-03-01 | 2019-06-25 | 中安智联未来有限公司 | A kind of programmable logic controller (PLC) core system |
| CN111198698A (en) * | 2018-11-16 | 2020-05-26 | 上海安浦鸣志自动化设备有限公司 | EtherCAT-based multi-device firmware program parallel downloading method and system |
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| CN113075902A (en) * | 2020-05-18 | 2021-07-06 | 格联(上海)物联技术有限公司 | PLC data acquisition device |
| CN113760816A (en) * | 2021-09-07 | 2021-12-07 | 中国电力科学研究院有限公司 | RISC-VCPU and AI core heterogeneous communication system and design method |
| CN114460898A (en) * | 2022-01-26 | 2022-05-10 | 无锡信捷电气股份有限公司 | CodeSys-based external extension module component design method and system |
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| CN109412897A (en) * | 2018-11-15 | 2019-03-01 | 紫光测控有限公司 | System and method is realized based on the shared MAC of multi-core processor and FPGA |
| CN109412897B (en) * | 2018-11-15 | 2021-12-21 | 清能华控科技有限公司 | Shared MAC (media Access control) implementation system and method based on multi-core processor and FPGA (field programmable Gate array) |
| CN111198698A (en) * | 2018-11-16 | 2020-05-26 | 上海安浦鸣志自动化设备有限公司 | EtherCAT-based multi-device firmware program parallel downloading method and system |
| CN109932997A (en) * | 2019-03-01 | 2019-06-25 | 中安智联未来有限公司 | A kind of programmable logic controller (PLC) core system |
| CN109932997B (en) * | 2019-03-01 | 2021-09-28 | 中安智联未来有限公司 | Programmable logic controller kernel system |
| CN111708329A (en) * | 2020-05-18 | 2020-09-25 | 武汉华中数控股份有限公司 | Intelligent numerical control system and method |
| CN113075902A (en) * | 2020-05-18 | 2021-07-06 | 格联(上海)物联技术有限公司 | PLC data acquisition device |
| CN113760816A (en) * | 2021-09-07 | 2021-12-07 | 中国电力科学研究院有限公司 | RISC-VCPU and AI core heterogeneous communication system and design method |
| CN114460898A (en) * | 2022-01-26 | 2022-05-10 | 无锡信捷电气股份有限公司 | CodeSys-based external extension module component design method and system |
| CN114460898B (en) * | 2022-01-26 | 2024-05-17 | 无锡信捷电气股份有限公司 | CodeSys-based external expansion module component design method and CodeSys-based external expansion module component design system |
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