CN106803750A - A kind of multichannel flowing water FIR filter - Google Patents
A kind of multichannel flowing water FIR filter Download PDFInfo
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- CN106803750A CN106803750A CN201710022449.1A CN201710022449A CN106803750A CN 106803750 A CN106803750 A CN 106803750A CN 201710022449 A CN201710022449 A CN 201710022449A CN 106803750 A CN106803750 A CN 106803750A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H2017/0072—Theoretical filter design
- H03H2017/0081—Theoretical filter design of FIR filters
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Abstract
The present invention discloses a kind of multichannel flowing water FIR filter, including passage merges device, zero level filter unit, the general filter unit of several series connection and passage detachment device, and M roads input data is merged into after merging device through the passage and exported all the way；The output signal all the way of zero level filter unit enters buffering shift unit, it is buffered to be displaced into the second multiplier, output signal with the second coefficient memory units carries out multiplying, result is exported to multiplication output register group, signal after delay is added with another road output signal of zero level filter unit through adder, then exports addition output register group；Passage detachment device, for extracting parallel M circuit-switched datas output from serial filtering signal.Operation efficiency of the present invention is high, supports that input data interrupts transmission, and cascade system is simple, and exponent number is easy to extension, highly versatile.
Description
Technical field
The present invention relates to wave filter technology field, more particularly to a kind of multichannel flowing water FIR filter.
Background technology
As the fields such as radar, communication are continuously increased to the demand of broadband system, wideband digital array-processing techniques are wide
General application.For wideband digital array system, in order to compensate the mismatch of interchannel frequency response, it is necessary to connect in each channel
One digital FIR equalization filter so that the frequency response of all passages is consistent.To ensure system real time, digital FIR is balanced
Wave filter is generally realized by FPGA or special ASIC.
Traditional N ranks FIR time domains realize pipeline computing usually through N number of adder and multiplier of series connection, and dominant frequency and the input of adder and multiplier have
Effect data transfer rate is consistent.But because the actual data rate of digital array is different because of system, with developing rapidly for integrated circuit,
The dominant frequency more and more higher of FPGA especially ASIC, the work dominant frequency of typical ASIC may be up to more than 1GHz, actually enter data
Rate only hundred M magnitudes, it is typical such as 200M.Clearly for the adder and multiplier for being operated in 1GHz dominant frequency, in treatment 200MHz input datas
When, the time for having 80% is in idle condition, and operation efficiency is extremely low.Therefore, it is necessary to time-sharing multiplex principle is based on, design one
Multichannel flowing water FIR filter is planted, realizes that the timesharing of multiple passage FIR filtering is calculated, so as to give full play to high workload dominant frequency
Advantage, improves operation efficiency.
The content of the invention
The present invention provides a kind of multichannel flowing water FIR filter (MCP-FIR, Multi-Channel Pipeline
FIR), and develop simultaneously be applied to FPGA and special ASIC MCP-FIR filter modules.Purpose is according to work dominant frequency and reality
The relation of border input data rate, is calculated by one group of timesharing of high primary frequency adder and multiplier, completes the flowing water FIR filtering of multiple passages,
Port number can dynamic configuration.
A kind of multichannel flowing water FIR filter, merges device, zero level filter unit, several series connection including passage successively
General filter unit and passage detachment device, M roads input data merges into and exports all the way after merging device through the passage, M
It is the integer more than or equal to 1；The zero level filter unit includes the first multiplier, coefficient of zero order memory cell, the first input
Register group, the first output register group and the first control register group, the coefficient of zero order memory cell and input register
The output signal of group is multiplied as the input of the multiplier, as a result into output register group；The general filtering is single
Unit includes that the second multiplier, first adder, buffering shift unit, the second coefficient memory units, multiplication output register, addition are defeated
Go out register group and the second control register group, the output signal all the way of the zero level filter unit enters the buffering displacement
Device, buffered to be displaced into second multiplier, the output signal with second coefficient memory units carries out multiplication fortune
Calculate, as a result export to multiplication output register group, another road output signal of the signal after delay and the zero level filter unit
It is added through the adder, then is exported addition output register group；The addition output register group and the buffering
The output signal of shift unit enters next general filter unit, cascades successively；The passage detachment device, for from serial
Parallel M circuit-switched datas output is extracted in filtering signal.
The coefficient memory units are register file or RAM, but are not limited to both the above storage organization；
The multiplier includes but is not limited to fixed point real multipliers, pinpoints complex multiplier, floating point real number multiplier, floats
Any one of point complex multiplier.
Present invention produces following beneficial effect：
1st, under the conditions of high workload dominant frequency low data-rate applications, using a multiply-add resource for FIR filter, timesharing is completed
The flowing water FIR filtering operations of individual multiple input channels, operation efficiency is high；
2nd, input/output interface meets the standard AXI4-Stream interfaces of non-obstruction, supports that input data interrupts transmission；
3rd, realize N ranks FIR and filter calculating, level by 1 zero level filter unit and the N-1 of cascade general filter unit
Connection mode is simple, and exponent number is easy to extension；
4th, port number can be with dynamic configuration, it is adaptable to different application scenarios, highly versatile.
Brief description of the drawings
Fig. 1 is multichannel flowing water FIR filter structure block diagram of the present invention；
Fig. 2 is zero level filter unit structure chart in the embodiment of multichannel flowing water FIR filter one；
Fig. 3 is general filter unit structure chart in multichannel another embodiment of flowing water FIR filter；
Fig. 4 is the working timing figure of the rank FIR filter of 3 passage of another embodiment 16.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
M channel data timesharing of parallel input is merged into all the way first, then using 1 zero level filter unit and level
N-1 general filter unit of connection carries out the flowing water N rank FIR filtering operations of multichannel to the circuit-switched data, and N number of multiplier is consumed altogether
With N-1 adder, operation result timesharing is finally split into M channel parallel output, structured flowchart is as shown in Figure 1.Wherein,
S_axi_data_i is the i-th tunnel input data, and m_axi_data_i is the i-th tunnel output data after the completion of calculating, i=0,1 ...
M-1, input/output interface meets the standard AXI4-Stream interfaces of non-obstruction, and port number M can be by input interface s_M_
Value dynamic configurations.
If the coefficient of the N rank FIR filters on the i-th tunnel is hn(i, j), input data be D (i, k), output result be Q (i,
K), then after completing the M N ranks FIR filtering of passage using MCP-FIR, can obtain：
Wherein, j=0,1 ..., N-1, k=0,1 ..., K+N-1, K are the total points of input.
The function of each module in MCP-FIR inside is described as follows：
(1) passage merges
Passage merges device to be used to complete parallel-serial conversion, and the data timesharing of the M passage that will be input into parallel is merged into one
Road exports.If input data rate is fin, work dominant frequency fwork, wherein the dominant frequency satisfaction that works：fwork≥M*fin.To per all the way
Data are respectively provided with shift register, and the i-th tunnel shifts i efficient clock cycle, and (corresponding clock is all when s_axi_valid is effective
Phase is referred to as the efficient clock cycle, similarly hereinafter, is not shifted when s_axi_valid is invalid), then M ways from after displacement
Select to export according to middle poll so that in k-th efficient clock cycle output kth %M (% represents complementation, similarly hereinafter) circuit-switched data, its
In, i=0,1 ..., M-1, k=0,1 ....
(2) zero level filter unit
Zero level filter unit includes the first multiplier, coefficient of zero order memory cell, the first input register group, the first output
Register group and the first control register group.Structured flowchart is as shown in Figure 2.
Coefficient memory units include M data register, and the 1st rank FIR systems of correspondence M roads input data are deposited respectively
Number, when k-th valid data is reached, the FIR filter on selection correspondence kth %M roads is exported to multiplier, k=0,1 ....First
Multiplier then completes the multiplying of data and FIR filter.
Register group then realizes the delay to input data difference series by different register numbers, is mainly used in zero
Level filter unit and general filter unit cascade when valid data alignment, it is ensured that two-way output meet general filter unit when
Sequence requirement.
(3) general filter unit
General filter unit includes the second multiplier, first adder, buffers shift unit, the second coefficient memory units, multiplies
Method output register, addition output register group and the second control register group.Structured flowchart is as shown in Figure 3.
The function of coefficient memory units, multiplier and register group is identical with zero level filter unit.
Buffering shift unit is mainly used in realizing interrupting transfer function, when work dominant frequency and actual data rate an odd lot are closed again
System or data transfer rate are lowered when using, and the data after passage merges occur invalid situation, are caused to interrupt and are transmitted.Buffering is moved
Position device is controlled to be shifted into row buffering by the s_axi_valid_1 being input into, and when s_axi_valid_1 is effective, function is equivalent to M+1
The shift register of level, when s_axi_valid_1 is invalid, can latch current shift state, and next clock cycle immediately
The current invalid data of output, continues to shift until s_axi_valid_1 is again effectively rear.Multiplication is given in the output of buffer
Device, while as m_axi_data_1 outputs to next stage.
Adder is used to complete the add operation that multiplier output result is input into s_axi_data_2 with prime, addition results
Exported as the m_axi_data_2 when prime.The adder output of N-1 grades of general filter unit is M passage N ranks FIR
Filtered operation result.
(4) passage splits
Passage detachment device is used to complete serioparallel exchange, i.e., extracted from M serial passage FIR filter result parallel
M circuit-switched datas output.First carry out the displacement of M roads respectively to input data, the i-th tunnel shifts M-i-1 efficient clock cycle, in kth
The individual clock cycle, result is exported simultaneously after as k%M=M-1, M roads are shifted, wherein, i=0,1 ..., M-1, k=0,1 ....
Realized by following steps using the N grades of FIR filtering of M passage of above structure：
First, current channel number M is configured, then, M channel data is input into by the non-obstruction AXI interfaces of standard, and passage is closed
And device carries out parallel-serial conversion, M channel data timesharing is merged into and is exported all the way；
Secondly, the data of merging carry out N-1 grades of general filter unit of zero level filter unit and cascade successively, complete M and lead to
The input data in road and the multiply-add operation of respective channel FIR filter, obtain FIR operation results；
Finally, serial conversion is completed by passage detachment device, M channel data is isolated in chronological order defeated parallel
Go out.
The M N rank flowing water FIR of passage is calculated under realizing low data rate using the adder and multiplier of N number of high primary frequency, operation efficiency
It is high；FIR calculating is carried out by the way of 1 zero level filter unit and N-1 general filter unit cascade, is realized complete pipelining
Can, and cascade system is simple, exponent number easily extends；Buffering displacement mechanism, it is ensured that when input data it is invalid and effectively between saltus step
When, adder and multiplier can correctly be recognized and process valid data, realize the function that can interrupt transmission；Port number can dynamic configuration, fit
For different application scene, highly versatile.
According to above technical scheme, in ASIC work dominant frequency 500MHz, input single channel average data rate 160M, exponent number 16
Application demand under, devise the rank flowing water FIR filter of a 3 passage 16, wherein, in zero level filter unit first input deposit
Device group is 1 grade, and the first output register group and the first control register group are 3 grades；Multiplication output deposit in general filter unit
Device group is 2 grades, and addition output register group and the second control register group are 1 grade, and its work schedule schematic diagram is as shown in Figure 4.
Illustrated for ease of sequential, without loss of generality, if the corresponding FIR filter of 3 passages is complete 1, in input data, 1,
4,7 ... is the 1st passage input data, and 2,5,8 ... is the 2nd passage input data, and 3,6,9 ... is the 3rd passage input
Data, 1. represent the output that passage merges, and 2. represent the output of zero level filter unit, and the 1st grade of general filter 3. and is 5. represented respectively
The tunnel of ripple unit 2 exports, and 4. represents the 1st grade of input of general filter unit internal additions device, and 6. and 8. the 2nd grade of expression is general respectively
The tunnel of filter unit 2 exports, and 7. represents the 2nd grade of input of general filter unit internal additions device.
It can be seen that, three passage input datas by after passage merging module, parallel 3 circuit-switched data serial arrangement, timesharing
Output, valid is invalid in the 7th clock cycle, and the 10th clock cycle recovers effective.It is defeated after zero level filter unit completion multiplication
Go out, because the first output register group is 3 grades, therefore 2. relative to 3 clock cycle are 1. delayed, invalid data equally delays 3
The individual clock cycle.Meanwhile, 1. it is directly fed to the 1st grade of general filter unit.
During multiplying in zero level filter unit and general filter unit, the coefficient memory units meeting inside unit
The FIR filter that remainder according to valid data number with 3 takes out corresponding road successively gives multiplier, it is ensured that three tunnel input datas are just
Really corresponding FIR filter is used.
In the 1st grade of general filter unit, first to 1. entering row buffering displacement, when data are effective, 4 grades of shiftings are directly carried out
Position, when data invalid, latches current shift state, and preferentially exports invalid data in following clock cycle, until the 10th
Clock cycle data recover effective, and following clock cycle continues to start shifting function.3. data after buffering displacement give simultaneously
Internal multiplier and the 2nd grade of general filter unit.4. multiplier output given the adder of inside after 2 grades postpone,
Adder complete 4. with being added 2., and 5. given the 2nd grade of general filter unit after postponing 1 grade.
Working mechanism inside 2nd grade of general filter unit is identical with the 1st grade, is output as 6. to 3. entering row buffering displacement,
Internal multiplier exports and is that 7., internal additions device will 5. and 7. 8. phase adduction obtain after postponing 1 grade, 6. and 8. after postponing 2 grades
Continue to deliver to 3rd level filter unit.
The like, the 15th grade of filter unit output is 16 rank FIR filter results of 3 tunnel input datas, then by logical
Road splits module and completes serioparallel exchange, and 3 circuit-switched datas are separated in chronological order, and the parallel result of 3 passages required for obtaining is defeated
Go out.
Last data of the s_axi_last characterizations of input currently input, the signal will be filtered according to every one-level
Real data length of delay inside unit carries out the displacement of respective cycle, final to ensure that output m_axi_last characterizes output FIR
Last result of computing.
Technological means disclosed in the present invention program is not limited only to the technological means disclosed in above-mentioned implementation method, also includes
Constituted technical scheme is combined by above technical characteristic.
Claims (3)
1. a kind of multichannel flowing water FIR filter, it is characterised in that：If successively include passage merge device, zero level filter unit,
Dry the general filter unit connected and passage detachment device, M roads input data merge into one after merging device through the passage
Road exports, and M is the integer more than or equal to 1；The zero level filter unit include the first multiplier, coefficient of zero order memory cell,
First input register group, the first output register group and the first control register group, the coefficient of zero order memory cell and defeated
The output signal for entering register group is multiplied as the input of the multiplier, as a result into output register group；It is described logical
Include that the second multiplier, first adder, buffering shift unit, the second coefficient memory units, multiplication export deposit with filter unit
Device, addition output register group and the second control register group, the output signal all the way of the zero level filter unit enter described
Buffering shift unit, buffered to be displaced into second multiplier, the output signal with second coefficient memory units is entered
Row multiplying, as a result exports to multiplication output register group, another road of the signal after delay and the zero level filter unit
Output signal is added through the adder, then exports addition output register group；The addition output register group and
The output signal of the buffering shift unit enters next general filter unit, cascades successively；The passage detachment device, is used for
Parallel M circuit-switched datas output is extracted from serial filtering signal.
2. multichannel flowing water FIR filter according to claim 1, it is characterised in that：The coefficient memory units are to post
Register file or RAM.
3. multichannel flowing water FIR filter according to claim 1, it is characterised in that：The multiplier is fixed point real number
Any one of multiplier, fixed point complex multiplier, floating point real number multiplier, floating-point complex multiplier.
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Cited By (7)
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| CN108900177A (en) * | 2018-06-14 | 2018-11-27 | 福建星海通信科技有限公司 | A kind of FIR filter and its method that data are filtered |
| CN109120241A (en) * | 2017-06-23 | 2019-01-01 | 北京遥感设备研究所 | A kind of real number chiasma type complex coefficient FIR filter |
| CN109412556A (en) * | 2018-10-25 | 2019-03-01 | 天津光电通信技术有限公司 | A kind of multidiameter delay data FIR filter achieving method based on FPGA |
| CN112039495A (en) * | 2020-08-31 | 2020-12-04 | 电子科技大学 | Floating-point number FIR digital filter and design method thereof |
| CN113095495A (en) * | 2021-03-29 | 2021-07-09 | 上海西井信息科技有限公司 | Control method of convolutional neural network module |
| CN114978210A (en) * | 2022-04-13 | 2022-08-30 | 中国人民解放军军事科学院国防科技创新研究院 | Digital channelized receiving device |
| CN115085693A (en) * | 2022-06-30 | 2022-09-20 | 成都志诚信通科技合伙企业(有限合伙) | Multi-channel multi-phase interpolation processing architecture |
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| CN109120241A (en) * | 2017-06-23 | 2019-01-01 | 北京遥感设备研究所 | A kind of real number chiasma type complex coefficient FIR filter |
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| CN113095495A (en) * | 2021-03-29 | 2021-07-09 | 上海西井信息科技有限公司 | Control method of convolutional neural network module |
| CN113095495B (en) * | 2021-03-29 | 2023-08-25 | 上海西井科技股份有限公司 | Control Method of Convolutional Neural Network Module |
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| CN115085693A (en) * | 2022-06-30 | 2022-09-20 | 成都志诚信通科技合伙企业(有限合伙) | Multi-channel multi-phase interpolation processing architecture |
| CN115085693B (en) * | 2022-06-30 | 2023-03-14 | 成都志诚信通科技合伙企业(有限合伙) | Multi-channel multi-phase interpolation processing architecture |
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