CN106788424B - Locking indicator based on frequency comparison - Google Patents
Locking indicator based on frequency comparison Download PDFInfo
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- CN106788424B CN106788424B CN201611086921.XA CN201611086921A CN106788424B CN 106788424 B CN106788424 B CN 106788424B CN 201611086921 A CN201611086921 A CN 201611086921A CN 106788424 B CN106788424 B CN 106788424B
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- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 claims description 54
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- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 claims description 10
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- 238000010586 diagram Methods 0.000 description 13
- 230000000630 rising effect Effects 0.000 description 4
- 101150110971 CIN7 gene Proteins 0.000 description 2
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 2
- 101150110298 INV1 gene Proteins 0.000 description 2
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
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Abstract
The invention discloses a locking indicator based on frequency comparison, which comprises: the waveform adjusting unit is used for respectively shaping the reference clock and the VCO clock into a shaped reference clock with a duty ratio of 50% and a shaped VCO clock; an edge frequency discriminator for frequency comparing the shaped reference clock with the shaped VCO clock and outputting a frequency error pulse; the invention realizes the function of the locking indicator by adopting a pure digital circuit, and has the advantages of wide coverage frequency range, low code rate and capability of accurately setting the error range of the locking time frequency.
Description
Technical Field
The present invention relates to a lock indicator, and more particularly, to a lock indicator based on frequency comparison.
Background
A conventional phase comparison type lock indicator is shown in fig. 1, in which two clocks CLK1 and CLK2O pass through a Phase Frequency Detector (PFD), output U and D signals, and pass through an or gate, where the duty ratio of the output (Y) of the or gate represents the phase difference between CLK1 and CLK 2O. This signal is passed through a low pass filter and compared to a reference voltage VREF. If the phase difference between CLK1 and CLK2O is large, the duty cycle of Y will be large and the output Voltage (VIN) after the filter will be high, if VIN > VREF, the lock indicator output is low; if CLK1 is close in phase to CLK2O and VIN < VREF, then the lock indicator output is high. And selecting a proper VREF according to actual conditions, so that the precision of the locking indicator can be adjusted.
However, implementing the lock indicator function in this manner has several problems:
1. the filter can only be designed for a specific frequency and cannot cover all frequency bands.
2. And the error rate is high by judging the locking phase.
3. Other circuitry is required to generate the VREF voltage.
Disclosure of Invention
In order to overcome the defects in the prior art, the present invention provides a locking indicator based on frequency comparison, which realizes the function of the locking indicator by using a pure digital circuit, and has the advantages of wide frequency coverage, low code rate and capability of accurately setting the error range of the frequency during locking.
To achieve the above and other objects, the present invention provides a lock indicator based on frequency comparison, including:
a waveform adjusting unit for shaping the reference clock CLKREF and the VCO clock CLKVCO into a shaped reference clock CLK1 and a shaped VCO clock CLK2O having a duty ratio of 50%, respectively;
an edge frequency discriminator for frequency-comparing the shaped reference clock CLK1 and the shaped VCO clock CLK2O and outputting a frequency error pulse VOUT;
the edge frequency discriminator comprises an inverter, a third D flip-flop D3, a fourth D flip-flop D4 and an XOR gate X1, wherein one path of the shaped reference clock CLK1 output by the waveform adjusting unit is connected to the clock input terminal of the third D flip-flop D3, the other path of the shaped reference clock is inverted by the inverter to obtain an inverted shaped reference clock, the inverted shaped reference clock is connected to the clock input terminal of the fourth D flip-flop D4, the shaped VCO clock CLK2O is connected to the data input terminals of the third D flip-flop D3 and the fourth D flip-flop D4, the non-inverting output terminals of the third D flip-flop D3 and the fourth D flip-flop D4 are connected to the input terminal of the XOR gate X1, and the frequency error pulse VOUT is output from the output terminal of the XOR gate X1 to the locking indication generating unit;
and the locking indication generating unit is used for counting the shaping reference clock CLK1 under the control of the frequency error pulse and carrying out AND operation on the counting output to obtain a locking indication signal.
Further, the waveform adjusting unit adjusts the duty ratio of the input waveform to 50% while not changing the ratio of the frequencies of the shaped reference clock CLK1 and the shaped VCO clock CLK 2O.
Further, the waveform adjusting unit adjusts the duty ratio of the input waveform to 50% using an even number of D flip-flops.
Further, the waveform adjusting unit at least comprises a first D flip-flop D1 and a second D flip-flop D2, the reference clock CLKREF and the VCO clock CLKVCO are respectively connected to the clock input terminals of the first D flip-flop D1 and the second D flip-flop D2, the inverted output terminals of the first D flip-flop D1 and the second D flip-flop D2 are respectively connected to the respective data input terminals, and the shaped reference clock CLK1 and the shaped VCO clock CLK2O are respectively output from the non-inverted output terminals of the first D flip-flop D1 and the second D flip-flop D2 and output to the edge frequency discriminator.
Further, the edge discriminator outputs a frequency error pulse VOUT when the frequencies of the shaped reference clock CLK1 and the shaped VCO clock CLK2O are different, the larger the frequency difference, the higher the frequency of the frequency error pulse.
Furthermore, the edge frequency discriminator comprises an odd number of inverters, two paths of D triggers and an exclusive-OR gate.
Further, the locking indication generating unit comprises an n counter, an n input AND gate and a latching D trigger.
Further, the n counter is a counting unit with a reset function, if the reset terminal R thereof has no pulse signal all the time, the counter counts normally, the output lock indication signal becomes high after n cycles of the shaped reference clock CLK1, and thereafter the output does not change even if the reset terminal R has a pulse signal; if during normal counting a reset terminal R occurs a pulse in less than n periods of the shaped reference clock CLK1, the counting starts again with 0.
Further, the lock indication generating unit includes a counter composed of n-1D flip-flops D6-D (5+ n-1) cascade, an n-input AND gate AND1 AND a latched D flip-flop D5, the frequency error pulse VOUT output by the edge frequency discriminator is connected to the reset input R of the D flip-flops D6-D (5+ n-1), the shaping reference clock CLK1 is further connected to the clock input of the D flip-flop D6 AND an input of the n-input AND gate AND1, the non-inverting output of the D flip-flop D6 is connected to the clock input of the D flip-flop D7, AND so on, the non-inverting output of the D flip-flop D (5+ n-2) is connected to the clock input of the D flip-flop D (5+ n-1), the inverting outputs of all D flip-flops D6-D (5+ n-1) are connected to the respective data inputs, the non-inverting output terminals of all the D flip-flops D6-D (5+ n-1) are connected to the n-1 input terminals of the n-input AND gate AND1, the output terminal of the n-input AND gate AND1 is connected to the clock input terminal of the latched D flip-flop D5, the data input terminal of the latched D flip-flop D5 is connected to a power supply or a high level, AND the lock indication signal is output from the non-inverting output terminal of the latched D flip-flop D5.
Compared with the prior art, the locking indicator based on frequency comparison realizes the function of the locking indicator by adopting a pure digital circuit, and has the following advantages:
1. the frequency range is wide because of the absence of a filter and the existence of only a digital circuit.
2. And the error rate is low by judging locking through frequency.
3. No additional circuitry is required to generate the VREF.
4. The error range of the frequency at the time of locking can be accurately set.
Drawings
FIG. 1 is a schematic diagram of a conventional phase comparison type lock indicator;
FIG. 2 is a schematic diagram of a lock indicator based on frequency comparison according to the present invention;
FIG. 3 is a schematic structural diagram of the waveform adjustment unit 10 according to the preferred embodiment of the present invention;
fig. 4 is a schematic diagram of the edge discriminator 20 according to the preferred embodiment of the present invention;
FIG. 5 is a schematic diagram of a lock indication generating unit 30 according to a preferred embodiment of the present invention;
FIG. 6 is a timing diagram of the edge discriminator according to the present invention;
fig. 7 is a timing chart of the counter of the lock indicator generating unit according to the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
Fig. 2 is a schematic structural diagram of a locking indicator based on frequency comparison according to the present invention. As shown in fig. 2, a lock indicator based on frequency comparison according to the present invention includes a waveform adjusting unit 10, an edge discriminator 20 and a counter 30.
A waveform adjusting unit 10 composed of an even number of D flip-flops (illustrated as 2) for shaping the reference clock CLKREF and the VCO clock CLKVCO into a shaped reference clock CLK1 and a shaped VCO clock CLK2O having a duty ratio of 50%, respectively; the edge frequency discriminator 20 is composed of odd inverters, two paths of D triggers and an exclusive-OR gate, and is used for comparing the frequencies of the shaping reference clock CLK1 and the shaping VCO clock CLK2O and outputting a frequency error pulse VOUT; and the locking indication generating unit 30 consists of a counter formed by cascading n-1D triggers, an n-input AND gate and a latching D trigger, and is used for counting the integer reference clock CLK1 under the control of the error frequency pulse and carrying out AND operation on the counting output to obtain a locking indication signal.
Fig. 3 is a schematic structural diagram of the waveform adjustment unit 10 according to the preferred embodiment of the invention. As shown in fig. 3, the waveform adjustment unit 10 is composed of an even number of D flip-flops (shown as 2), the reference clock CLKREF and the VCO clock CLKVCO are respectively connected to the clock input terminals CLK of the D flip-flops D1 and D2, the inverted output terminals QB of the D flip-flops D1 and D2 are respectively connected to the respective data input terminals D, and the shaped reference clock CLK1 and the shaped VCO clock CLK2O are respectively output from the non-inverted output terminals Q of the D flip-flops D1 and D2 and output to the edge frequency discriminator 20. It should be noted that the waveform adjusting unit 10 adjusts the duty ratio of the input waveform to 50% without changing the ratio of the frequencies of CLK1 and CLK2O, and the two-frequency divider used in fig. 3 is only one possible implementation method.
Fig. 4 is a schematic diagram of the edge discriminator 20 according to the preferred embodiment of the invention. The edge frequency discriminator 20 is composed of an odd number of inverters, two paths of D flip-flops and an exclusive nor gate, in the embodiment of the invention, the edge frequency discriminator 20 includes an inverter INV1, a D flip-flop D3, a D4 and an exclusive nor gate X1, one path of the shaped reference clock CLK1 output by the waveform adjusting unit 10 is connected to the clock input CLK of the D flip-flop D3, the other path is inverted by an inverter INV1 to obtain an inverted shaped reference clock CLK1B, the inverted shaped reference clock CLK1B is connected to the clock input CLK of the D flip-flop D4, the shaped VCO clock CLK2O is connected to the data input D of the D flip-flops D3 and D4, the non-phase output terminals of the D flip-flops D3 and D4 are connected to the input terminal of the exclusive nor gate X1, a frequency error pulse is output from the output terminal of the exclusive nor gate X1 to the lock indication generating unit 30, that is, that the edge flip-flop outputs a pulse when the frequencies of the shaped reference clock CLK1 and the VCO 2 clock CLK, the larger the frequency difference, the higher the pulse frequency
Fig. 5 is a schematic structural diagram of the lock indication generating unit 30 according to the preferred embodiment of the invention. As shown in FIG. 5, the lock indication generation unit 30 is composed of a counter (D6-D (5+ n-1)) composed of a cascade of n-1D flip-flops, an n-input AND gate AND1, AND a latching D flip-flop D5. In the present invention, the n counter in the lock indication generating unit 30 is a counting unit with a reset function, if the reset terminal R has no pulse signal all the time, the counter normally counts, the output LKDTR becomes high after n cycles of CLK1, and thereafter, even if the reset terminal R has a pulse signal, the output does not change any more; if during normal counting, R pulses occur in less than n cycles of CLK1, the count starts again at 0. The counter can have various forms, AND FIG. 5 shows only one of them, as shown in FIG. 5, the frequency error pulse VOUT output by the edge frequency discriminator 20 is connected to the reset input R of the D flip-flops D6-D (5+ n-1), the shaped reference clock CLK1 is further connected to an input of the AND gate AND1 composed of the clock input CLK of the D flip-flop D6 AND the n input, the non-inverting output of the D flip-flop D6 is connected to the clock input CLK, … … of the D flip-flop D7, the non-inverting output of the D flip-flop D (5+ n-2) is connected to the clock input CLK of the D flip-flop D (5+ n-1), the inverting output QB of the D flip-flops D6-D (5+ n-1) is connected to the respective data input D, the non-inverting outputs of the D flip-flops D6-D (5+ n-1) are connected to the other n-1 inputs of the AND gate 1, the output terminal of the n-input AND gate AND1 is connected to the clock input terminal CLK of the D flip-flop D5, the data input terminal of the D flip-flop D5 is connected to the power supply or high level, AND the lock indicator signal LKDTR is output from the non-inverting output terminal of the D flip-flop D5.
FIG. 6 is a timing diagram of the edge discriminator according to the present invention. First, two clocks CLKREF and CLKVCO are adjusted to two signals CLK1, CLK2O having duty ratios of 50%, respectively, through a waveform adjusting unit. Then, the two clocks CLK1 and CLK2O enter an edge discriminator which sequentially picks the level of CLK2O using the rising and falling edges of CLK 1. If CLK1 agrees with the CLK2O frequency, then the results collected will be 0, 1, … … (alternating "0" and "1"). If the frequencies of CLK1 and CLK2O do not coincide, a timing diagram of the inputs and outputs is shown in FIG. 6. The solid arrow shows the code "0, 0" (and possibly "1, 1") at which time VOUT will go high until the next alternate sequence occurs ("0, 1" or "1, 0") and then go low again.
Fig. 7 is a timing chart of the counter of the lock indicator generating unit according to the present invention. The counter generates a rising edge signal at the output in accordance with the number of rising edges at the input. The number of such rising edges affects the accuracy of the lock indicator. R is the RESET terminal (RESET) of the counter, which will count again as long as the R input is high. The timing diagram for an n counter is shown in FIG. 7:
if the frequency of CLK1 is the same as that of CLK2O, the output of the edge frequency detector is always kept low, the counter counts normally, and after the preset value is reached, the LKDTR value is high, namely locking is carried out; if the CLK1 and CLK2O frequencies are different, the edge discriminator will continue to output positive going pulses and the counter will continue to reset, with the output always low.
In a Phase Locked Loop (PLL), it is common to use a phase difference between two clocks smaller than a certain value as a criterion for locking. But under some conditions (e.g., capacitance leakage, charge pump mismatch, etc.) the phase difference remains at a relatively high level even though the internal is in a stable locked state. At this time, the phase comparison type lock indicator assumes that the PLL is not locked and fails. However, the frequency as the determination means is not limited by the above-mentioned problem.
In addition, if an n-counter is selected, the output will be latched as long as the R signal is not high for n cycles of CLK 1. According to the working principle of the edge discriminator, it can be known that the frequency of CLK1 is f1, and the frequency of CLK2O is f 2:
the frequency accuracy at the time of locking can be adjusted by appropriately setting n.
In the invention, the waveform adjusting unit 10 consists of two DFFs (D flip-flops) used as two frequency dividers, and the two D flip-flops at the input end perform one-time frequency division on the input signals, so that the duty ratios of CLK1 and CLK2O can be ensured to be 50%; then CLK1 and CLK2O enter the edge discriminator to compare the frequencies; the frequency of CLKVCO and CLKREF are discriminated from being close based on the number of bits of the counter. Since 1 frequency-halving unit is passed here, the locking precision is half of the original, namely:
wherein f isREFAnd fVCOThe frequencies of CLKREF and CLKVCO, respectively, and n is the counter count total.
Therefore, the locking indicator based on frequency comparison realizes the function of the locking indicator by adopting a pure digital circuit. Compared with the prior art, the invention has the following advantages:
1. the frequency range is wide because of the absence of a filter and the existence of only a digital circuit.
2. And the error rate is low by judging locking through frequency.
3. No additional circuitry is required to generate the VREF.
4. The error range of the frequency at the time of locking can be accurately set.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (9)
1. A lock indicator based on frequency comparison, comprising:
a waveform adjusting unit for shaping the reference clock CLKREF and the VCO clock CLKVCO into a shaped reference clock CLK1 and a shaped VCO clock CLK2O having a duty ratio of 50%, respectively;
an edge frequency discriminator for frequency-comparing the shaped reference clock CLK1 and the shaped VCO clock CLK2O and outputting a frequency error pulse VOUT;
the edge frequency discriminator comprises an inverter, a third D trigger D3, a fourth D trigger D4 and an exclusive-OR gate X1, one path of a shaped reference clock CLK1 output by the waveform adjusting unit is connected to the clock input end of the third D trigger D3, the other path of the shaped reference clock is inverted by the inverter to obtain an inverted shaped reference clock, the inverted shaped reference clock is connected to the clock input end of the fourth D trigger D4, the shaped VCO clock CLK2O is connected to the data input ends of the third D trigger D3 and the fourth D trigger D4, and the inverter, the
The non-inverting outputs of the third and fourth D flip-flops D3 and D4 are connected to the input terminal of the xor gate X1, and the frequency error pulse VOUT is output from the output terminal of the xor gate X1 to the lock indication generating unit;
and the locking indication generating unit is used for counting the shaping reference clock CLK1 under the control of the frequency error pulse and carrying out AND operation on the counting output to obtain a locking indication signal.
2. A frequency comparison based lock indicator as claimed in claim 1 wherein: the waveform adjusting unit adjusts the duty ratio of the input waveform to 50% while not changing the ratio of the frequencies of the shaped reference clock CLK1 and the shaped VCO clock CLK 2O.
3. A frequency comparison based lock indicator as claimed in claim 2, wherein: the waveform adjusting unit adjusts the duty ratio of the input waveform to 50% using an even number of D flip-flops.
4. A frequency comparison based lock indicator as claimed in claim 3, wherein: the waveform adjusting unit at least comprises a first D flip-flop D1 and a second D flip-flop D2, the reference clock CLKREF and the VCO clock CLVCO are respectively connected with the clock input ends of the first D flip-flop D1 and the second D flip-flop D2, the inverted output ends of the first D flip-flop D1 and the second D flip-flop D2 are respectively connected with the data input ends thereof, and the shaped reference clock CLK1 and the shaped VCO clock CLK2O are respectively output from the non-inverted output ends of the first D flip-flop D1 and the second D flip-flop D2 and output to the edge frequency discriminator.
5. A frequency comparison based lock indicator as claimed in claim 4, wherein: the edge discriminator outputs a frequency error pulse VOUT when the frequencies of the shaped reference clock CLK1 and the shaped VCO clock CLK2O are different, the frequency error pulse frequency being higher the larger the frequency difference.
6. A frequency comparison based lock indicator as claimed in claim 5, wherein: the edge frequency discriminator comprises an odd number of inverters, two paths of D triggers and an exclusive-OR gate.
7. A frequency comparison based lock indicator as claimed in claim 6, wherein: the locking indication generating unit comprises an n counter, an n input AND gate and a latching D trigger.
8. A frequency comparison based lock indicator as claimed in claim 7, wherein: the n counter is a counting unit with a reset function, if the reset end R of the n counter has no pulse signal all the time, the n counter counts normally, the output locking indication signal becomes high after n cycles of the shaping reference clock CLK1, and the output does not change any more after that even if the reset end R has the pulse signal; if during normal counting a reset terminal R occurs a pulse in less than n periods of the shaped reference clock CLK1, the counting starts again with 0.
9. A frequency comparison based locking as claimed in claim 8An indicator, characterized by: the locking indication generating unit comprises n-1D flip-flops D6D (5+ n-1) cascade-formed counters, n-input AND gate AND1 AND latch D flip-flop D5, the frequency error pulse VOUT output by the edge frequency discriminator is connected to the reset input R of D6-D (5+ n-1), the shaping reference clock CLK1 is also connected to the clock input of D flip-flop D6 AND an input of n-input AND gate AND1, the in-phase output of D flip-flop D6 is connected to the clock input of D flip-flop D7, AND so on, the in-phase output of D flip-flop D (5+ n-2) is connected to the clock input of D flip-flop D (5+ n-1), the inverted outputs of all D flip-flops D6-D (5+ n-1) are connected to respective data inputs, the in-phase outputs of all D flip-flops D6-D (5+ n-1) are connected to n-1 inputs of the n-input AND gate 1, the output terminal of the n-input AND gate AND1 is connected to the clock input terminal of the latching D-flip-flop D5, the data input terminal of the latching D-flip-flop D5 is connected to the power supply or high level, AND the lock indication signal is output from the non-inverting output terminal of the latching D-flip-flop D5.
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| CN107786202B (en) * | 2017-11-09 | 2021-10-01 | 上海华力微电子有限公司 | Locking indicator circuit with error code eliminating function |
| CN108120971B (en) * | 2017-12-12 | 2021-01-29 | 中国特种设备检测研究院 | Expected signal identification method and device, ground tracking equipment and system |
| CN109639271B (en) * | 2018-12-12 | 2023-08-11 | 上海华力集成电路制造有限公司 | Lock indication circuit and phase-locked loop formed by same |
| CN111642140B (en) * | 2019-01-02 | 2023-12-01 | 京东方科技集团股份有限公司 | Measuring device and measuring method |
| CN110635800B (en) * | 2019-09-20 | 2023-05-23 | 上海华力微电子有限公司 | Locking indication circuit and method applied to phase-locked loop and based on frequency comparison |
| CN112187218B (en) * | 2020-08-28 | 2024-05-17 | 芯创智（北京）微电子有限公司 | Accurate clock signal duty cycle correction circuit |
| CN116155273B (en) * | 2023-04-17 | 2023-06-23 | 南京航空航天大学 | Injection locking frequency locking loop and method based on frequency-voltage conversion |
| CN117978160A (en) * | 2024-03-29 | 2024-05-03 | 成都电科星拓科技有限公司 | Frequency discrimination circuit and clock data recovery chip |
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| CN106027039A (en) * | 2016-05-16 | 2016-10-12 | 上海华力微电子有限公司 | Verification circuit for locking detection circuit |
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