CN106788407B - A kind of phaselocked loop for supporting multi-protocols - Google Patents
A kind of phaselocked loop for supporting multi-protocols Download PDFInfo
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- CN106788407B CN106788407B CN201611104156.XA CN201611104156A CN106788407B CN 106788407 B CN106788407 B CN 106788407B CN 201611104156 A CN201611104156 A CN 201611104156A CN 106788407 B CN106788407 B CN 106788407B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The present invention relates to a kind of phaselocked loops for supporting multi-protocols, belong to IC design field, including phase frequency detector, charge pump, low-pass filter, voltage controlled oscillator and frequency divider, there are two voltage controlled oscillators, it is arranged in parallel, and resonance is covered each by different frequency ranges in different frequency, synchronization is only working there are one voltage controlled oscillator；Frequency divider is multi-mode frequency divider, contain the frequency division module of multiple and different frequency dividing ratios, the output frequency signal of the voltage controlled oscillator to work is divided, obtained signal and reference signal is compared by phase frequency detector, using charge pump, low-pass filter output to the control signal of voltage controlled oscillator, the frequency and phase of the voltage controlled oscillator to work are locked；The phaselocked loop has the characteristics that compact-sized, covering frequence range is big, supports working frequency points more, can exportable multiple clock frequencies, meet requirement of the various protocols such as Ethernet in HSSI High-Speed Serial Interface, optical-fibre channel, RapidIO to transmission data rate.
Description
Technical field
The invention belongs to IC design technical field, more particularly to a kind of phaselocked loop for supporting multi-protocols.
Background technology
Phaselocked loop (Phase Locked Loop, PLL) is a kind of feedback circuit, passes through externally input low-frequency ginseng
Examine the frequency and phase of the high frequency oscillation signal of signal control circuit output.PLL can provide accurate, stable for other circuits
Clock signal all plays an important role in wired data transfer and wireless communication.
The basic principle figure of PLL is as shown in Figure 1, including mainly phase frequency detector, charge pump, low-pass filter, voltage-controlled shaking
Swing the modules such as device (Voltage Controlled Oscillator) and frequency divider.fREFFor input reference signal, fOUTFor PLL
Output signal, fDIVFor fOUTOutput signal after frequency divider divides.
At present there are many agreement, each agreement defines multiple and different message transmission rates for high-speed serial data transmission.
Certain applications need to support the High Speed Serial circuit of multi-protocols, more data rate transmissions, and such circuit, which needs to have, to be provided
The PLL of required multi-frequency.The circuit having at present realizes that multi-frequency exports using 2 PLL, and such circuit area is bigger, PLL
It is more complicated with the connection of other circuits.Some circuits realize multi-frequency output using the PLL of fractional frequency division structure, at this moment export
The spuious or noise of signal is larger, and signal quality is difficult to ensure.
Invention content
In order to overcome the disadvantages of the above prior art, the purpose of the present invention is to provide a kind of locking phases for supporting multi-protocols
Ring supports a variety of HSSI High-Speed Serial Interface agreements, has multiple output frequencies, supports Ethernet, optical-fibre channel, RapidIO associations
A variety of data transfer rates specified in view, required clock signal is provided for transceiver circuit.
To achieve the goals above, the technical solution adopted by the present invention is：
A kind of phaselocked loop for supporting multi-protocols, including phase frequency detector, charge pump, low-pass filter, voltage controlled oscillator and
Frequency divider, there are two the voltage controlled oscillators, is arranged in parallel, and resonance is covered each by different frequency ranges in different frequency,
Synchronization is only working there are one voltage controlled oscillator；The frequency divider is multi-mode frequency divider, contains multiple and different frequency dividings
The frequency division module of ratio, by the output frequency signal f of the voltage controlled oscillator to workOUTIt is divided to obtain signal fDIV, signal
fDIVWith reference signal fREFCompared by phase frequency detector, using charge pump, low-pass filter output to voltage controlled oscillator
Signal is controlled, the frequency and phase of the voltage controlled oscillator to work are locked.
The invention also includes multiple selector, the output for the voltage controlled oscillator that multiple selector selection is working will lock
Signal after fixed is sent out.
The invention also includes the mode control circuit of setting output frequency, the mode control circuit output control signal C1
~C5, C1Adjust the bias current of charge pump so that charge pump has correctly output at different frequencies；C2And C3Setting pressure
The state for controlling oscillator is work or suspend mode, and adjusts the frequency of oscillation of the voltage controlled oscillator of work；C4Set multiple selector
Output source；C5Set the frequency dividing ratio of multi-mode frequency divider.Control signal C1~C5It is unit or multidigit control signal.
The multi-mode frequency divider includes four frequency division modules, the output frequency signal f of voltage controlled oscillatorOUTInto multimode
Formula frequency divider, according to control signal C5Setting, fOUTIt is divided by one in four frequency division modules, using multichannel
Selector exports to obtain fDIV, which realizes 68/80/82.5/100 division function respectively.
The frequency dividing of the frequency division module 68 is divided by cascade 2,2 frequency dividings, 8/9 frequency dividing circuit are realized；80 frequency dividings are by cascade 4
A 2 frequency dividing, 15 frequency dividing circuit are realized；82.5 frequency dividings are divided by cascade 2,2 frequency dividings, 20/21 frequency dividing circuit are realized；100 points
Frequency is divided by cascade 2,2 frequency dividings, 5/5 frequency dividing circuits of frequency dividing are realized.
The frequency division module realizes fixed integer or fraction division.
Compared with prior art, the beneficial effects of the invention are as follows：Only multiple high speed serializations can be supported to connect with a PLL
Multiple frequencies needed for mouth agreement.The PLL only needs a fixed external reference input signal.The PLL uses fixed integer
And fractional divider, the phase noise of output signal and spuious smaller.
Description of the drawings
Fig. 1 is conventional principle of phase lock loop figure.
Fig. 2 is the principle of phase lock loop figure for supporting multi-protocols.
Fig. 3 is multi-mode frequency divider schematic diagram.
Fig. 4 is the schematic diagram of each frequency division module in multi-mode frequency divider.
Specific implementation mode
Below in conjunction with the accompanying drawings, it elaborates to preferred embodiment.It is emphasized that following the description is merely exemplary
, the range being not intended to be limiting of the invention and its application.
The circuit structure of PLL of the present invention as shown in Fig. 2, comprising phase frequency detector, charge pump, low-pass filter, two it is humorous
Shake the VCO in different frequency, multiple selector and multi-mode frequency divider, and in addition there are the scheme control electricity of setting output frequency
Road.The circuit use two VCO, be covered each by different frequency ranges, in use according to setting synchronization only there are one
VCO is working.Multi-mode frequency divider then contains the frequency division module of multiple and different frequency dividing ratios, by the frequency of the VCO to work
It is divided.Especially, it should be noted that each frequency division module in multi-mode frequency divider realizes fixed integer or fraction division,
With good phase noise and spuious characteristic.The output signal f of VCOOUTSignal is obtained after multi-mode frequency divider frequency dividing
fDIV。fDIVWith externally input reference signal fREFIt is defeated using charge pump and low-pass filter by the comparison of phase frequency detector
Go out the control signal to VCO, locks the frequency and phase of the VCO to work.Multiple selector then selects the VCO to work
Output, the signal after locking is sent out.Since two VCO have wider frequency coverage, multi-mode frequency divider
A variety of frequency dividing ratios can be provided, therefore in the appropriately designed lower multiple output frequencies that can be generated needed for various protocols.Scheme control electricity
Other circuits in PLL are adjusted in road, and PLL is made to be operated in the frequency of setting.
Mode control circuit output control signal C in Fig. 21~C5。C1Adjust the bias current of charge pump so that not
Charge pump has correctly output under same frequency；C2And C3The state (work or suspend mode) of VCO is set, and adjust the VCO of work
Frequency of oscillation；C4Set the output source of multiple selector；C5Set the frequency dividing ratio of multi-mode frequency divider.It should be noted that C1
~C5Can be unit or multidigit control signal.
Fig. 3 is the schematic diagram of multi-mode frequency divider.The output f of VCOOUTInto multi-mode frequency divider, according to control signal C5
Setting, fOUTIt is divided by one in four frequency division modules, exports to obtain f using multiple selectorDIV.This four
Frequency division module realizes 68/80/82.5/100 division function respectively.
Fig. 4 is the realization method of each frequency division module in multi-mode frequency divider.68 frequency dividings are by cascade 2 frequency dividing, 2 frequency dividings, 8/9
Frequency dividing circuit is realized；80 frequency dividings are realized by cascade 42 frequency dividings, 15 frequency dividing circuit；82.5 frequency dividings are by cascade 2 frequency dividing, 2
Frequency dividing, 20/21 frequency dividing circuit are realized；100 frequency dividings are divided by cascade 2,2 frequency dividings, 5/5 frequency dividing circuits of frequency dividing are realized.
Table 1 is the output frequency for the PLL for supporting multi-protocols.Input reference signal frequency is 125MHz, when being divided using 68
PLL output signal frequency is 8.5GHz；PLL output signal frequency is 10.0GHz when being divided using 80；When being divided using 82.5
PLL output signal frequency is 10.3125GHz；PLL output signal frequency is 12.5GHz when being divided using 100.4 kinds of the PLL
Output frequency can obtain low frequency signal by 2 power frequency dividing.The output of PLL and its output frequency after frequency dividing can support with
The too requirement of net, optical-fibre channel, RapidIO agreements to clock frequency.
Table 1 supports the output frequency of the phaselocked loop of multi-protocols
| Reference frequency (MHz) | Output frequency (GHz) | Frequency dividing ratio | Supported protocol |
| 125 | 8.5 | 68 | Optical-fibre channel |
| 125 | 10 | 80 | RapidIO |
| 125 | 10.3125 | 82.5 | Ethernet, RapidIO |
| 125 | 12.5 | 100 | RapidIO |
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, the change or replacement that can be readily occurred in,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with scope of the claims
Subject to.
Claims (6)
1. a kind of phaselocked loop for supporting multi-protocols, including phase frequency detector, charge pump, low-pass filter, voltage controlled oscillator and point
Frequency device, there are two the voltage controlled oscillators, is arranged in parallel, and resonance is covered each by different frequency ranges, together in different frequency
One moment only had a voltage controlled oscillator working；The frequency divider is multi-mode frequency divider, contains multiple and different frequency dividing ratios
Frequency division module, by the output frequency signal f of the voltage controlled oscillator to workOUTIt is divided to obtain signal fDIV, signal fDIV
With reference signal fREFCompared by phase frequency detector, the control to voltage controlled oscillator is exported using charge pump, low-pass filter
Signal locks the frequency and phase of the voltage controlled oscillator to work, which is characterized in that further includes the pattern that output frequency is arranged
Control circuit, the mode control circuit output control signal C1~C5, C1Adjust the bias current of charge pump so that in difference
Charge pump has correctly output under frequency；C2And C3The state of voltage controlled oscillator is set as work or suspend mode, and adjusts work
The frequency of oscillation of voltage controlled oscillator；C4Set the output source of multiple selector；C5Set the frequency dividing ratio of multi-mode frequency divider.
2. supporting the phaselocked loop of multi-protocols according to claim 1, which is characterized in that further include multiple selector, multichannel choosing
The output for selecting the voltage controlled oscillator that device selection is working, the signal after locking is sent out.
3. supporting the phaselocked loop of multi-protocols according to claim 1, which is characterized in that the control signal C1~C5It is unit
Or multidigit controls signal.
4. supporting the phaselocked loop of multi-protocols according to claim 1, which is characterized in that the multi-mode frequency divider includes four
Frequency division module, the output frequency signal f of voltage controlled oscillatorOUTInto multi-mode frequency divider, according to control signal C5Setting, fOUT
It is divided by one in four frequency division modules, exports to obtain f using multiple selectorDIV, four frequency division modules point
68/80/82.5/100 division function is not realized.
5. supporting the phaselocked loop of multi-protocols according to claim 4, which is characterized in that the frequency division module 68 is divided by cascading
2 frequency dividing, 2 frequency dividing, 8/9 frequency dividing circuit realize；80 frequency dividings are realized by cascade 42 frequency dividings, 15 frequency dividing circuit；82.5 points
Frequency is divided by cascade 2,2 frequency dividings, 20/21 frequency dividing circuit are realized；100 frequency dividings are divided by cascade 2,2 divide, 5 divide, 5 points
Frequency circuit is realized.
6. supporting the phaselocked loop of multi-protocols according to claim 1, which is characterized in that the frequency division module is realized fixed whole
Number or fraction division.
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| CN201611104156.XA CN106788407B (en) | 2016-12-05 | 2016-12-05 | A kind of phaselocked loop for supporting multi-protocols |
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| CN201611104156.XA CN106788407B (en) | 2016-12-05 | 2016-12-05 | A kind of phaselocked loop for supporting multi-protocols |
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| CN106788407B true CN106788407B (en) | 2018-10-19 |
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| CN102355240A (en) * | 2011-08-02 | 2012-02-15 | 深圳市国微电子股份有限公司 | Clock generator used for integrated circuit |
| CN103684445A (en) * | 2012-09-11 | 2014-03-26 | 成都锐成芯微科技有限责任公司 | Multiphase high-resolution phase locked loop |
| CN104242916A (en) * | 2013-06-20 | 2014-12-24 | 沈阳中科微电子有限公司 | Frequency synthesizer of five-to-one structure 40 MHz crystal oscillator for Q-band wireless communication |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10257185B3 (en) * | 2002-12-06 | 2004-02-05 | Infineon Technologies Ag | Phase-locked loop with sigma-delta modulator having feedback path representing complex transmission function in Laplace plane |
| US7138877B2 (en) * | 2004-04-21 | 2006-11-21 | Rambus Inc. | PLL and method for providing a single/multiple adjustable frequency range |
| US8130044B2 (en) * | 2008-06-19 | 2012-03-06 | Altera Corporation | Phase-locked loop circuitry with multiple voltage-controlled oscillators |
| US9276622B2 (en) * | 2013-03-14 | 2016-03-01 | Qualcomm Incorporated | Local oscillator (LO) generator with multi-phase divider and phase locked loop |
| CN104702279A (en) * | 2015-03-17 | 2015-06-10 | 东南大学 | Frequency synthesizer of phase-locked loop |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102355240A (en) * | 2011-08-02 | 2012-02-15 | 深圳市国微电子股份有限公司 | Clock generator used for integrated circuit |
| CN103684445A (en) * | 2012-09-11 | 2014-03-26 | 成都锐成芯微科技有限责任公司 | Multiphase high-resolution phase locked loop |
| CN104242916A (en) * | 2013-06-20 | 2014-12-24 | 沈阳中科微电子有限公司 | Frequency synthesizer of five-to-one structure 40 MHz crystal oscillator for Q-band wireless communication |
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