CN106788386B - Level conversion circuit for reducing hot carrier degradation - Google Patents
Level conversion circuit for reducing hot carrier degradation Download PDFInfo
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- CN106788386B CN106788386B CN201611077581.4A CN201611077581A CN106788386B CN 106788386 B CN106788386 B CN 106788386B CN 201611077581 A CN201611077581 A CN 201611077581A CN 106788386 B CN106788386 B CN 106788386B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
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Abstract
A level shift circuit for reducing hot carrier degradation includes first and second PMOS transistors, first and second NMOS transistors, an inverter, and a hot carrier suppressor circuit; the node of the second PMOS transistor and the node of the second NMOS transistor form the output of the level conversion circuit and are connected with the grid electrode of the first PMOS transistor; the source end of the second PMOS transistor is connected with an external high-voltage power supply, and the source end of the second NMOS transistor is connected with the ground level; the node of the first PMOS transistor and the node of the first NMOS transistor are connected with the grid electrode of the second PMOS transistor, the source end of the first PMOS transistor is connected with an external high-voltage power supply, and the source end of the first NMOS transistor is connected with the ground level; the first inverter input constitutes the input of a level shifter circuit, the output of which is connected to the gate of the first NMOS transistor and to the input of the hot carrier suppressor circuit, the output of which is connected to the gate of the second NMOS transistor to reduce the voltage that actually reaches the second NMOS transistor.
Description
Technical Field
The invention belongs to the technical field of test chip design, and particularly relates to a level conversion circuit for reducing hot carrier degradation.
Background
In an integrated circuit, a level shifter circuit is an important component. The device bearing high level in the level conversion circuit has the characteristics of high working voltage and high driving capability. As chip sizes decrease, particularly in deep submicron technologies for a typical integrated circuit chip, device feature sizes, such as gate oxide thickness and channel length, decrease significantly, the supply voltage and operating voltage of the chip are not reduced much, and the corresponding electric field strength increases, resulting in an increase in the electron motion rate.
Under high working voltage, a strong transverse electric field exists in a channel of the device, so that a carrier is subjected to impact ionization in the transportation process to generate extra electron hole pairs, and part of hot carriers are injected into a gate oxide layer, so that the threshold voltage of the device is increased, the saturation current and the carrier mobility are reduced, and the like, and the phenomenon is called HCI (hot carrier injection) effect.
The HCI effect is a problem often encountered in device design, and is a main factor affecting the device characteristics and reliability, especially for NMOS devices, and the HCI cumulative effect directly causes that the level conversion circuit cannot be inverted and loses the conversion function.
Referring to fig. 1, fig. 1 is a schematic diagram of a low-to-high level conversion circuit in the prior art. As shown, the circuit is for an integrated circuit level shifter circuit having an internal low voltage power supply (VPPL) and an external high voltage power supply (VPPH), having first and second PMOS transistors 1 and 2, having first and second NMOS transistors 3 and 4, and first and second inverters 5 and 6; the node 11 of the second PMOS transistor 2 and the second NMOS transistor 4 forms the output OUT of the level shift circuit, and is connected to the gate of the first PMOS transistor 1; the source end of the second PMOS transistor 2 is connected with an external high-voltage power supply, and the source end of the second NMOS transistor 4 is connected with the ground level. The node 22 of the first PMOS transistor 1 and the first NMOS transistor 3 is connected to the gate of the second PMOS transistor 2, the source terminal of the first PMOS transistor 1 is connected to an external high voltage power supply, and the source terminal of the first NMOS transistor 3 is connected to ground. The inverter 5 has an input IN forming a level shifter circuit, an output connected to the gate of the first NMOS transistor 3 and to an input of the second inverter 6, and an output of the hot carrier suppressor circuit 6 connected to the gate of the second NMOS transistor 4.
The operating condition of the NMOS transistor under severe HCI effect is to satisfy the following relationship between the gate voltage VG and the drain voltage VD:
1/3*VD<VG<1/2*VD
as can be seen from the above level shift circuit, when the output of the level shift circuit from low to high (as shown in fig. 1) is inverted from high to low, the second NMOS transistor 4 is turned on, the drain terminal thereof is the external high voltage power supply (VPPH), and the gate thereof is the internal low voltage power supply (VPPL).
If VPPH is 3.3V voltage source and VPPL is 1.8V voltage source, then the device is under the working condition that HCI occurs, hot carriers are injected into the gate oxide layer, and the threshold voltage of the device is increased. After long-term accumulation, the driving current of the second NMOS transistor 4 is reduced after being turned on due to the rise of the threshold voltage, the driving capability of the first NMOS transistor 2 is finally not enemy, the situation that the level conversion circuit cannot output low occurs, meanwhile, the first PMOS transistor 1 cannot be turned on, and then the first NMOS transistor 2 cannot be completely turned off, so that the circuit fails.
The industry also has made a lot of work on the degradation of the performance of the MOS device caused by the injection of hot carriers, but the process for improving the HCI effect by changing the structure of the device is very complicated and high in consumption cost. Therefore, reducing the dose of LDD ion implantation for lightly doped source/drain region, increasing the energy of LDD ion implantation, and obtaining deeper LDD junction to reduce the lateral electric field is an effective means for improving HCI effect, for example, chinese patent nos. CN 102693904B and CN 100490094C.
However, as the size of MOSFET devices is reduced, the gate oxide thickness is thinner and thinner, and the LDD junction is shallower. In the above patent technology, when the LDD ion implantation is performed, in order to avoid the gate oxide breakdown during the ion implantation, the implantation energy is reduced accordingly, so that the formed LDD junction becomes shallower, which is not beneficial to improving the HCI effect; on the other hand, As the concentration gradient between As ions and P ions is relatively larger, the overlapping area between the formed LDD diffusion area and the grid electrode is smaller and smaller, so that the transverse electric field intensity in the channel is larger, and the HCI effect of the device is more and more obvious. Therefore, it is not sufficient to improve the HCI effect simply by changing the dose and energy of the LDD ion implantation.
Disclosure of Invention
In order to overcome the above problems, the level shift circuit for reducing hot carrier degradation according to the present invention embeds a hot carrier suppressor circuit with a selection signal control in a conventional level shift circuit from a circuit design point of view, and reduces a gate driving voltage of a high voltage NMOS to make a transistor avoid a severe working region where HCI occurs, thereby achieving an effect of reducing HCI influence.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a level shift circuit for reducing hot carrier degradation for a level shift circuit having an internal low voltage power supply (VPPL) and an external high voltage power supply (VPPH) integrated circuit, comprising:
a first PMOS transistor 1 and a second PMOS transistor 2;
a first NMOS transistor 3 and a second NMOS transistor 4; and
a first inverter 5 and a hot carrier suppression sub-circuit 6;
the node 11 of the second PMOS transistor 2 and the second NMOS transistor 4 forms the output OUT of the level shift circuit, and is connected to the gate of the first PMOS transistor 1; the source end of the second PMOS transistor 2 is connected with an external high-voltage power supply, and the source end of the second NMOS transistor 4 is connected with the ground level;
a node 22 of the first PMOS transistor 1 and the first NMOS transistor 3 is connected with a grid electrode of the second PMOS transistor 2, a source end of the first PMOS transistor 1 is connected with an external high-voltage power supply, and a source end of the first NMOS transistor 3 is connected with a ground level;
the input of first inverter 5 constitutes the input IN of a level shifter circuit, the output of which is connected to the gate of first NMOS transistor 3 and to the input of hot carrier suppression sub-circuit 6, the output of hot carrier suppression sub-circuit 6 being connected to the gate of second NMOS transistor 4 to reduce the voltage actually reaching second NMOS transistor 4.
Preferably, the gate voltage VG and the drain voltage VD of the second transistor have the following relationship:
VT<VG<1/3*VD
preferably, the hot carrier suppressor circuit 6 is constituted by a second inverter 71, a diode 72, a third PMOS transistor 73 and a third NMOS transistor 74; the second inverter 71 and the diode 72 are connected in series, and the anode of the diode 72 and the second inverter 71 share a node; a third PMOS transistor 73 and a third NMOS transistor 74 are connected in parallel with the diode 72 and are controlled by the selection control signal EN and the anti-EN signal, respectively.
Preferably, the forward conduction voltage drop of the diode 72 is 0.3 Volt-0.8 Volt.
Preferably, the diode 72 is a schottky diode, a zener diode, or a PN junction diode.
According to the technical scheme, the level conversion circuit has certain driving capability by controlling the voltage to the grid electrode of the second NMOS transistor, and simultaneously works in a non-HCI high-risk region when the level is reversed, so that the effect of reducing HCI influence is realized, the protection of devices and circuits is realized, and the reliability of long-term work is improved.
Drawings
FIG. 1 is a diagram of a low-to-high level conversion circuit in the prior art
FIG. 2 is a schematic diagram of a low-to-high level conversion circuit according to an embodiment of the present invention
FIG. 3 is a diagram of a hot carrier suppressor circuit in a level shifter circuit according to an embodiment of the present invention
Detailed Description
Embodiments that embody features and advantages of the invention are described in detail in the description that follows. It is understood that the invention is capable of modification in various forms and that the description and drawings are to be regarded as illustrative in nature, and not as restrictive.
A level shift circuit according to the present invention will be described in detail with reference to the accompanying drawings. It should be noted that, in order to overcome the HCI risk of the level shift circuit in the prior art, the level shift circuit of the present invention adds a protection circuit for reducing hot electron injection in the front stage of the gate of the second NMOS transistor 4, so as to reduce the voltage actually reaching the gate, and make the second NMOS transistor 4 work in the non-high risk HCI occurrence environment, thereby protecting the circuit and improving the reliability of long-term work.
Referring to fig. 2, fig. 2 is a schematic diagram of a low-to-high level conversion circuit according to an embodiment of the present invention. As shown in the drawings, in an embodiment of the present invention, an integrated circuit level shifter circuit having an internal low voltage power supply VPPL and an external high voltage power supply VPPH, a first PMOS transistor 1 and a second PMOS transistor 2; a first NMOS transistor 3 and a second NMOS transistor 4; and an inverter 5 and a hot carrier suppression sub-circuit 6; the node 11 of the second PMOS transistor 2 and the second NMOS transistor 4 forms the output OUT of the level shift circuit, and is connected to the gate of the first PMOS transistor 1; the source end of the second PMOS transistor 2 is connected with an external high-voltage power supply, and the source end of the second NMOS transistor 4 is connected with the ground level; a node 22 of the first PMOS transistor 1 and the first NMOS transistor 3 is connected with a grid electrode of the second PMOS transistor 2, a source end of the first PMOS transistor 1 is connected with an external high-voltage power supply, and a source end of the first NMOS transistor 3 is connected with a ground level; the input of first inverter 5 constitutes the input IN of a level shifter circuit, the output of which is connected to the gate of first NMOS transistor 3 and to the input of hot carrier suppression sub-circuit 6, the output of hot carrier suppression sub-circuit 6 being connected to the gate of second NMOS transistor 4 to reduce the voltage actually reaching second NMOS transistor 4.
In the gate pre-stage of the second NMOS transistor 4, the voltage actually reaching the gate is reduced by the hot carrier suppressor circuit 6, and in the embodiment of the present invention, the gate voltage VG and the drain voltage VD of the second transistor preferably have the following relationship:
VT<VG<1/3*VD
that is, the second NMOS transistor 4 is operated in a non-high risk HCI generation environment, thereby protecting the circuit and improving the reliability of long-term operation.
Therefore, the gist of the present invention is to control the voltage reaching the gate of the second NMOS transistor 4 to have a certain driving capability and to operate in a non-HCI generation high-risk region during level inversion, thereby realizing protection of devices and circuits. Any method for achieving the same effect of the present invention through a circuit or a device should be within the scope of the present invention.
Exemplary details are provided below by way of hot carrier suppression sub-circuits that may be used in the level shifting circuits of the present invention.
Example one
Referring to fig. 3, fig. 3 is a schematic diagram of a hot carrier suppressor circuit in a level shifter circuit according to an embodiment of the present invention. As shown, hot carrier suppressor circuit 6 is composed of second inverter 71, diode 72, third PMOS transistor 73, and third NMOS transistor 74; the second inverter 71 and the diode 72 are connected in series, and the anode of the diode 72 and the second inverter 71 share a node; the third PMOS transistor 73 and the third NMOS transistor 74 are connected in parallel with the diode 72 and are controlled by the selection control signal EN and the anti-EN signal, respectively.
In the present embodiment, the diode 72 may be a schottky diode, a zener diode, a PN junction diode, or the like, and the forward conduction voltage drop thereof is 0.3Volt to 0.8 Volt.
That is, the gate voltage applied to the second NMOS transistor 4 is reduced by serially connecting diodes and using the characteristic that the forward voltage of the diodes drops by 0.4 to 0.8V. The second inverter 71 performs the logic function of level conversion correctly, and the third PMOS transistor 73 and the third NMOS transistor 74 are controlled as conduction pipes by the selection signal EN and whether the hot carrier suppression sub-circuit 6 is active or not.
The above description is only an embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.
Claims (4)
1. A level shift circuit for reducing hot carrier degradation for a level shift circuit of an integrated circuit having an internal low voltage power supply (VPPL) and an external high voltage power supply (VPPH), comprising:
a first PMOS transistor (1) and a second PMOS transistor (2);
a first NMOS transistor (3) and a second NMOS transistor (4); and
a first inverter (5) and a hot carrier suppression circuit (6);
the hot carrier suppressor circuit (6) comprises an input end, a power supply end, an output end, a control signal EN end and a grounding end; the power supply terminals of the first inverter (5) and the hot carrier suppression sub-circuit (6) are connected with an internal low voltage power supply (VPPL);
the node (11) of the second PMOS transistor (2) and the second NMOS transistor (4) forms the Output (OUT) of the level conversion circuit and is connected with the grid electrode of the first PMOS transistor (1); the source end of the second PMOS transistor (2), the source end of the first PMOS transistor (1) are connected with an external high-voltage power supply (VPPH), and the source end of the second NMOS transistor (4) is connected with the first NMOS transistor (3) in a ground level;
a node (22) of the first PMOS transistor (1) and the first NMOS transistor (3) is connected with a grid electrode of the second PMOS transistor (2), a source end of the first PMOS transistor (1) is connected with an external high-voltage power supply, and a source end of the first NMOS transistor (3) is connected with a ground level;
the input of the first inverter (5) forms the Input (IN) of a level conversion circuit, the output of the Input (IN) is connected with the grid of the first NMOS transistor (3) and the input end of the hot carrier suppression circuit (6), the output end of the hot carrier suppression circuit (6) is connected with the grid of the second NMOS transistor (4), when the level conversion circuit is under high operating voltage, the hot carrier suppression circuit (6) receives the control signal EN signal for control, and the voltage VG output by the output end of the hot carrier suppression circuit (6) to the second NMOS transistor (4) and the drain voltage VD have the following relation:
VT<VG<1/3*VD
wherein VT is the threshold voltage of the gate of the second NMOS transistor (4).
2. A level shift circuit for reducing hot carrier degradation according to claim 1, wherein the hot carrier suppression sub-circuit (6) is constituted by a second inverter (71), a diode (72), a third PMOS transistor (73) and a third NMOS transistor (74); the second inverter (71) and the diode (72) are connected in series, and the anode of the diode (72) and the second inverter (71) are in a common node; a third PMOS transistor (73) and a third NMOS transistor (74) are connected in parallel with the diode (72) and are controlled by a select control signal EN and an anti-EN signal, respectively.
3. The level shift circuit for reducing hot carrier degradation according to claim 2, wherein the forward conducting voltage drop of the diode (72) is 0.3Volt to 0.8 Volt.
4. A level shift circuit for reducing hot carrier degradation according to claim 2, characterized in that the diode (72) is a schottky diode, a zener diode and a PN junction diode.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611077581.4A CN106788386B (en) | 2016-11-30 | 2016-11-30 | Level conversion circuit for reducing hot carrier degradation |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611077581.4A CN106788386B (en) | 2016-11-30 | 2016-11-30 | Level conversion circuit for reducing hot carrier degradation |
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| CN106788386B true CN106788386B (en) | 2021-08-06 |
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| CN101777907A (en) * | 2009-12-31 | 2010-07-14 | 宁波大学 | Low-power dissipation RS latch unit and low-power dissipation master-slave D flip-flop |
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