CN106788279B

CN106788279B - Low-sensitivity substrate input amplifier

Info

Publication number: CN106788279B
Application number: CN201611095402.XA
Authority: CN
Inventors: 李洪革; 龚斯迪; 白会新
Original assignee: Beihang University
Current assignee: Beihang University
Priority date: 2016-12-01
Filing date: 2016-12-01
Publication date: 2020-02-14
Anticipated expiration: 2036-12-01
Also published as: CN106788279A

Abstract

The application discloses a low-sensitivity substrate input amplifier, which solves the electromagnetic performance defect of the existing substrate input amplifier. The invention comprises at least one positive feedback structure, and the optimized embodiment is an improved positive feedback structure which comprises a first positive feedback structure and a filter circuit. Further, the amplifier of the present invention includes a second positive feedback structure. The embodiment of the invention further comprises a bias circuit, a filter circuit and a symmetrical output stage circuit. The invention improves the EMI resistance of the circuit.

Description

Low-sensitivity substrate input amplifier

Technical Field

The invention relates to the field of electronic circuits, in particular to an amplifier with anti-electromagnetic interference performance.

Background

The low-voltage low-power-consumption amplifier is the key in wearable intelligent electronic products, biomedical micro-nano devices and implantable brain-computer interactive microcomputer systems. For the requirements of long-time endurance and the like of chips, low-voltage and low-power consumption amplifiers with good performance need to be designed. In the current low voltage amplifier technology, the substrate input technology has been widely adopted by low voltage design due to its advantages of wide input swing, suitability for working at very low voltage, etc.

However, the equivalent transconductance of the substrate input MOS transistor in the conventional substrate input amplifier is usually much lower than that of the gate driving transistor under the same condition, which in turn leads to performance degradation such as low cut-off frequency, low DC gain, low signal-to-noise ratio, and the like. Due to high electromagnetic sensitivity, the high-efficiency work or even the normal work can not be realized when the high-efficiency work is interfered by electromagnetic.

Disclosure of Invention

The application discloses a low-sensitivity substrate input amplifier, which solves the electromagnetic performance defect of the existing substrate input amplifier.

The embodiment of the application provides a low-sensitivity substrate input amplifier, which comprises at least one positive feedback structure; the positive feedback structure comprises an 11 th transistor, a 12 th transistor, a 13 th transistor, a 21 st transistor, a 22 nd transistor and a 23 rd transistor; the 11 th transistor, the 12 th transistor, the 13 th transistor, the 21 st transistor, the 22 nd transistor and the 23 rd transistor are all PMOS transistors; the substrates of the 11 th transistor, the 12 th transistor and the 13 th transistor are connected to serve as a first substrate end; the substrates of the 21 st transistor, the 22 nd transistor and the 23 rd transistor are connected to serve as second substrate ends; sources of the 11 th transistor, the 12 th transistor, the 13 th transistor, the 21 st transistor, the 22 nd transistor and the 23 rd transistor are connected to serve as a total source electrode terminal; the drain electrode of the 11 th transistor, the drain electrode of the 12 th transistor, the grid electrode of the 13 th transistor and the grid electrode of the 21 st transistor are connected to form a first grid electrode terminal; the drain of the 21 st transistor, the drain of the 22 nd transistor, the gate of the 23 rd transistor and the gate of the 11 th transistor are connected to form a second gate terminal; the drain electrode of the 13 th transistor is a first drain end; a drain of the 23 rd transistor is a second drain terminal.

As a further preferred embodiment of the present invention, the low-sensitivity substrate input amplifier comprises an improved positive feedback structure, wherein the improved positive feedback structure comprises a filter circuit and a first positive feedback structure (referred to as a first positive feedback structure); the filter circuit comprises a first resistor, a second resistor, a first capacitor, a second capacitor, a first substrate source capacitor and a second substrate source capacitor; one end of the first resistor is connected with a differential signal positive input end, and the other end of the first resistor is connected with a first substrate end of a first positive feedback structure; the positive electrode of the first capacitor is connected with the first substrate end of the first positive feedback structure, and the negative electrode of the first capacitor is grounded; one end of the first substrate source capacitor is connected with the total source electrode end, and the other end of the first substrate source capacitor is connected with the first substrate end of the first positive feedback structure; one end of the second resistor is connected with the negative input end of the differential signal, and the other end of the second resistor is connected with the second substrate end of the first positive feedback structure; the positive electrode of the second capacitor is connected with the second substrate end of the first positive feedback structure, and the negative electrode of the second capacitor is grounded; one end of the second substrate source capacitor is connected with the total source electrode end, and the other end of the second substrate source capacitor is connected with the second substrate end of the first positive feedback structure.

Preferably, the first resistance and the second resistance have a value of 500k Ω; the first capacitor and the second capacitor have a value of 200 fF; the first substrate source capacitance and the second substrate source capacitance have a value of 3 pF.

As a further preferred embodiment of the present invention, the low-sensitivity substrate input amplifier comprises the improved positive feedback structure and further comprises a second positive feedback structure (for short, a second positive feedback structure); the first drain terminal of the first positive feedback structure is connected with the first drain terminal of the second positive feedback structure; the second drain terminal of the first positive feedback structure is connected with the second drain terminal of the second positive feedback structure; a first gate terminal of the first positive feedback structure is connected with a first gate terminal of the second positive feedback structure; the second grid terminal of the first positive feedback structure is connected with the second grid terminal of the second positive feedback structure; the differential signal positive input end is connected with the first substrate end of the second positive feedback structure; and the negative input end of the differential signal is connected with the second substrate end of the second positive feedback structure.

In a further optimized embodiment of the invention, the device also comprises a bias circuit; the bias circuit comprises a 6 th transistor, a 14 th transistor and a 24 th transistor; the 6 th transistor is a PMOS transistor; the 14 th transistor and the 24 th transistor are NMOS transistors; the source electrode of the 6 th transistor is connected with working voltage, the grid electrode of the 6 th transistor is connected with bias voltage, and the drain electrode of the 6 th transistor is connected with the total source electrode terminal; the source electrode of the 14 th transistor is grounded, the grid electrode of the 14 th transistor is connected with a bias voltage, and the drain electrode of the 14 th transistor is connected with the first grid electrode terminal; the source of the 24 th transistor is grounded, the grid of the 24 th transistor is connected with a bias voltage, and the drain of the 24 th transistor is connected with the second grid terminal.

As a further optimized embodiment of the invention, the invention also comprises a symmetrical output stage circuit; the symmetrical output stage circuit comprises a 31 st transistor, a 32 nd transistor, a 41 st transistor and a 42 th transistor; the 41 st transistor and the 42 th transistor are PMOS transistors; the 31 st transistor and the 32 nd transistor are NMOS transistors; the drain electrode of the 31 st transistor is connected with the drain electrode of the 41 th transistor, the grid electrode of the 31 st transistor is connected with the first drain electrode end, and the source electrode of the 31 st transistor is grounded; the drain electrode of the 32 th transistor is connected with the drain electrode of the 42 th transistor, the grid electrode of the 32 th transistor is connected with the second drain electrode end, and the source electrode of the 32 th transistor is grounded; the grid electrode of the 41 th transistor is connected with the drain electrode, and the source electrode of the 41 th transistor is connected with working voltage; the grid electrode of the 42 th transistor is connected with the grid electrode of the 41 th transistor, and the source electrode of the 42 th transistor is connected with working voltage; the drain of the 32 nd transistor is used as an output voltage terminal V_O。

The invention further comprises an active load circuit as a further optimized embodiment; the active load circuit comprises a 15 th transistor and a 25 th transistor; the 15 th transistor and the 25 th transistor are NMOS transistors; the grid electrode and the drain electrode of the 15 th transistor are connected and connected with the first drain end, and the source electrode is grounded; and the 25 th transistor is connected with the grid electrode and the drain electrode, the second drain electrode end and the source electrode to the ground.

As a further preferred embodiment of the present invention, the bias circuit further comprises a 7 th transistor, an 8 th transistor, a 9 th transistor, a 10 th transistor, a 5 th transistor, a current source; the 7 th transistor, the 9 th transistor and the 10 th transistor are PMOS transistors; the 8 th transistor and the 5 th transistor are NMOS transistors; the source electrode of the 6 th transistor is connected with the working voltage, and the drain electrode of the 6 th transistor is connected with the total source electrode terminal; the source electrode of the 7 th transistor is connected with the total source electrode end, the grid electrode of the 7 th transistor is connected with the drain electrode of the 9 th transistor, and the drain electrode of the 7 th transistor is connected with the drain electrode of the 8 th transistor; the source electrode of the 8 th transistor is grounded, and the grid electrode of the 8 th transistor is connected with the grid electrode of the 10 th transistor; the source electrode of the 9 th transistor is connected with working voltage, and the grid electrode of the 9 th transistor is connected with the drain electrode of the transistor; and the source electrode of the 10 th transistor is grounded, the grid electrode of the 10 th transistor is connected with the 5 th transistor, and the drain electrode of the 10 th transistor is connected with the drain electrode of the 9 th transistor. The grid electrode of the 5 th transistor is connected with the drain electrode, and the source electrode of the transistor is grounded; the anode of the current source is connected with the working voltage, and the cathode of the current source is connected with the drain electrode of the 5 th transistor; a drain voltage of the 7 th transistor used as the upper bias voltage; a gate voltage of the 5 th transistor is used as the lower bias voltage.

The embodiment of the application adopts at least one technical scheme which can achieve the following beneficial effects: the amplifier provided by the invention is a low-voltage field effect transistor amplifier with anti-electromagnetic interference capability, improves the original amplifier, improves the equivalent transconductance by using a positive feedback structure, improves the signal-to-noise ratio and cut-off frequency of the circuit while improving the direct current performance of the circuit, and enhances the anti-electromagnetic interference (EMI) capability; because the amplifier adopts a symmetrical output structure, the whole topological structure of the circuit is highly symmetrical, the highly symmetrical conversion rate is realized, and the EMI resistance of the circuit is comprehensively improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

FIG. 1 is a block diagram of a conventional substrate input amplifier;

FIG. 2 is a block diagram of a substrate input amplifier with a positive feedback structure of the present invention;

FIG. 3 is a block diagram of a substrate input amplifier with a positive feedback structure and a filter circuit in accordance with the present invention;

FIG. 4 is a block diagram of an input amplifier with a positive feedback structure and filter circuit and dual input stage substrate according to the present invention;

FIG. 5 is a graph of the amplitude-frequency characteristics of the low sensitivity substrate input amplifier of the present invention;

FIG. 6 is a graph of the DC transfer characteristic of the low sensitivity substrate input amplifier of the present invention;

FIG. 7 is a graph of the large signal time domain response simulation results for the low sensitivity substrate input amplifier of the present invention;

FIG. 8 is a graph of the input equivalent offset voltage simulation results for the low sensitivity substrate input amplifier of the present invention;

FIG. 9 is a graph of the simulation results of the output spectral density (PSD) of the low sensitivity substrate input amplifier of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The invention provides a low-sensitivity substrate input amplifier aiming at some electromagnetic performance defects of the existing substrate input amplifier. The structure adopts a positive feedback structure to improve equivalent input transconductance of a substrate input stage, improves direct current characteristic nonlinearity of the substrate input structure through an input voltage division structure, adopts a double-input stage structure to ensure good alternating current characteristic of the whole amplifier, and adopts a symmetrical topological structure to ensure high symmetry of a circuit and realize symmetrical conversion rate.

The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.

Fig. 1 is a structure diagram of a conventional substrate input amplifier, which includes a 1 st transistor M1, a 2 nd transistor M2 as a main amplifying device, and a 3 rd transistor M3 as an active load; the 41 st transistor M41 and the 42 th transistor M42 are symmetric output stage devices; vin + and Vin-are respectively a differential signal positive input end and a differential signal negative input end; vo is a signal output end; IB is a current source for generating a bias at the 6 th transistor M6; operating voltage is V_DDThe circuit ground is Vss. Equivalent transconductance (g) of substrate input MOS transistor in conventional substrate input amplifier_mb) Transconductance (g) of a gate drive transistor is generally higher than that of a gate drive transistor under the same conditions_m) Much lower (e.g., 1/5-1/2 g)_mb) Further, the circuit has low cut-off frequency, low dc gain, low signal-to-noise ratio and other limited performances, which results in high electromagnetic sensitivity, and when the circuit is subjected to electromagnetic interference, the circuit cannot work normally or efficiently.

Fig. 2 is a block diagram of a substrate input amplifier with a positive feedback structure of the present invention. A low-sensitivity substrate input amplifier comprising at least one positive feedback structure; the positive feedback structure includes an 11 th transistor M11, a 21 st transistor M21, a 12 th transistor M12, a 22 nd transistor M22, a 13 th transistor M13, and a 23 th transistor M23; the 11 th transistor, the 12 th transistor, the 13 th transistor, the 21 st transistor, the 22 nd transistor and the 23 rd transistor are all PMOS transistors; the substrates of the 11 th transistor, the 12 th transistor and the 13 th transistor are connected to serve as a first substrate end; the substrates of the 21 st transistor, the 22 nd transistor and the 23 rd transistor are connected to serve as second substrate ends; sources of the 11 th transistor, the 12 th transistor, the 13 th transistor, the 21 st transistor, the 22 nd transistor and the 23 rd transistor are connected to serve as a total source electrode terminal; the drain electrode of the 11 th transistor, the drain electrode of the 12 th transistor, the grid electrode of the 13 th transistor and the grid electrode of the 21 st transistor are connected to form a first grid electrode terminal; the drain of the 21 st transistor, the drain of the 22 nd transistor, the gate of the 23 rd transistor and the gate of the 11 th transistor are connected to form a second gate terminal; the drain electrode of the 13 th transistor is a first drain end; a drain of the 23 rd transistor is a second drain terminal.

When the differential amplifier is used for realizing amplification, a positive input end Vin + of a differential signal is connected with a first substrate end of the positive feedback structure; and a negative input end Vin-of the differential signal is connected with the second substrate end of the positive feedback structure.

It should be noted that the present embodiment implements the principle of positive feedback. The drain voltage of the 12 th transistor is fed back to the gate of the 21 st transistor, and the drain voltage of the 22 nd transistor is fed back to the gate of the 11 th transistor to change the drain currents of the 11 th transistor and the 21 st transistor, so that equivalent input transconductance improvement is realized. According to the small signal equivalent model analysis, the equivalent transconductance satisfies the following conditions:

wherein, g_m1Is the gate transconductance of the 11 th transistor (or the 21 st transistor), g_mb1Bulk transconductance of the 11 th transistor (or the 21 st transistor), g_m2Is the gate transconductance of transistor 12 (or transistor 22), g_mb2Is the bulk transconductance of the 12 th transistor (or the 22 nd transistor), if the ratio N of the gate transconductance of the 12 th transistor M12 and the gate transconductance of the 11 th transistor M11 is

Then

That is, the equivalent input transconductance of the circuit can be improved to the original value

And (4) doubling. The improvement of equivalent transconductance can improve the DC performance, signal-to-noise ratio andcut off the frequency, so the anti-EMI capability is enhanced. In addition, the improvement of the equivalent transconductance also reduces the modulus of the transfer function to a certain extent, and further enhances the electromagnetic compatibility of the whole amplifier.

It should be noted that since the N value is shifted due to device mismatch, process variation and temperature variation, when N is close to 1, the circuit is unstable due to too strong positive feedback, and therefore, the feedback strength needs to be properly selected to ensure the circuit stability. In this embodiment, N is equal to 5/4, which can increase the transconductance by about 10 times without affecting the stability of the circuit.

In a further optimized embodiment of the invention, the device also comprises a bias circuit; the bias circuit includes a 6 th transistor M6, a 14 th transistor M14, a 24 th transistor M24; the 6 th transistor is a PMOS transistor; the 14 th transistor and the 24 th transistor are NMOS transistors; the source of the 6 th transistor is connected with a working voltage V_DDThe grid electrode is connected with a bias voltage Vb0, and the drain electrode is connected with the total source electrode terminal; the source of the 14 th transistor is grounded V_SSThe grid is connected with a bias voltage Vb, and the drain is connected with the first grid end; the source of the 24 th transistor is grounded, the grid of the 24 th transistor is connected with a bias voltage, and the drain of the 24 th transistor is connected with the second grid terminal.

As a further optimized embodiment of the invention, the invention also comprises a symmetrical output stage circuit; the symmetrical output stage circuit includes a 31 st transistor M31, a 32 nd transistor M32, a 41 st transistor M41, a 42 th transistor M42; the 41 st transistor and the 42 th transistor are PMOS transistors; the 31 st transistor and the 32 nd transistor are NMOS transistors; the drain electrode of the 31 st transistor is connected with the drain electrode of the 41 th transistor, the grid electrode of the 31 st transistor is connected with the first drain electrode end, and the source electrode of the 31 st transistor is grounded; the drain electrode of the 32 th transistor is connected with the drain electrode of the 42 th transistor, the grid electrode of the 32 th transistor is connected with the second drain electrode end, and the source electrode of the 32 th transistor is grounded; the grid electrode of the 41 th transistor is connected with the drain electrode, and the source electrode of the 41 th transistor is connected with working voltage; the grid electrode of the 42 th transistor is connected with the grid electrode of the 41 th transistor, and the source electrode of the 42 th transistor is connected with working voltage; a drain of the 32 th transistor serves as an output voltage terminal.

The invention further comprises an active load circuit as a further optimized embodiment; the active load circuit includes a 15 th transistor M15, a 25 th transistor M25; the 15 th transistor and the 25 th transistor are NMOS transistors; the grid electrode and the drain electrode of the 15 th transistor are connected and connected with the first drain end, and the source electrode is grounded; and the 25 th transistor is connected with the grid electrode and the drain electrode, the second drain electrode end and the source electrode to the ground.

Fig. 3 is a block diagram of a substrate input amplifier with a positive feedback structure and a filter circuit in accordance with the present invention. As a further preferred embodiment of the present invention, the low-sensitivity substrate input amplifier comprises an improved positive feedback structure, wherein the improved positive feedback structure comprises a filter circuit and a first positive feedback structure (referred to as a first positive feedback structure); the first positive feedback structure is the positive feedback structure shown in fig. 2; the filter circuit comprises a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C1, a first substrate-source capacitor Cbs1 and a second substrate-source capacitor Cbs 2; one end of the first resistor is connected with a differential signal positive input end Vin +, and the other end of the first resistor is connected with a first substrate end of the first positive feedback structure; the positive electrode of the first capacitor is connected with the first substrate end of the first positive feedback structure, and the negative electrode of the first capacitor is grounded; one end of the first substrate source capacitor is connected with the total source electrode end, and the other end of the first substrate source capacitor is connected with the first substrate end of the first positive feedback structure; one end of the second resistor is connected with the negative input end Vin-of the differential signal, and the other end of the second resistor is connected with the second substrate end of the first positive feedback structure; the positive electrode of the second capacitor is connected with the second substrate end of the first positive feedback structure, and the negative electrode of the second capacitor is grounded; one end of the second substrate source capacitor is connected with the total source electrode end, and the other end of the second substrate source capacitor is connected with the second substrate end of the first positive feedback structure.

It should be noted that the first resistor and the second resistor connected to the differential input end can reduce the bias voltage directly applied to the parasitic substrate source triode of the input pair, and the proper selection of the resistance values of the first resistor and the second resistor can ensure that the parasitic triode always maintains the reverse bias state without being influenced by the substrate input voltage, thereby correcting the nonlinearity of the direct current characteristic of the amplifier and improving the anti-electromagnetic interference capability of the amplifier. Meanwhile, the first resistor, the second resistor and the circuit equivalent input capacitor C_inAnd a low-pass filtering structure is formed, so that the influence of high-frequency electromagnetic interference can be effectively inhibited. In addition, an input voltage drop capacitor, finger, is adoptedThe first substrate source capacitor Cbs1 and the second substrate source capacitor Cbs2 can reduce offset voltage caused by parasitic capacitance and improve the electromagnetic compatibility of the circuit in the whole frequency band. Preferably, the first resistance and the second resistance have a value of 500k Ω; the first capacitor and the second capacitor have a value of 200 fF; the first substrate source capacitance and the second substrate source capacitance have a value of 3 pF.

As a further optimized embodiment, in the embodiment shown in fig. 3, the active load circuit, the symmetrical output stage circuit, and the bias circuit described in the embodiment of fig. 2 are included. The specific structure will not be described in detail.

Fig. 4 is a block diagram of a substrate input amplifier with a positive feedback structure and filter circuit and dual input stages according to the present invention. It should be noted that, after the positive feedback structure and the filter circuit are adopted, the offset voltage of the amplifier is greatly reduced compared with the existing substrate input structure. However, due to the use of resistive and capacitive devices with large resistance values, some ac characteristics of the amplifier are impaired, such as: phase margin and gain bandwidth product. The insufficient phase margin causes the circuit to generate voltage jitter or peak under the transient electromagnetic interference disturbance, and the voltage jitter or peak can seriously affect the operation of the circuit and a post-stage circuit due to conduction and coupling among circuit modules, so that the electromagnetic compatibility of the whole circuit or system is limited. If additional compensation measures such as miller compensation are adopted in the circuit structure, on one hand, area and power consumption are increased to a great extent, and on the other hand, asymmetry and nonlinearity of the circuit may be caused, thereby causing a corresponding electromagnetic sensitivity problem. Therefore, in order to ensure good alternating current characteristics of the whole amplifier, a double-input-stage structure can be adopted to realize high electromagnetic compatibility.

As a further preferred embodiment of the present invention, the low-sensitivity substrate input amplifier comprises the improved positive feedback structure and further comprises a second positive feedback structure (for short, a second positive feedback structure); the second positive feedback structure is still the positive feedback structure shown in fig. 2; another embodiment of the improved positive feedback structure comprises a first positive feedback structure; for the present embodiment, the first drain terminal of the first positive feedback structure is connected to the first drain terminal of the second positive feedback structure; the second drain terminal of the first positive feedback structure is connected with the second drain terminal of the second positive feedback structure; a first gate terminal of the first positive feedback structure is connected with a first gate terminal of the second positive feedback structure; the second grid terminal of the first positive feedback structure is connected with the second grid terminal of the second positive feedback structure; the differential signal positive input end is connected with the first substrate end of the second positive feedback structure; and the negative input end of the differential signal is connected with the second substrate end of the second positive feedback structure.

In this embodiment, the first positive feedback structure serves as a secondary input stage; the second positive feedback structure is used as a main input stage, and a double-input stage structure is formed.

In fig. 4, the secondary input stage is the embodiment shown in fig. 2, and is not described herein again; since the first positive feedback structure and the second positive feedback structure have the same principle, in order to distinguish the primary input stage element from the secondary input stage element, the following description is provided: the second positive feedback structure used as the main input stage comprises 11 × transistor M11, 21 × transistor M21, 12 × transistor M12, 22 × transistor M22, 13 × transistor M13, and 23 × transistor M23; the 11 th transistor, the 12 th transistor, the 13 th transistor, the 21 st transistor, the 22 nd transistor and the 23 rd transistor are all PMOS transistors; the substrates of the 11 th transistor, the 12 th transistor and the 13 th transistor are connected to serve as a first substrate end of the second positive feedback structure; the substrates of the 21 st transistor, the 22 nd transistor and the 23 th transistor are connected to serve as a second substrate end of the second positive feedback structure; the sources of the 11 th transistor, the 12 th transistor, the 13 th transistor, the 21 st transistor, the 22 nd transistor and the 23 th transistor are connected to be used as a total source terminal of the second positive feedback structure; the drain of the 11 th transistor, the drain of the 12 th transistor, the gate of the 13 th transistor and the gate of the 21 st transistor are connected to be used as a first gate terminal of the second positive feedback structure; the drain of the 21 st transistor, the drain of the 22 st transistor, the gate of the 23 st transistor and the gate of the 11 th transistor are connected to be used as a second gate terminal of the second positive feedback structure; the drain of the 13 th transistor is a first drain terminal of the second positive feedback structure; and the drain of the 23 th transistor is a second drain terminal of the second positive feedback structure.

As a further optimized embodiment, in the embodiment shown in fig. 4, the active load circuit, the symmetrical output stage circuit, and the bias circuit described in the embodiment of fig. 2 are included. The following are described one by one.

As a general embodiment of the present invention, in the embodiment of fig. 4, when the first positive feedback structure and the second positive feedback structure share one active load circuit, the active load circuit includes a 15 th transistor M15, a 25 th transistor M25; the 15 th transistor and the 25 th transistor are NMOS transistors; the grid electrode and the drain electrode of the 15 th transistor are connected and connected with the first drain end of the first positive feedback structure and the first drain end of the second positive feedback structure, and the source electrode is grounded; and the 25 th transistor is connected with the drain electrode, the second drain electrode ends of the first positive feedback structure and the second positive feedback structure, and the source electrode is grounded.

As a further preferred embodiment of the present invention, in the embodiment shown in fig. 4, when the first positive feedback structure and the second positive feedback structure are respectively connected to an active load circuit, the active load circuit includes a first active load circuit and a second active load circuit.

The first active load circuit includes a 15 th transistor M15, a 25 th transistor M25; the 15 th transistor and the 25 th transistor are NMOS transistors; the grid electrode and the drain electrode of the 15 th transistor are connected and connected with the first drain end of the first positive feedback structure, and the source electrode is grounded; and the 25 th transistor is connected with the grid electrode and the drain electrode, is connected with the second drain end of the first positive feedback structure, and is grounded at the source electrode.

The second active load circuit comprises a 15 th transistor M15 and a 25 th transistor M25; the 15 th transistor and the 25 th transistor are NMOS transistors; the grid electrode and the drain electrode of the 15 th transistor are connected and connected with the first drain electrode end of the second positive feedback structure, and the source electrode is grounded; and the grid electrode and the drain electrode of the 25 th transistor are connected with the second drain electrode end of the second positive feedback structure, and the source electrode is grounded.

When the first active load circuit and the second active load circuit are included, preferably, a first drain terminal of the first positive feedback structure is connected with a first drain terminal of the second positive feedback structure; and the second drain terminal of the first positive feedback structure is connected with the second drain terminal of the second positive feedback structure.

As a general embodiment of the present invention, in the embodiment shown in fig. 4, when the total source terminal of the first positive feedback structure and the total source terminal of the second positive feedback structure share a bias circuit, the bias circuit includes a 6 th transistor M6, a 14 th transistor M14, and a 24 th transistor M24, as in the embodiment shown in fig. 2; the 6 th transistor is a PMOS transistor; the 14 th transistor and the 24 th transistor are NMOS transistors; the source electrode of the 6 th transistor is connected with working voltage, the grid electrode of the 6 th transistor is connected with bias voltage Vb0, and the drain electrode of the 6 th transistor is connected with the total source electrode terminal; the source electrode of the 14 th transistor is grounded, the grid electrode of the 14 th transistor is connected with a lower bias voltage Vb, and the drain electrode of the 14 th transistor is connected with the first grid electrode terminal; the source of the 24 th transistor is grounded, the grid of the 24 th transistor is connected with a bias voltage, and the drain of the 24 th transistor is connected with the second grid terminal.

As a further preferred embodiment of the present invention, in the embodiments of FIGS. 2 to 4, the bias circuit further includes a 7 th transistor M7, an 8 th transistor M8, a 9 th transistor M9, a 10 th transistor M10, a 5 th transistor M5, and a current source IB; the 7 th transistor, the 9 th transistor and the 10 th transistor are PMOS transistors; the 8 th transistor and the 5 th transistor are NMOS transistors; the source electrode of the 6 th transistor is connected with the working voltage, and the drain electrode of the 6 th transistor is connected with the total source electrode terminal; the source electrode of the 7 th transistor is connected with the total source electrode end, the grid electrode of the 7 th transistor is connected with the drain electrode of the 9 th transistor, and the drain electrode of the 7 th transistor is connected with the drain electrode of the 8 th transistor; the source electrode of the 8 th transistor is grounded, and the grid electrode of the 8 th transistor is connected with the grid electrode of the 10 th transistor; the source electrode of the 9 th transistor is connected with working voltage, and the grid electrode of the 9 th transistor is connected with the drain electrode of the transistor; and the source electrode of the 10 th transistor is grounded, the grid electrode of the 10 th transistor is connected with the 5 th transistor, and the drain electrode of the 10 th transistor is connected with the drain electrode of the 9 th transistor. The grid electrode of the 5 th transistor is connected with the drain electrode, and the source electrode of the transistor is grounded; the anode of the current source is connected with the working voltage, and the cathode of the current source is connected with the drain electrode of the 5 th transistor; a drain voltage of the 7 th transistor used as the upper bias voltage; a gate voltage of the 5 th transistor is used as the lower bias voltage.

As a further optimized embodiment, in the embodiment shown in fig. 4, when the total source terminal of the first positive feedback structure and the total source terminal of the second positive feedback structure are respectively connected to a bias circuit, in the further optimized embodiment of the present invention, the bias circuit is divided into a first bias circuit and a second bias circuit.

The first bias circuit comprises a 6 th transistor, a 14 th transistor and a 24 th transistor; the 6 th transistor is a PMOS transistor; the 14 th transistor and the 24 th transistor are NMOS transistors; the source electrode of the 6 th transistor is connected with working voltage, the grid electrode of the 6 th transistor is connected with the upper bias voltage of the first bias circuit, and the drain electrode of the 6 th transistor is connected with the total source electrode terminal of the first positive feedback structure; the source electrode of the 14 th transistor is grounded, the grid electrode of the 14 th transistor is connected with the lower bias voltage of the first bias circuit, and the drain electrode of the 14 th transistor is connected with the first grid electrode terminal of the first positive feedback structure; and the source electrode of the 24 th transistor is grounded, the grid electrode of the 24 th transistor is connected with the lower bias voltage of the first bias circuit, and the drain electrode of the 24 th transistor is connected with the second grid electrode terminal of the first positive feedback structure.

The second bias circuit comprises a 6 th transistor M6, a 14 th transistor M14, a 24 th transistor M24; the 6 th transistor is a PMOS transistor; the 14 th transistor and the 24 th transistor are NMOS transistors; the source electrode of the 6 th transistor is connected with working voltage, the grid electrode of the 6 th transistor is connected with upper bias voltage of the second bias circuit, and the drain electrode of the 6 th transistor is connected with the total source electrode terminal of the second positive feedback structure; the source electrode of the 14 th transistor is grounded, the grid electrode of the 14 th transistor is connected with the lower bias voltage of the second bias circuit, and the drain electrode of the 14 th transistor is connected with the first grid electrode terminal of the second positive feedback structure; and the source electrode of the 24 th transistor is grounded, the grid electrode of the 24 th transistor is connected with the lower bias voltage of the second bias circuit, and the drain electrode of the 24 th transistor is connected with the second grid electrode terminal of the second positive feedback structure.

As a further preferred embodiment of the present invention, the first bias circuit further comprises a 7 th transistor, an 8 th transistor, a 9 th transistor, a 10 th transistor, a 5 th transistor, a current source; the 7 th transistor, the 9 th transistor and the 10 th transistor are PMOS transistors; the 8 th transistor and the 5 th transistor are NMOS transistors; the source electrode of the 6 th transistor is connected with working voltage, and the drain electrode of the 6 th transistor is connected with the total source electrode terminal of the first positive feedback structure; the source electrode of the 7 th transistor is connected with the total source electrode end of the first positive feedback structure, the grid electrode of the 7 th transistor is connected with the drain electrode of the 9 th transistor, and the drain electrode of the 7 th transistor is connected with the drain electrode of the 8 th transistor; the source electrode of the 8 th transistor is grounded, and the grid electrode of the 8 th transistor is connected with the grid electrode of the 10 th transistor; the source electrode of the 9 th transistor is connected with working voltage, and the grid electrode of the 9 th transistor is connected with the drain electrode of the transistor; and the source electrode of the 10 th transistor is grounded, the grid electrode of the 10 th transistor is connected with the 5 th transistor, and the drain electrode of the 10 th transistor is connected with the drain electrode of the 9 th transistor. The grid electrode of the 5 th transistor is connected with the drain electrode, and the source electrode of the transistor is grounded; the anode of the current source is connected with the working voltage, and the cathode of the current source is connected with the drain electrode of the 5 th transistor; a drain voltage of the 7 th transistor used as an upper bias voltage of the first bias circuit; and the gate voltage of the 5 th transistor is used as the lower bias voltage of the first bias circuit.

As a further preferred embodiment of the present invention, the second bias circuit further comprises a 7 th transistor M7, an 8 th transistor M8, a 9 th transistor, a 10 th transistor, a 5 th transistor, a current source; the 7 th transistor, the 9 th transistor and the 10 th transistor are PMOS transistors; the 8 th transistor and the 5 th transistor are NMOS transistors; the source electrode of the 6 th transistor is connected with the working voltage, and the drain electrode of the 6 th transistor is connected with the total source electrode terminal of the second positive feedback structure; the source electrode of the 7 th transistor is connected with the total source electrode end of the second positive feedback structure, the grid electrode of the 7 th transistor is connected with the drain electrode of the 9 th transistor, and the drain electrode of the 7 th transistor is connected with the drain electrode of the 8 th transistor; the source electrode of the 8 th transistor is grounded, and the grid electrode of the 8 th transistor is connected with the grid electrode of the 10 th transistor; the source electrode of the 9 th transistor is connected with working voltage, and the grid electrode of the 9 th transistor is connected with the drain electrode of the transistor; and the source electrode of the 10 th transistor is grounded, the grid electrode of the 10 th transistor is connected with the 5 th transistor, and the drain electrode of the 10 th transistor is connected with the drain electrode of the 9 th transistor. The grid electrode of the 5 th transistor is connected with the drain electrode, and the source electrode of the transistor is grounded; the anode of the current source is connected with the working voltage, and the cathode of the current source is connected with the drain electrode of the 5 th transistor; a drain voltage of the 7 th transistor used as an upper bias voltage of the second bias circuit; and the gate voltage of the 5 th transistor is used as the lower bias voltage of the second bias circuit.

Wherein, the 9 th transistor, the 10 th transistor, the 5 th transistor and the current source are devices shared by the first bias circuit and the second bias circuit.

When a first bias circuit and a second bias circuit are included, preferably, a first gate terminal of the first positive feedback structure and a first gate terminal of the second positive feedback structure are connected; a second gate terminal of the first positive feedback structure and a second gate terminal of the second positive feedback structure are connected.

It should be noted that, larger resistor and capacitor devices (the first resistor, the first capacitor, the second resistor, and the second capacitor) are adopted in the secondary input stage circuit to improve the electromagnetic compatibility of the whole amplifier. Meanwhile, the improved structure is applied to the secondary input stage, so that the secondary input stage does not have serious influence on a main input stage circuit, and the alternating current characteristic of the amplifier is good. Through the matching use of the primary input stage and the secondary input stage, the circuit has sufficient phase margin and proper gain bandwidth product, additional compensation measures in the form of Miller compensation and the like are not needed, and circuit asymmetry and nonlinearity caused by a compensation structure are effectively avoided. Meanwhile, the amplifier adopts a symmetrical output structure, the overall topological structure of the circuit is highly symmetrical, the highly symmetrical conversion rate is realized, and the electromagnetic compatibility reliability of the circuit is comprehensively improved. In addition, the primary input stage and the secondary input stage have the same structural composition and transistor size, so that the overall design of the amplifier is easy to realize.

It should be noted that in the embodiment shown in fig. 4, when other characters in the labels are the same, the transistors with the "mark" have the same parameters as the transistors without the "mark", for example, the 11 th transistor M11 has the same parameters as the 11 th transistor M11; the "1N" transistor and the "2N" transistor have the same parameters (N is 1 to 5), for example, the 11 th transistor M11 and the 21 st transistor M21 have the same parameters; in addition, the transistors M31, M32 have identical parameters; the transistors M41, M42 have exactly the same parameters.

It should be noted that, in all embodiments of the present invention, if no specific reference is made, the NMOS transistor substrate is connected to the lowest voltage and the PMOS transistor substrate is connected to the highest voltage by default.

The main device parameters of the low sensitivity substrate input amplifier of the present invention are shown in the following table.

Device with a metal layer	Parameter(s)	Device with a metal layer	Parameter(s)
				M11/M21/M11/M21	40μm/1μm	M6	500μm/1μm
M12/M22/M12/M22	50μm/1μm	M32/M31	40μm/2μm
				M13/M23/M13/M23	50μm/1μm	M42/M41	120μm/2μm
M14/M24/M14/M24	40μm/2μm	R1/R2	500kΩ
				M15/M25/M15/M25	40μm/2μm	C1/C2	200fF
M5	40μm/2μm	Cbs1/Cbs2	3pF

FIG. 5 is a graph of the amplitude-frequency characteristics of the low sensitivity substrate input amplifier of the present invention; the gain of the low-sensitivity substrate input amplifier of the embodiment is 51dB, the gain-bandwidth product is 1.6MHz, the phase margin is 70 °, and the amplitude-frequency characteristic and the phase-frequency characteristic are shown in fig. 5.

Fig. 6 is a simulation result of the dc transfer characteristic of the low-sensitivity substrate input amplifier of the present embodiment. The input signal range is 0V to 1V. Compared with the existing substrate input amplifier, the amplifier provided by the invention has the advantages that the structure has higher linearity and wider input signal swing.

FIG. 7 is a graph of the simulation results of the large signal time domain response of the low sensitivity substrate input amplifier of the present invention. The large-signal transient response is obtained by applying square waves with the amplitude of 1Vpp and the frequency of 100kHz to a voltage following structure, and the transient response curves of the electromagnetic compatibility high-reliability low-voltage amplifier and the existing substrate input amplifier are shown in the figure. Compared with the existing substrate input amplifier, the amplifier structure designed by the method has the advantages of symmetrical conversion rate, small jitter and good transient characteristics.

FIG. 8 is a graph showing the simulation result of the input equivalent offset voltage of the low-sensitivity substrate input amplifier of this embodiment. And when the input end has electromagnetic interference of 1V and the frequency range of 1Hz to 4GHz, the simulation result of the equivalent offset voltage is obtained. The detuning of the structure is reduced by about one order of magnitude compared to the prior art substrate input amplifier: the maximum value of the offset voltage caused by electromagnetic interference in the structure of the invention is only about 50 mV.

Fig. 9 is a graph showing the simulation result of the output spectral density (PSD) of the low-sensitivity substrate input amplifier of the present embodiment. The simulation results of the output spectral density (PSD) are shown for 100kHz, 1Vpp emi at the amplifier input. It can be seen that the peak value of the output PSD of the low-sensitivity substrate input amplifier of the present embodiment is significantly reduced compared with the existing substrate input structure, and the peak values of the harmonic component and the fundamental component are reduced by about 60dBm compared with the existing structure, so that the low-sensitivity substrate input amplifier has a lower electromagnetic radiation characteristic, and the electromagnetic compatibility performance is significantly improved.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A low-sensitivity substrate input amplifier is characterized by comprising at least one positive feedback structure;

the positive feedback structure comprises an 11 th transistor, a 12 th transistor, a 13 th transistor, a 21 st transistor, a 22 nd transistor and a 23 rd transistor;

the 11 th transistor, the 12 th transistor, the 13 th transistor, the 21 st transistor, the 22 nd transistor and the 23 rd transistor are all PMOS transistors;

the substrates of the 11 th transistor, the 12 th transistor and the 13 th transistor are connected to serve as a first substrate end; the substrates of the 21 st transistor, the 22 nd transistor and the 23 rd transistor are connected to serve as second substrate ends;

sources of the 11 th transistor, the 12 th transistor, the 13 th transistor, the 21 st transistor, the 22 nd transistor and the 23 rd transistor are connected to serve as a total source electrode terminal;

the drain electrode of the 11 th transistor, the drain electrode of the 12 th transistor, the grid electrode of the 13 th transistor and the grid electrode of the 21 st transistor are connected to form a first grid electrode terminal;

the drain of the 21 st transistor, the drain of the 22 nd transistor, the gate of the 23 rd transistor and the gate of the 11 th transistor are connected to form a second gate terminal;

the drain electrode of the 13 th transistor is a first drain end;

the drain of the 23 rd transistor is a second drain terminal;

the low-sensitivity substrate input amplifier comprises an improved positive feedback structure, wherein the improved positive feedback structure comprises a first positive feedback structure and a filter circuit;

the filter circuit comprises a first resistor, a second resistor, a first capacitor, a second capacitor, a first substrate source capacitor and a second substrate source capacitor;

one end of the first resistor is connected with a differential signal positive input end, and the other end of the first resistor is connected with a first substrate end of a first positive feedback structure;

the positive electrode of the first capacitor is connected with the first substrate end of the first positive feedback structure, and the negative electrode of the first capacitor is grounded;

one end of the first substrate source capacitor is connected with the total source electrode end, and the other end of the first substrate source capacitor is connected with the first substrate end of the first positive feedback structure;

one end of the second resistor is connected with the negative input end of the differential signal, and the other end of the second resistor is connected with the second substrate end of the first positive feedback structure;

the positive electrode of the second capacitor is connected with the second substrate end of the first positive feedback structure, and the negative electrode of the second capacitor is grounded;

one end of the second substrate source capacitor is connected with the total source electrode end, and the other end of the second substrate source capacitor is connected with the second substrate end of the first positive feedback structure;

said low sensitivity substrate input amplifier further comprising a second of said positive feedback structures;

the first drain terminal of the first positive feedback structure is connected with the first drain terminal of the second positive feedback structure;

the second drain terminal of the first positive feedback structure is connected with the second drain terminal of the second positive feedback structure;

a first gate terminal of the first positive feedback structure is connected with a first gate terminal of the second positive feedback structure;

the second grid terminal of the first positive feedback structure is connected with the second grid terminal of the second positive feedback structure;

the differential signal positive input end is connected with the first substrate end of the second positive feedback structure;

the negative input end of the differential signal is connected with the second substrate end of the second positive feedback structure;

the low-sensitivity substrate input amplifier comprises a first bias circuit and a second bias circuit;

the first bias circuit includes a 6 th transistor, a 14 th transistor, and a 24 th transistor;

the 6 th transistor is a PMOS transistor;

the 14 th transistor and the 24 th transistor are NMOS transistors;

the source electrode of the 6 th transistor is connected with working voltage, the grid electrode of the 6 th transistor is connected with bias voltage, and the drain electrode of the 6 th transistor is connected with the total source electrode terminal of the first positive feedback structure;

the source electrode of the 14 th transistor is grounded, the grid electrode of the 14 th transistor is connected with a lower bias voltage, and the drain electrode of the 14 th transistor is connected with the first grid electrode terminal of the first positive feedback structure;

the source electrode of the 24 th transistor is grounded, the grid electrode of the 24 th transistor is connected with a lower bias voltage, and the drain electrode of the 24 th transistor is connected with the second grid electrode terminal of the first positive feedback structure;

the second bias circuit comprises a 6 th transistor, a 14 th transistor and a 24 th transistor;

the 6 th transistor is a PMOS transistor;

the 14 th transistor and the 24 th transistor are NMOS transistors;

the source electrode of the 6 th transistor is connected with working voltage, the grid electrode of the 6 th transistor is connected with bias voltage, and the drain electrode of the 6 th transistor is connected with the total source electrode terminal of the second positive feedback structure;

the source electrode of the 14 th transistor is grounded, the grid electrode of the 14 th transistor is connected with a bias voltage, and the drain electrode of the 14 th transistor is connected with the first grid electrode terminal of the second positive feedback structure;

and the source electrode of the 24 th transistor is grounded, the grid electrode of the 24 th transistor is connected with a bias voltage, and the drain electrode of the 24 th transistor is connected with the second grid electrode terminal of the second positive feedback structure.

2. The low sensitivity substrate input amplifier of claim 1, comprising a symmetrical output stage circuit;

the symmetrical output stage circuit comprises a 31 st transistor, a 32 nd transistor, a 41 st transistor and a 42 th transistor;

the 41 st transistor and the 42 th transistor are PMOS transistors;

the 31 st transistor and the 32 nd transistor are NMOS transistors;

the drain electrode of the 31 st transistor is connected with the drain electrode of the 41 th transistor, the grid electrode of the 31 st transistor is connected with the first drain electrode end, and the source electrode of the 31 st transistor is grounded;

the drain electrode of the 32 th transistor is connected with the drain electrode of the 42 th transistor, the grid electrode of the 32 th transistor is connected with the second drain electrode end, and the source electrode of the 32 th transistor is grounded;

the grid electrode of the 41 th transistor is connected with the drain electrode, and the source electrode of the 41 th transistor is connected with working voltage;

the grid electrode of the 42 th transistor is connected with the grid electrode of the 41 th transistor, and the source electrode of the 42 th transistor is connected with working voltage;

a drain of the 32 th transistor serves as an output voltage terminal.

3. The low sensitivity substrate input amplifier of claim 1, comprising an active load circuit;

the active load circuit comprises a 15 th transistor and a 25 th transistor;

the 15 th transistor and the 25 th transistor are NMOS transistors;

the grid electrode and the drain electrode of the 15 th transistor are connected and connected with the first drain end, and the source electrode is grounded;

and the 25 th transistor is connected with the grid electrode and the drain electrode, the second drain electrode end and the source electrode to the ground.

4. The low sensitivity substrate input amplifier of claim 1,

the first bias circuit further comprises a 7 th transistor, an 8 th transistor, a 9 th transistor, a 10 th transistor, a 5 th transistor and a current source;

the 7 th transistor, the 9 th transistor and the 10 th transistor are PMOS transistors;

the 8 th transistor and the 5 th transistor are NMOS transistors;

the source electrode of the 6 th transistor is connected with working voltage, and the drain electrode of the 6 th transistor is connected with the total source electrode terminal of the first positive feedback structure;

the source electrode of the 7 th transistor is connected with the total source electrode end of the first positive feedback structure, the grid electrode of the 7 th transistor is connected with the drain electrode of the 9 th transistor, and the drain electrode of the 7 th transistor is connected with the drain electrode of the 8 th transistor;

the source electrode of the 8 th transistor is grounded, and the grid electrode of the 8 th transistor is connected with the grid electrode of the 10 th transistor;

the source electrode of the 9 th transistor is connected with working voltage, and the grid electrode of the 9 th transistor is connected with the drain electrode of the transistor;

the source electrode of the 10 th transistor is grounded, the grid electrode of the 10 th transistor is connected with the 5 th transistor, and the drain electrode of the 10 th transistor is connected with the drain electrode of the 9 th transistor;

the grid electrode of the 5 th transistor is connected with the drain electrode, and the source electrode of the transistor is grounded;

the anode of the current source is connected with the working voltage, and the cathode of the current source is connected with the drain electrode of the 5 th transistor;

a drain voltage of the 7 th transistor used as an upper bias voltage of the first bias circuit;

a gate voltage of the 5 th transistor used as a lower bias voltage of the first bias circuit;

the second bias circuit further comprises a 7 th transistor, an 8 th transistor, a 9 th transistor, a 10 th transistor, a 5 th transistor and a current source;

the 9 th transistor, the 10 th transistor, the 5 th transistor and the current source are devices shared by the first bias circuit and the second bias circuit;

the 7 th transistor is a PMOS transistor;

the 8 th transistor is an NMOS transistor;

the source electrode of the 6 th transistor is connected with the working voltage, and the drain electrode of the 6 th transistor is connected with the total source electrode terminal of the second positive feedback structure;

the source electrode of the 7 th transistor is connected with the total source electrode end of the second positive feedback structure, the grid electrode of the 7 th transistor is connected with the drain electrode of the 9 th transistor, and the drain electrode of the 7 th transistor is connected with the drain electrode of the 8 th transistor;

a drain voltage of the 7 th transistor used as an upper bias voltage of the second bias circuit;

the gate voltage of the 5 th transistor is also used as a lower bias voltage of the second bias circuit.

5. The low sensitivity substrate input amplifier of claim 1,

the first resistor and the second resistor have a value of 500k Ω;

the first capacitor and the second capacitor have a value of 200 fF;

the first substrate source capacitance and the second substrate source capacitance have a value of 3 pF.