CN106787652B - A kind of dynamic suitable for buck converter output DC maladjustment eliminates circuit - Google Patents

A kind of dynamic suitable for buck converter output DC maladjustment eliminates circuit Download PDF

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Publication number
CN106787652B
CN106787652B CN201710070538.3A CN201710070538A CN106787652B CN 106787652 B CN106787652 B CN 106787652B CN 201710070538 A CN201710070538 A CN 201710070538A CN 106787652 B CN106787652 B CN 106787652B
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resistor
capacitor
ripple
voltage
circuit
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CN106787652A (en
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明鑫
赵佳祎
高笛
魏秀凌
唐韵杨
王卓
张波
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

A kind of dynamic suitable for buck converter output DC maladjustment eliminates circuit, belongs to electronic circuit technology field.Including ripple generation circuit and ripple supercircuit, the present invention directly samples upper power tube S by the way that duty cycle information is added in ripple generation circuit1With lower power tube S2Voltage at connecting node SW is superimposed upon feedback voltage V to simulate generation and the ripple of inductive current same-phaseFBAbove so that feedback voltage VFBWith preset reference voltage VREFIt is equal, to control the normal overturning of pulse width modulated comparator PWM, enhance system stability, avoid the too small resonance problems for leading to output voltage delayed phase and generating of equivalent series resistance by output capacitance, increase converter output voltage precision, contradiction of the valley detection pattern of traditional ripple control between system stability and accuracy is overcome, can accomplish the DC maladjustment amount for dynamically eliminating output voltage under different application condition, that is, different input voltages and output voltage.

Description

Dynamic elimination circuit suitable for output direct current offset of buck converter
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a dynamic elimination circuit for output direct current offset of a voltage reduction type DC-DC converter, which is applicable to constant starting time and based on ripple control.
Background
With the widespread use of portable electronic devices, the market demand for power management integrated circuits is increasing, and the Buck (Buck) DC-DC converter is widely used in the fields of communication, computers, industrial automation, and the like. The traditional step-down DC-DC converter has three control modes, namely current mode, voltage mode and hysteresis control. A Ripple-based Constant On-time Control scheme (Ripple-based Constant On-time Control) belongs to one of the hysteresis mode Control, and is widely applied due to advantages of simple Control, no need of external compensation, excellent load regulation rate and efficiency, and the like.
For a conventional buck converter, there is a certain tradeoff in system performance: the small ripple quantity of the loop superposed on the positive end of the PWM comparator can cause the problems of the reduction of the stability of the loop, the false triggering caused by the output jitter of the PWM comparator and the like. If the ripple quantity is too large, the Q value of the system at one half of the switching frequency is too low, so that the response speed of the system is slow; and the direct current misadjustment amount introduced by the inherent valley value detection mode of the constant starting time is overlarge, which can cause great influence on the system precision on the premise that the buck converter outputs low voltage.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a dynamic elimination circuit aiming at the output offset introduced by the inherent valley detection mode of the constant opening time under the application conditions of different input voltages Vin and output voltages Vout of the buck converter with the constant opening time and based on ripple control, and ensures that the output direct current offset is dynamically eliminated under the conditions of different duty ratios.
The technical scheme of the invention is as follows:
a dynamic eliminating circuit suitable for the output DC offset of a buck converter comprises a ripple generating circuit and a ripple superposing circuit,
the ripple superposition circuit comprises a transconductance amplifier Gm, the positive input end of the transconductance amplifier Gm is used as the first input end of the ripple superposition circuit, the negative input end of the transconductance amplifier Gm is used as the second input end of the ripple superposition circuit, the output end of the ripple superposition circuit outputs a pulse signal, and the pulse signal controls the power tube on the buck converter to be turned on and the power tube to be turned off when the pulse signal is at a high level;
the ripple generating circuit is characterized by comprising a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a first PMOS tube MP1, a second PMOS tube MP2 and a third buffer BUF,
one end of the first resistor R1 is used as the input end of the ripple generating circuit and is input into the voltage at the upper and lower power tube nodes SW of the buck converter, and the other end of the first resistor R1 is grounded after passing through the first capacitor C1;
the second resistor R2 and the third resistor R3 are connected in series, and the series point of the second resistor R2 and the third resistor R3 outputs a triangular wave voltage VF1The other end of the second resistor R2 is connected with the connection point of the first resistor R1 and the first capacitor C1, and the other end of the third resistor R3 is grounded;
the fourth resistor R4 is connected in series with the second capacitor C2, the other end of the fourth resistor R4 is connected with the series point of the second resistor R2 and the third resistor R3, and the other end of the second capacitor C2 is grounded;
the fifth resistor R5 is connected in series with the third capacitor C3, the series point of the fifth resistor R5 is connected with the positive input end of the third buffer BUF, the other end of the fifth resistor R5 is connected with the series point of the fourth resistor R4 and the second capacitor C2, and the other end of the third capacitor C3 is grounded;
the negative input end of the third buffer BUF is connected with the source electrode of the first NMOS transistor MN1, grounded after passing through a sixth resistor R6, and the output end of the third buffer BUF is connected with the grid electrode of the first NMOS transistor MN 1;
the sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are interconnected and connected to a power supply voltage VCCThe grid electrodes of the PMOS transistor and the NMOS transistor are interconnected and connected with the drain electrodes of the first PMOS transistor MP1 and the first NMOS transistor MN 1;
the grid electrode of the second NMOS tube MN2 is connected with a control signal with the inverse phase of the signal at the node SW of the upper power tube and the lower power tube of the buck converter, the drain electrode of the second NMOS tube MN2 is connected with the drain electrode of the third NMOS tube MN3, and the source electrode of the second NMOS tube MN2 is grounded;
the grid electrode of the third NMOS transistor MN3 is connected with a control signal which is in phase with signals at the node SW of the upper power tube and the lower power tube of the buck converter, and the source electrode of the third NMOS transistor MN3 is grounded through the parallel connection structure of the fifth capacitor C5 and the seventh resistor R7;
the eighth resistor R8 is connected in series with the fourth capacitor C4, the other end of the eighth resistor R8 is connected with the source electrode of the third NMOS transistor MN3, and the other end of the fourth capacitor C4 is grounded;
the ninth resistor R9 is connected in series with the sixth capacitor C6, and the series point of the ninth resistor R9 and the sixth capacitor C6 outputs direct current voltage VSW_DCAnd the other end of the ninth resistor R9 is connected with the series point of the eighth resistor R8 and the fourth capacitor C4, and the other end of the sixth capacitor C6 is grounded.
Specifically, the ripple superposition circuit further comprises a first buffer BUF1, a second buffer BUF2, a tenth resistor R10 and a pulse width modulation comparator PWM,
the input end of the first buffer BUF1 inputs the feedback voltage VFBThe output end of the comparator is connected with the output end of the transconductance amplifier Gm and the positive input end of the pulse width modulation comparator PWM after passing through a tenth resistor R10;
the reference voltage V is input to the input end of the second buffer BUF2REFThe output end of the pulse width modulation comparator PWM is connected with the negative input end of the pulse width modulation comparator PWM, and the output end of the pulse width modulation comparator PWM is used as the output end of the ripple wave superposition circuit.
The invention is provided withThe beneficial effects are as follows: the invention can dynamically eliminate the DC detuning quantity of the output end voltage under different application conditions, namely different input voltages Vin and output voltages Vout, and adds duty ratio information in the ripple wave generating circuit to ensure that the feedback voltage V is proportional to the output voltage VoutFBAnd a preset reference voltage VREFThe accuracy of the output voltage Vout of the converter is increased, and the contradiction between the system stability and the accuracy of a valley detection mode of the traditional ripple control is overcome; the on-chip ripple superposition circuit adopted by the invention directly samples the upper power tube S1And a lower power tube S2The voltage at the connection node SW is used for simulating the generation of a ripple wave which is in the same phase with the inductive current and is superposed on the feedback voltage VFBIn the above, the normal inversion of the PWM comparator is controlled to enhance the system stability and avoid the output capacitor's equivalent series resistance RCToo small results in a resonance problem due to phase lag of the output voltage Vout; the fifth capacitor C5 filters the glitch of the upper wave signal of the seventh resistor R7 so that the average voltage obtained by the post-stage filtering is more accurate; meanwhile, the invention also reserves the advantages of simple control, no need of external compensation, good electromagnetic interference (EMI) performance, better load regulation rate, light load efficiency and the like of the traditional constant conduction time control mode based on ripple waves, and optimizes the system performance of the buck converter.
Drawings
Fig. 1 is a schematic diagram of a loop control principle of a buck converter based on ripple control, which is applicable to the present invention.
Fig. 2 is a schematic diagram of a ripple generation circuit of a dynamic cancellation circuit for dc offset output of a buck converter according to the present invention.
Fig. 3 is a schematic diagram of a ripple superposition circuit and a dynamic cancellation circuit for output dc offset of a buck converter according to the present invention.
Fig. 4 is a schematic diagram of output dc offset dynamic cancellation.
Detailed Description
The technical solution of the present invention will be described in detail below with reference to the accompanying drawings:
according to the dynamic elimination circuit suitable for the output direct current offset of the buck converter, the duty ratio information is added into a traditional direct current filter (DC value extra), so that the output direct current offset voltage can be dynamically eliminated under different application conditions of input voltage Vin and output voltage Vout and different duty ratios, and the output precision of the buck converter is improved; meanwhile, the size of the ripple quantity is ensured, and the stability of the system is not influenced.
FIG. 1 is a schematic diagram of a ripple control-based step-down converter, in which a circuit frame is composed of an input voltage Vin, an inductor L, and an upper power transistor S1Lower power tube S2Output capacitor Co and equivalent series resistor R thereofCoAnd an output load Ro, wherein the upper and lower power tubes S1And S2The output voltage Vout generates a feedback voltage V via a feedback coefficient βFBWith a reference voltage VREFInputting the two into a Pulse Width Modulator (PWM) together for comparison and finally controlling an upper power tube S and a lower power tube S through a Logic module Logic1And S2The switch of (2). Upper power tube S1Power tube S under the switch2The time of turn-off is Ton, and is constant; upper power tube S1Turn-off lower power tube S2The time of opening is Toff, and the signal for marking the end is the output signal of the PWM comparatorFBLower than a set reference voltage value VREFIs generated. The duty cycle D is the proportion of the total switching period (Ton + Toff) occupied by Ton. Due to the feedback voltage VFBAfter being fed into a pulse width modulation comparator PWM and a reference voltage VREFBefore comparison, ripple voltage with the same frequency and phase as the inductor current is superposed, so that the first resistor R1, the first capacitor C1, the second resistor R2 and the third resistor R2The resistor R3 is used for generating a triangular wave voltage V with the same frequency and phase as the inductive currentF1The difference between the DC value and the DC value is generated by adding duty ratio information to the DC value after passing through a DC filterFBThe required ripple voltage is superimposed.
The on-chip ripple superposition circuit adopted by the invention directly samples the upper power tube S1And a lower power tube S2The voltage at the connection node SW is used for simulating the generation of a ripple wave which is in the same phase with the inductive current and is superposed on the feedback voltage VFBIn the above, the normal inversion of the PWM comparator is controlled to enhance the system stability and avoid the output capacitor's equivalent series resistance RCoToo small results in an output voltage VOUTResonance problems due to phase lag; and meanwhile, duty ratio information is added to ensure that output direct current offset can be dynamically eliminated under different applications, and the precision of the output voltage of the converter is increased.
As shown in fig. 2, the ripple generating circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a first PMOS tube MP1, a second PMOS tube MP2, and a third buffer BUF, wherein one end of the first resistor R1 is used as an input end of the ripple generating circuit and is input to step down a voltage at an upper power tube SW node of the converter, and the other end of the first resistor R6754 is grounded through a first capacitor C1; the second resistor R2 and the third resistor R3 are connected in series, and the series point of the second resistor R2 and the third resistor R3 outputs a triangular wave voltage VF1The other end of the second resistor R2 is connected with the connection point of the first resistor R1 and the first capacitor C1, and the other end of the third resistor R3 is grounded; the fourth resistor R4 is connected in series with the second capacitor C2, the other end of the fourth resistor R4 is connected with the series point of the second resistor R2 and the third resistor R3, and the other end of the second capacitor C2 is grounded; a fifth resistor R5 connected in series with the third capacitor C3, the series point of the fifth resistor R5 being connected to the positive input terminal of the third buffer BUF, the other end of the fifth resistor R5 being connected to the fourth resistor R4 and the second capacitor C3The serial point of the capacitor C2, and the other end of the third capacitor C3 is grounded; the negative input end of the third buffer BUF is connected with the source electrode of the first NMOS transistor MN1, grounded after passing through a sixth resistor R6, and the output end of the third buffer BUF is connected with the grid electrode of the first NMOS transistor MN 1; the sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are interconnected and connected to a power supply voltage VCCThe grid electrodes of the PMOS transistor and the NMOS transistor are interconnected and connected with the drain electrodes of the first PMOS transistor MP1 and the first NMOS transistor MN 1; the grid electrode of the second NMOS tube MN2 is connected with a control signal with the inverse phase of the signal at the node SW of the upper power tube and the lower power tube of the buck converter, the drain electrode of the second NMOS tube MN2 is connected with the drain electrode of the third NMOS tube MN3, and the source electrode of the second NMOS tube MN2 is grounded; the grid electrode of the third NMOS transistor MN3 is connected with a control signal which is in phase with signals at the node SW of the upper power tube and the lower power tube of the buck converter, and the source electrode of the third NMOS transistor MN3 is grounded through the parallel connection structure of the fifth capacitor C5 and the seventh resistor R7; the eighth resistor R8 is connected in series with the fourth capacitor C4, the other end of the eighth resistor R8 is connected with the source electrode of the third NMOS transistor MN3, and the other end of the fourth capacitor C4 is grounded; the ninth resistor R9 is connected in series with the sixth capacitor C6, and the series point of the ninth resistor R9 and the sixth capacitor C6 outputs direct current voltage VSW_DCAnd the other end of the ninth resistor R9 is connected with the series point of the eighth resistor R8 and the fourth capacitor C4, and the other end of the sixth capacitor C6 is grounded.
As shown in fig. 3, the ripple superposition circuit includes a transconductance amplifier Gm, a first buffer BUF1, a second buffer BUF2, a tenth resistor R10, and a pulse width modulation comparator PWM, a positive input end of the transconductance amplifier Gm is used as a first input end of the ripple superposition circuit, a negative input end of the transconductance amplifier Gm is used as a second input end of the ripple superposition circuit, an output end of the ripple superposition circuit outputs a pulse signal, and when the pulse signal is at a high level, the power tube on the buck converter is controlled to be turned on and the power tube is controlled to be turned off; the input end of the first buffer BUF1 inputs the feedback voltage VFBThe output end of the comparator is connected with the output end of the transconductance amplifier Gm and the positive input end of the pulse width modulation comparator PWM after passing through a tenth resistor R10; the reference voltage V is input to the input end of the second buffer BUF2REFThe output end of the pulse width modulation comparator PWM is connected with the negative input end of the pulse width modulation comparator PWM, and the output end of the pulse width modulation comparator PWM is used as the output end of the ripple wave superposition circuit.
The specific working process of the ripple superposition to control the PWM output inversion of the PWM comparator is as follows:
as shown in fig. 2, the input terminal of the ripple generating circuit is the voltage at the node SW of the upper and lower power tubes of the buck converter, and the input terminal is filtered into a triangular signal, i.e. a triangular voltage V, through an RC network composed of a first resistor R1, a first capacitor C1, a second resistor R2 and a third resistor R3F1Here, the second resistor R2 and the third resistor R3 function to adjust the triangular wave voltage VF1Is measured to fit the common mode input range of the transconductance amplifier Gm of the subsequent stage. For a triangular wave voltage VF1The ripple quantity is as follows:
the average value is:
triangular wave voltage VF1The average value of the two-stage filter network consisting of the fourth resistor R4, the second capacitor C2, the fifth resistor R5 and the third capacitor C3 is obtained after the two-stage filter network is connected, and the voltage at the two ends of the sixth resistor R6 is clamped to the triangular wave voltage V through a third buffer BUFF1Is measured. Therefore, the current through the sixth resistor R6 is:
the width-length ratio of a current mirror formed by the first PMOS tube MP1 and the second PMOS tube MP2 is 1:1, the resistance value of the seventh resistor R7 is equal to the resistance value of the sixth resistor R6, and the grids of the second NMOS tube MN2 and the third NMOS tube MN3 are respectively connected with control signals with the same frequency and phase at the nodes SW of the upper power tube and the lower power tube, so that the third NMOS tube MN3 is switched on during Ton, and the second NMOS tube MN2 is switched off; and during Toff the secondThe NMOS transistor MN2 is turned on, and the third NMOS transistor MN3 is turned off. Therefore, the voltage drop across the seventh resistor R7 during Ton is a triangular wave voltage VF1Average value of (2)And the voltage drop across the seventh resistor R7 during Toff is 0. As shown in the dashed box of FIG. 2, this part of the circuit realizes the voltage V of the triangular waveF1The duty ratio information is added into the direct current information for dynamically eliminating the direct current offset output by the later stage. Therefore, the seventh resistor R7 is a square wave signal with an average value:
where D is the duty cycle. The function of the fifth capacitor C5 is to filter the glitch of the square wave signal at the seventh resistor R7 to make the average voltage obtained by the subsequent filtering more accurate, but it is too large to introduce a large time constant, which is not favorable for the formation of square wave. In general, the time constant of the seventh resistor R7 and the fifth capacitor C5 should be less than 0.1 times the switching period.
The square wave signal at the two ends of the seventh resistor R7 passes through a filter network with a large time constant, which is composed of the eighth resistor R8, the fourth capacitor C4, the ninth resistor R9 and the sixth capacitor C6, and then the potential of the average value is obtained, that is:
then the triangular wave voltage V obtained by the ripple generating circuit is usedF1And a DC voltage VSW_DCInput to a transconductance amplifier of the later stage to generate ripple current I1Said DC voltage VSW_DCContains duty cycle information as shown in fig. 3. Let the equivalent transconductance of the transconductance amplifier be Gm, VF1And VSW_DCRespectively input to positive and negative input terminals, a triangular wave voltage VF1Has an average value ofSo that the output current I of the transconductance amplifier Gm1This can be obtained from the following equation:
wherein,here IrippleThe current contains ripple information and has the same frequency and phase with the inductive current, and the direct current component of the current is zero; and the delta I is an information direct current containing a duty ratio D and is used for dynamically eliminating output voltage offset.
As shown in fig. 4, the current I after passing through the transconductance amplifier Gm1Flows through the tenth resistor R10 to generate the required ripple voltage and the feedback voltage V which is proportional to the output voltage Vout of the buck converter and sampled at the input end of the first buffer BUF1FBSuperimposed as the positive input V of the PWM comparator1Namely:
V1＝VFB+R10·I1
＝VFB+R10·(Iripple+ΔI)
and the negative input terminal V of the PWM of the pulse width modulation comparator2Is a reference voltage V passing through a second buffer BUF2REF. Namely:
V2＝VREF
V1and V2Respectively as the positive and negative input ends of the PWM comparator for comparison and difference, the difference is:
V1-V2＝VFB+R10·(Iripple+ΔI)-VREF
＝(VFB+R10·Iripple)-(VREF-R10·ΔI)
another feedback voltage VFBThe ripple voltage superposed on the upper part is Vripple＝R10·IripplePeak to peak voltage of Vripple(pp)(ii) a And a reference voltage VREFHas a translation amount of Δ V ═ R10Δ I, as marked by the arrow in FIG. 4. Due to the inherent valley detection mode of the constant on-time control method, the PWM comparator needs to generate a pulse signal for turning on the upper power transistor S1 and turning off the lower power transistor S2 by PWM inversion, which includes the feedback voltage VFBV of information1The signal falls to V at its valley2Are equal in value as shown in fig. 4. Ripple current I1Has a peak-to-peak value of Iripple(pp)Then V is1Touching V at valley2Time current I1Has a ripple amount ofNamely:
the DC offset on the output voltage Vout output from the output terminal is eliminated, so that the feedback voltage V isFBAnd a reference voltage VREFOf the same size, i.e. VFB＝VREF. Combining the above formula of the turning condition, there must be:
due to the fact that
And is
The calculation before the substitution can obtain the left side and the right side of the above formula as follows:
it can be seen that the two formulas both contain duty ratio information to offset, and ensure that the output voltage dc offset can be dynamically eliminated under the application conditions of different input voltages Vin and output voltages Vout (i.e., different duty ratios D), so that the invention is applicable in a wide range. The two equations are equal, that is:
2R1·C1·fsw·(R2+R3)＝R1+R2+R3
for a Buck converter for constant frequency applications (fsw constant, e.g., 700kHz), the above equation can be satisfied by adjusting the resistance of the second resistor R2 and the third resistor R3. At the same time, V is derived from the previous derivationF1The amount of ripple of (3) is inversely proportional to the values of the first resistor R1 and the first capacitor C1, so that the feedback voltage V can be adjusted and superposed by properly setting the first resistor R1 and the first capacitor C1 during designFBThe size of the upper ripple is usually not less than 30mV, so as to ensure the stability of the system.
The invention can dynamically eliminate the DC detuning quantity of the output end voltage under different application conditions, namely different input voltages Vin and output voltages Vout, so that the feedback voltage V proportional to the output VoutFBAnd a preset reference voltage VREFAnd the contradiction between system stability and accuracy of a valley detection mode of the traditional ripple control is overcome. Meanwhile, the invention also reserves the traditional Ripple-based constant on-time control modeConstant On-timeControl), has the advantages of simple control, no need of external compensation, good EMI performance, better load regulation rate, light load efficiency and the like, and well optimizes the system performance of the Buck converter.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims (2)

1. A dynamic eliminating circuit suitable for the output DC offset of a buck converter comprises a ripple generating circuit and a ripple superposing circuit,
the ripple superposition circuit comprises a transconductance amplifier (Gm), the positive input end of the transconductance amplifier (Gm) is used as the first input end of the ripple superposition circuit, the negative input end of the transconductance amplifier (Gm) is used as the second input end of the ripple superposition circuit, the output end of the ripple superposition circuit outputs a pulse signal, and the pulse signal controls the power tube on the buck converter to be turned on and the power tube to be turned off when the pulse signal is at a high level;
the ripple generation circuit is characterized by comprising a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6), a seventh resistor (R7), an eighth resistor (R8), a ninth resistor (R9), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), a fifth capacitor (C5), a sixth capacitor (C6), a first NMOS tube (MN1), a second NMOS tube (MN2), a third NMOS tube (MN3), a first PMOS tube (MP1), a second PMOS tube (MP2) and a third Buffer (BUF),
one end of a first resistor (R1) is used as the input end of the ripple generating circuit and is input into the voltage at the upper and lower power tube nodes (SW) of the buck converter, and the other end of the first resistor is grounded after passing through a first capacitor (C1);
the second resistor (R2) and the third resistor (R3) are connected in series, and the series point of the second resistor (R2) and the third resistor (R3) outputs a triangular wave voltage (V)F1) The first input end of the ripple superposition circuit is connected, the other end of the second resistor (R2) is connected with the connection point of the first resistor (R1) and the first capacitor (C1), and the other end of the third resistor (R3) is grounded;
the fourth resistor (R4) is connected with the second capacitor (C2) in series, the other end of the fourth resistor (R4) is connected with the series point of the second resistor (R2) and the third resistor (R3), and the other end of the second capacitor (C2) is grounded;
the fifth resistor (R5) and the third capacitor (C3) are connected in series, the series point of the fifth resistor (R5) is connected with the positive input end of the third Buffer (BUF), the other end of the fifth resistor (R5) is connected with the series point of the fourth resistor (R4) and the second capacitor (C2), and the other end of the third capacitor (C3) is grounded;
the negative input end of the third Buffer (BUF) is connected with the source electrode of the first NMOS tube (MN1), grounded after passing through a sixth resistor (R6), and the output end of the third Buffer (BUF) is connected with the grid electrode of the first NMOS tube (MN 1);
the sources of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are interconnected and connected with a power supply voltage (V)CC) The grid electrode of the NMOS transistor is interconnected and connected with the drain electrode of the first PMOS transistor (MP1) and the drain electrode of the first NMOS transistor (MN 1);
the grid electrode of the second NMOS tube (MN2) is connected with a control signal with the inverse phase of the signal at the node (SW) of the upper power tube and the lower power tube of the buck converter, the drain electrode of the second NMOS tube (MP2) and the drain electrode of the third NMOS tube (MN3) are connected, and the source electrode of the second NMOS tube is grounded;
the grid electrode of the third NMOS tube (MN3) is connected with a control signal which is in phase with signals at the nodes (SW) of the upper power tube and the lower power tube of the buck converter, and the source electrode of the third NMOS tube is grounded after passing through the parallel connection structure of the fifth capacitor (C5) and the seventh resistor (R7);
the eighth resistor (R8) is connected with the fourth capacitor (C4) in series, the other end of the eighth resistor (R8) is connected with the source electrode of the third NMOS tube (MN3), and the other end of the fourth capacitor (C4) is grounded;
the ninth resistor (R9) and the sixth capacitor (C6) are connected in series, and the series point of the ninth resistor and the sixth capacitor outputs direct current voltage (V)SW_DC) And the other end of the ninth resistor (R9) is connected with the series point of the eighth resistor (R8) and the fourth capacitor (C4), and the other end of the sixth capacitor (C6) is grounded.
2. The dynamic cancellation circuit for DC offset of buck converter output according to claim 1, wherein the ripple superposition circuit further comprises a first buffer (BUF1), a second buffer (BUF2), a tenth resistor (R10) and a pulse width modulation comparator (PWM),
the input end of the first buffer (BUF1) inputs the feedback voltage (V)FB) The output end of the comparator is connected with the output end of the transconductance amplifier (Gm) and the positive input end of the pulse width modulation comparator (PWM) after passing through a tenth resistor (R10);
the input terminal of the second buffer (BUF2) inputs the reference voltage (V)REF) The output end of the ripple superposition circuit is connected with the negative input end of a pulse width modulation comparator (PWM), and the output end of the pulse width modulation comparator (PWM) is used as the output end of the ripple superposition circuit.
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