CN106783992A - A kind of two-way SCR structure of NMOS low pressure triggering - Google Patents
A kind of two-way SCR structure of NMOS low pressure triggering Download PDFInfo
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- CN106783992A CN106783992A CN201611077368.3A CN201611077368A CN106783992A CN 106783992 A CN106783992 A CN 106783992A CN 201611077368 A CN201611077368 A CN 201611077368A CN 106783992 A CN106783992 A CN 106783992A
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- traps
- injection regions
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- pwell
- way scr
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- 238000002347 injection Methods 0.000 claims abstract description 69
- 239000007924 injection Substances 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 101100365087 Arabidopsis thaliana SCRA gene Proteins 0.000 claims description 10
- 101000668165 Homo sapiens RNA-binding motif, single-stranded-interacting protein 1 Proteins 0.000 claims description 10
- 102100039692 RNA-binding motif, single-stranded-interacting protein 1 Human genes 0.000 claims description 10
- 101150105073 SCR1 gene Proteins 0.000 claims description 10
- 101100134054 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) NTG1 gene Proteins 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 230000001960 triggered effect Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000004224 protection Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 210000001367 artery Anatomy 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A kind of two-way SCR structure of NMOS low pressure triggering, includes P type substrate, and its structure is：PWell traps, NWell traps are formed in P type substrate, wherein PWell traps are located at centre position, and PWell traps both sides form NWell traps；A N+ injection regions and a P+ injection regions are formed in the NWell traps of side, the 2nd N+ injection regions and the 2nd P+ injection regions are formed in the NWell traps of opposite side；The 3rd N+ injection regions or the 4th N+ injection regions are formed respectively with the NWell traps intersection of both sides in middle PWell traps.The present invention in the case where additional devices are not used, can realize the function of two-way SCR, solve the problems, such as big chip area present in prior art, and can realize the function of two-way SCR, and working stability, performance is high, easy to use, has saved chip area.
Description
Technical field
The invention is related to a kind of SCR device, more particularly to the two-way SCR structure that a kind of NMOS low pressure is triggered.
Background technology
Controllable silicon（Silicon controlled rectifier – SCR）Also IGCT is, it is wide in power device
General application, because it can switch between high-impedance state and low resistance state, can be used as power switch, but it is also simultaneously extremely have
The ESD protection devices of effect, because its maintenance voltage is very low, it is possible to ESD electric currents very high are born, therefore, SCR is natural
With ESD robustness high.Compared with other ESD protection devices, the unit area ESD protective capabilities of SCR devices
It is most strong.General SCR device is one direction ESD protection devices, and the ESD in another direction is protected by parasitic diode or simultaneously
Join a diode to complete.The ESD protections in another direction are carried out using extra diode, domain face can be increased
Product.But in some circuits for having negative voltage, if IO voltages are less than -0.7V, GND voltage is 0V, is carried out using diode
When opposite direction is protected, diode will be turned in circuit normal work, produce electric leakage, it is necessary to carry out using two-way SCR structure
Protection.
The content of the invention
In order to solve the above-mentioned technical problem, the invention provides a kind of two-way SCR structure of NMOS low pressure triggering, bag
P type substrate is included, PWell trap NWell traps have been formed in P type substrate, wherein PWell traps have been located at centre position, PWell traps two
Side forms NWell traps；A N+ injection regions and a P+ injection regions are formed in the NWell traps of side, in the NWell traps of opposite side
Form the 2nd N+ injection regions and the 2nd P+ injection regions；The is formed respectively in middle PWell traps and the NWell traps intersection of both sides
Three N+ injection regions or the 4th N+ injection regions.By above structure, the present invention can be realized in the case where additional devices are not used
The function of two-way SCR, solves the problems, such as big chip area present in prior art.
To achieve these goals, the technical scheme of the invention use is：A kind of two-way SCR of NMOS low pressure triggering
Structure, includes P type substrate, it is characterised in that：PWell trap NWell traps are formed in P type substrate, during wherein PWell traps are located at
Between position, PWell traps both sides formed NWell traps；A N+ injection regions and a P+ injection regions are formed in the NWell traps of side,
The 2nd N+ injection regions and the 2nd P+ injection regions are formed in the NWell traps of opposite side；In the NWell of middle PWell traps with both sides
Trap intersection forms the 3rd N+ injection regions or the 4th N+ injection regions respectively.
The gate oxide polysilicon gate of floating is formed between the 3rd described N+ injection regions and the 4th N+ injection regions.
A described N+ injection regions and a P+ injection regions constitute t1 port, the 2nd N+ injection regions and the 2nd P+ injection regions
Constitute T2 ports.
From T1 to T2, positive ESD current drains path SCR2 is, by a P+ injection regions sequentially pass through NWell traps,
PWell traps, NWell traps, finally to the 2nd N+ injection regions；From T2 to T1, reverse ESD current drains path SCR1 is, by the 2nd P
+ injection region sequentially passes through NWell traps, PWell traps, NWell traps, finally to a N+ injection regions.
Described SCR1 is consistent with SCR2 path-lengths, and is the structure of symmetry.
The beneficial effect of the invention is：The invention provides a kind of two-way SCR knots of NMOS low pressure triggering
Structure, includes P type substrate, and PWell trap NWell traps are formed in P type substrate, and wherein PWell traps are located at centre position, PWell
Trap both sides form NWell traps；A N+ injection regions and a P+ injection regions, the NWell of opposite side are formed in the NWell traps of side
The 2nd N+ injection regions and the 2nd P+ injection regions are formed in trap；NWell traps intersection in middle PWell traps with both sides distinguishes shape
Into the 3rd N+ injection regions or the 4th N+ injection regions.By above structure, the present invention can in the case where additional devices are not used,
The function of two-way SCR is realized, working stability performance is high, easy to use, and has saved chip area.
Brief description of the drawings
Fig. 1：It is existing unidirectional SCR esd protection structures.
Fig. 2：It is the invention structural representation.
Specific embodiment
A kind of two-way SCR structure of NMOS low pressure triggering, includes P type substrate 1, and its structure is：The shape in P type substrate 1
Into PWell traps 2, NWell traps 3, wherein PWell traps 2 are located at centre position, and the both sides of PWell traps 2 form NWell traps 3；Side
NWell traps 3 are inner to form a N+ injection regions 4 and a P+ injection regions 5, and the NWell traps 3 of opposite side are inner to form the 2nd N+ injection regions
6 and the 2nd P+ injection region 7；The 3rd N+ injection regions 8 are formed respectively with the intersection of NWell traps 3 of both sides in middle PWell traps 2
Or the 4th N+ injection region 9.
A described N+ injection regions 4 and a P+ injection regions 5 constitute t1 port, and the 2nd N+ injection regions 6 and the 2nd P+ are noted
Enter area 7 and constitute T2 ports.
From T1 to T2, positive ESD current drains path SCR2 is, by a P+ injection regions 5 sequentially pass through NWell traps 3,
PWell traps 2, NWell traps 3, finally to the 2nd N+ injection regions 6；From T2 to T1, reverse ESD current drains path SCR1 is, by
Two P+ injection regions 7 sequentially pass through NWell traps 3, PWell traps 2, NWell traps 3, finally to a N+ injection regions 4.
First N+ injection regions 4 are arranged on the outside of a P+ injection regions 5, and the 2nd N+ injection regions 6 are arranged on the 2nd P+ injection regions 7
Outside.
Described SCR1 is consistent with SCR2 path-lengths, and consistent passage length ensures that SCR1 as SCR2 characteristics, has
Identical trigger voltage and maintenance voltage, using the structure of symmetry, make ESD current drains evenly, SCR1 and SCR2 paths
It is symmetrical SCR paths.
The gate oxide polysilicon gate 10 of floating is formed between the 3rd described N+ injection regions 8 and the 4th N+ injection regions 9.It is floating
Empty gate oxide polysilicon gate helps to reduce the ESD trigger voltages of SCR1 and SCR2 paths.Such as there is the positive arteries and veins of ESD from T1 to T2
Punching, in the triggering stage, trigger current can trigger middle NMOS conductings, needed for this passage by the raceway groove under polysilicon gate
Trigger voltage is smaller, and the unlatching of SCR2 passages, ESD electric currents of releasing can be triggered when trigger current is sufficiently large.Such as from T2 to T1
There are ESD positive pulses, in the triggering stage, trigger current also can trigger middle NMOS conductings by the raceway groove under polysilicon gate, this
Trigger voltage needed for passage is smaller, and the unlatching of SCR1 passages, ESD electric currents of releasing can be triggered when trigger current is sufficiently large.
Claims (5)
1. a kind of two-way SCR structure of NMOS low pressure triggering, includes P type substrate（1）, it is characterised in that：In P type substrate（1）
Upper formation PWell traps（2）NWell traps（3）, wherein PWell traps（2）It is located at centre position, PWell traps（2）Both sides are formed
NWell traps（3）；The NWell traps of side（3）In formed a N+ injection regions（4）With a P+ injection regions（5）, opposite side
NWell traps（3）In formed the 2nd N+ injection regions（6）With the 2nd P+ injection regions（7）；In middle PWell traps（2）With both sides
NWell traps（3）Intersection forms the 3rd N+ injection regions respectively（8）Or the 4th N+ injection region（9）.
2. a kind of two-way SCR structure of NMOS low pressure triggering according to claim 1, includes P type substrate（1）, it is special
Levy and be：The 3rd described N+ injection regions（8）With the 4th N+ injection regions（9）Between formed floating gate oxide polysilicon gate
（10）.
3. a kind of two-way SCR structure of NMOS low pressure triggering according to claim 1, includes P type substrate（1）, it is special
Levy and be：A described N+ injection regions（4）With a P+ injection regions（5）Constitute t1 port, the 2nd N+ injection regions（6）With second
P+ injection regions（7）Constitute T2 ports.
4. a kind of two-way SCR structure of NMOS low pressure triggering according to claim 3, includes P type substrate（1）, it is special
Levy and be：From T1 to T2, positive ESD current drains path SCR2 is, by a P+ injection regions（5）Sequentially pass through NWell traps
（3）, PWell traps（2）, NWell traps（3）, finally to the 2nd N+ injection regions（6）；From T2 to T1, reverse ESD current drains path
SCR1 is, by the 2nd P+ injection regions（7）Sequentially pass through NWell traps（3）, PWell traps（2）, NWell traps（3）, finally to a N+
Injection region（4）.
5. the two-way SCR structure that a kind of NMOS low pressure is triggered according to claim 4, includes P type substrate（1）, its feature
It is：Described SCR1 is consistent with SCR2 path-lengths, and is the structure of symmetry.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611077368.3A CN106783992A (en) | 2016-11-30 | 2016-11-30 | A kind of two-way SCR structure of NMOS low pressure triggering |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611077368.3A CN106783992A (en) | 2016-11-30 | 2016-11-30 | A kind of two-way SCR structure of NMOS low pressure triggering |
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| Publication Number | Publication Date |
|---|---|
| CN106783992A true CN106783992A (en) | 2017-05-31 |
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ID=58899011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611077368.3A Pending CN106783992A (en) | 2016-11-30 | 2016-11-30 | A kind of two-way SCR structure of NMOS low pressure triggering |
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| Country | Link |
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| CN (1) | CN106783992A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108022912A (en) * | 2018-01-17 | 2018-05-11 | 上海长园维安微电子有限公司 | A kind of two-way SCR semiconductor protection devices of new low trigger voltage |
| CN108987393A (en) * | 2018-09-13 | 2018-12-11 | 扬州江新电子有限公司 | Bi-directional ESD structure for power integrated circuit output LDMOS device protection |
| CN109256378A (en) * | 2018-09-13 | 2019-01-22 | 扬州江新电子有限公司 | High maintenance voltage SCR structure for power integrated circuit output LDMOS device protection |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020056876A1 (en) * | 1998-09-03 | 2002-05-16 | Hans U. Schroeder | Semiconductor device |
| US20050133869A1 (en) * | 2003-12-18 | 2005-06-23 | Ming-Dou Ker | [double-triggered silicon controlling rectifier and electrostatic discharge protection circuit thereof] |
| CN102034858A (en) * | 2010-10-28 | 2011-04-27 | 浙江大学 | Bidirectional triode thyristor for electrostatic discharge protection of radio frequency integrated circuit |
-
2016
- 2016-11-30 CN CN201611077368.3A patent/CN106783992A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020056876A1 (en) * | 1998-09-03 | 2002-05-16 | Hans U. Schroeder | Semiconductor device |
| US20050133869A1 (en) * | 2003-12-18 | 2005-06-23 | Ming-Dou Ker | [double-triggered silicon controlling rectifier and electrostatic discharge protection circuit thereof] |
| CN102034858A (en) * | 2010-10-28 | 2011-04-27 | 浙江大学 | Bidirectional triode thyristor for electrostatic discharge protection of radio frequency integrated circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108022912A (en) * | 2018-01-17 | 2018-05-11 | 上海长园维安微电子有限公司 | A kind of two-way SCR semiconductor protection devices of new low trigger voltage |
| CN108987393A (en) * | 2018-09-13 | 2018-12-11 | 扬州江新电子有限公司 | Bi-directional ESD structure for power integrated circuit output LDMOS device protection |
| CN109256378A (en) * | 2018-09-13 | 2019-01-22 | 扬州江新电子有限公司 | High maintenance voltage SCR structure for power integrated circuit output LDMOS device protection |
| CN108987393B (en) * | 2018-09-13 | 2024-03-15 | 扬州江新电子有限公司 | Bidirectional ESD structure for protecting power integrated circuit output LDMOS device |
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Application publication date: 20170531 |
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| RJ01 | Rejection of invention patent application after publication |