CN106783532A - A kind of preparation method of low-temperature polysilicon film, thin film transistor (TFT), array base palte and liquid crystal display panel - Google Patents
A kind of preparation method of low-temperature polysilicon film, thin film transistor (TFT), array base palte and liquid crystal display panel Download PDFInfo
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- CN106783532A CN106783532A CN201611033946.3A CN201611033946A CN106783532A CN 106783532 A CN106783532 A CN 106783532A CN 201611033946 A CN201611033946 A CN 201611033946A CN 106783532 A CN106783532 A CN 106783532A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 63
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 57
- 239000010408 film Substances 0.000 title claims abstract description 32
- 238000002360 preparation method Methods 0.000 title claims abstract description 26
- 239000010409 thin film Substances 0.000 title claims abstract description 18
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 14
- 239000010410 layer Substances 0.000 claims abstract description 90
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims abstract description 59
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005224 laser annealing Methods 0.000 claims abstract description 17
- 239000012528 membrane Substances 0.000 claims abstract description 15
- 238000000926 separation method Methods 0.000 claims description 18
- 239000002346 layers by function Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 238000002425 crystallisation Methods 0.000 abstract description 5
- 230000008025 crystallization Effects 0.000 abstract description 5
- 229910021419 crystalline silicon Inorganic materials 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
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- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a kind of preparation method of low-temperature polysilicon film, methods described includes：Metal level is formed on substrate；Development is exposed to the metal level using the first light shield, metal pattern is obtained, the metal pattern includes the silicon island area of hollow out and positioned at silicon island area left and right sides or the metal area of upper and lower sides；Amorphous silicon layer is formed on the metal pattern；High-temperature process and laser annealing are carried out to the amorphous silicon layer, and then the amorphous silicon layer is formed polysilicon membrane.The present invention also provides a kind of thin film transistor (TFT), array base palte and liquid crystal display panel.In the preparation method of the low-temperature polysilicon film that the present invention is provided, by forming metal pattern on substrate, so that metal area forms temperature difference with silicon island area, when amorphous silicon layer is recrystallized, the starting point of grain crystalline is formed in low-temperature space, to temperature silicon island area side crystallization higher, uniform, larger polysilicon grain, the low-temperature polysilicon film with electron mobility very high is formed.
Description
Technical field
It is more particularly to a kind of preparation method of low-temperature polysilicon film, thin the present invention relates to technical field of display panel
Film transistor, array base palte and liquid crystal display panel.
Background technology
With the development of flat panel display technology, with high-resolution, the demand of the liquid crystal display panel of low energy consumption increasingly
Greatly.The electron mobility of non-crystalline silicon is relatively low, and low temperature polycrystalline silicon can make at low temperature, and low temperature polycrystalline silicon electron transfer
Rate is higher than the electron mobility of non-crystalline silicon 20-100 times.Using in the case of low temperature polycrystalline silicon, can by thin film transistor (TFT) with
And pixel accomplishes smaller, to reach high-resolution requirement.Additionally, the semiconductor devices that low temperature polycrystalline silicon makes causes liquid crystal
Show that device energy expenditure rate is low.Low temperature polycrystalline silicon has the advantages that so many compared with non-crystalline silicon so that low temperature polycrystalline silicon has been obtained extensively
Study generally and apply.
The content of the invention
The present invention solves the technical problem of a kind of preparation method of low-temperature polysilicon film is provided, crystalline substance can be obtained
Uniform, the larger polysilicon of grain.
To solve above-mentioned technical proposal, a kind of technical scheme that the present invention is provided is：A kind of low-temperature polysilicon film is provided
Preparation method, methods described includes：
Metal level is formed on substrate；
Development is exposed to the metal level using the first light shield, metal pattern is obtained, the metal pattern includes engraving
Empty silicon island area and positioned at silicon island area left and right sides or the metal area of upper and lower sides；
Amorphous silicon layer is formed on the metal pattern；
High-temperature process and laser annealing are carried out to the amorphous silicon layer, and then it is thin the amorphous silicon layer is formed polysilicon
Film.
Wherein, it is described that high-temperature process and laser annealing are carried out to the amorphous silicon layer, and then form the amorphous silicon layer
After the step of polysilicon membrane, also include：
Development is exposed to the polysilicon membrane using first light shield, and then removes the metal area.
Wherein, it is described on substrate formed metal level the step of, including：
The first separation layer, metal level are sequentially formed on substrate.
Wherein, the thickness range of first separation layer is 3000A-1um.
Wherein, it is described on the metal pattern formed amorphous silicon layer the step of before, including：
The second separation layer is formed on the metal pattern；
The first auxiliary functional layers are formed on second separation layer；
Amorphous silicon layer is formed in first auxiliary functional layers.
Wherein, it is described that high-temperature process and laser annealing are carried out to the amorphous silicon layer, and then form the amorphous silicon layer
Before the step of polysilicon membrane, including：
The second auxiliary functional layers are formed on the amorphous silicon layer；
It is described that high-temperature process and laser annealing are carried out to the amorphous silicon layer, and then the amorphous silicon layer is formed polysilicon
The step of film, including：
The described pair of amorphous silicon layer for being formed with the silicon oxide layer carries out high-temperature process and laser annealing, and then makes institute
State amorphous silicon layer and form polysilicon membrane.
Wherein, the thickness range of the amorphous silicon layer is 450A-600A.
To solve above-mentioned technical proposal, another technical scheme that the present invention is provided is：A kind of thin film transistor (TFT), institute are provided
State the low-temperature polysilicon film that thin film transistor (TFT) is obtained including preparation method as described above.
To solve above-mentioned technical proposal, another technical scheme that the present invention is provided is：A kind of array base palte is provided, it is described
Array base palte includes thin film transistor (TFT) as described above.
To solve above-mentioned technical proposal, another technical scheme that the present invention is provided is：A kind of liquid crystal display panel is provided,
The liquid crystal display panel includes array base palte as described above.
The beneficial effects of the invention are as follows：The situation of prior art is different from, the low-temperature polysilicon film that the present invention is provided
In preparation method, by forming metal pattern on substrate so that metal area forms temperature difference with silicon island area, amorphous silicon layer is tied again
When brilliant, the starting point of grain crystalline is formed in low-temperature space, to temperature silicon island area side crystallization higher, formed uniform, larger
Polysilicon grain, the low-temperature polysilicon film with electron mobility very high.
Brief description of the drawings
The step of Fig. 1 is the preparation method of the low-temperature polysilicon film that the present invention is provided schematic flow sheet；
Fig. 2 be the present invention provide low-temperature polysilicon film preparation method in formed metal level schematic diagram；
Fig. 3 be the present invention provide low-temperature polysilicon film preparation method in formed metal pattern schematic diagram；
Fig. 4 be the present invention provide low-temperature polysilicon film preparation method in formed amorphous silicon layer schematic diagram；
Fig. 5 is the process schematic of the preparation method high temperature treatment of the low-temperature polysilicon film that the present invention is provided；
Fig. 6 is that the structure of the low-temperature polysilicon film of the preparation method formation of the low-temperature polysilicon film that the present invention is provided is shown
It is intended to.
Specific embodiment
The present invention will be described in detail with reference to the accompanying drawings and examples.
Fig. 1 to Fig. 6 is referred to, the present invention provides a kind of preparation method of low-temperature polysilicon film 100, and method includes：
Step S101, refers to Fig. 2, and metal level 20 is formed on the substrate 10.
It is appreciated that metal level 20 is formed on the substrate 10 by way of physical vapour deposition (PVD).
Wherein, the step of forming metal level 20 on the substrate 10, including：
The first separation layer 30, metal level 20 are sequentially formed on the substrate 10.
First separation layer 30 is used to prevent the ionic impurity on substrate 10 from spreading, so as to influence the work of film layer being subsequently formed
Use effect.First separation layer 30 can be the composite bed of silicon nitride layer, silicon dioxide layer or silicon nitride layer and silicon dioxide layer.When
When one separation layer 30 is the composite bed of silicon nitride layer and silicon dioxide layer, silicon nitride layer and the directly contact of substrate 10, so as to reach
More preferably isolation effect.
The thickness range of the first separation layer 30 is 3000A-1um.
It is appreciated that substrate 10 can be but be not limited to flexible base board 10 or glass substrate 10.
It is appreciated that it is molybdenum or titanium that the material of metal level 20 is selected from.
Step S102, refers to Fig. 3, and development is exposed to metal level 20 using the first light shield, obtains metal pattern 21,
Metal pattern 21 includes the silicon island area 23 of hollow out and the metal area 25 positioned at the left and right sides of silicon island area 23 or upper and lower sides.
Wherein, the step of development being exposed to metal level 20 using the first light shield, specially：Use polysilicon road light shield
And negativity photoresistance, silicon island area 23 and metal area 25 are depicted, then silicon island area is removed by way of wet etching or dry ecthing
23 corresponding regions, obtain metal pattern 21.
It is appreciated that metal area 25 is disposed on the surface of the first separation layer 30.
Step S103, refers to Fig. 4, and amorphous silicon layer 40 is formed on metal pattern 21.
The thickness range of amorphous silicon layer 40 is 450A-600A, such as 450A, 500A, 550A, 600A etc..
It is appreciated that amorphous silicon layer 40 is formed on metal pattern 21 by way of physical vapour deposition (PVD), and cover silicon
Island area 23 and metal area 25.
It is appreciated that before the step of forming amorphous silicon layer 40 on metal pattern 21, further including：
The second separation layer 50 is formed on metal pattern 21；
The first auxiliary functional layers 60 are formed on the second separation layer 50；
Amorphous silicon layer 40 is formed in the first auxiliary functional layers 60.
Wherein, the first separation layer 30 is made up of silicon nitride material, further to prevent the ionic impurity on substrate 10 from spreading
To amorphous silicon layer 40.The thickness range of the first separation layer 30 is 500-1000A, such as 500A, 750A, 1000A etc..
First auxiliary functional layers 60 are made up of earth silicon material, and polysilicon is formed to aid in non-crystalline silicon to recrystallize.First
The thickness range of auxiliary functional layers 60 is 2000A-3000A, such as 2000A, 2300A, 2600A, 3000A etc..
It is appreciated that the lattice of silica is more similar to the lattice of polysilicon, so as to contribute in subsequent step
Amorphous silicon layer 40 forms low-temperature polysilicon film 100.
Step S104, high-temperature process and laser annealing is carried out to amorphous silicon layer 40, and then amorphous silicon layer 40 is formed low temperature
Polysilicon membrane 100.
It is appreciated that Fig. 4 is referred to, by high-temperature process so that amorphous silicon layer 40 is in molten condition, because near metal area
25 region radiating rate is faster so that the regional temperature is relatively low, and the region radiating away from metal area 25 is relatively slow, temperature compared with
Height, in this way, forming a temperature difference.Polysilicon is crystallized according to low energy in recrystallization to high-energy direction so that non-crystalline silicon
Layer 40 is that starting point is crystallized to temperature field side higher from the relatively low region of temperature, forms low-temperature polysilicon film 100.
It is appreciated that when amorphous silicon layer 40 is recrystallized, the starting point of grain crystalline is formed in the low-temperature space near metal area 25,
To the temperature side crystallization of silicon island area 23 higher, direction is thereby is achieved controllable and with the low-temperature polysilicon of larger polysilicon grain
Silicon thin film.
It is appreciated that carrying out high-temperature process to amorphous silicon layer 40 and laser annealing can be by way of excimer laser irradiation
Carry out.
It is appreciated that carrying out high-temperature process and laser annealing to amorphous silicon layer 40, and then amorphous silicon layer 40 is set to form low temperature
Before the step of polysilicon membrane 100, further include：
The second auxiliary functional layers 70 are formed on amorphous silicon layer 40；
High-temperature process and laser annealing are carried out to amorphous silicon layer 40, and then amorphous silicon layer 40 is formed low-temperature polysilicon film
100 the step of, including：
Amorphous silicon layer 40 to being formed with silicon oxide layer carries out high-temperature process and laser annealing, and then makes the shape of amorphous silicon layer 40
Into low-temperature polysilicon film 100.
It is appreciated that the second auxiliary functional layers 70 are made up of earth silicon material, further to aid in non-crystalline silicon to recrystallize
Form polysilicon.
It is appreciated that the second auxiliary functional layers 70 are formed by ozone Oxidation Treatment.
It is appreciated that before the step of forming the second auxiliary functional layers 70, further including step：
Amorphous silicon layer 40 is processed with hydrofluoric acid, to cause the surface of amorphous silicon layer 40 more smooth.
Fig. 5 is referred to, high-temperature process and laser annealing is carried out to amorphous silicon layer 40, and then amorphous silicon layer 40 is formed low temperature
After the step of polysilicon membrane 100, further include：
Development is exposed to polysilicon membrane using the first light shield, and then removes metal area 25.
Specifically, the silicon island for crystallizing out is protected using non-crystalline silicon road light shield and positivity photoresistance, using dry ecthing or wet etching
The mode of erosion etches away metal area 25, leaves the silicon island of side crystallization.
In the preparation method of the low-temperature polysilicon film 100 that the present invention is provided, by forming metal pattern on the substrate 10
21 so that metal area 25 forms temperature difference with silicon island area 23, when amorphous silicon layer 40 is recrystallized, grain crystalline is formed in low-temperature space
Starting point, to the temperature side crystallization of silicon island area 23 higher, forms uniform, larger polysilicon grain, with electronics very high
The low-temperature polysilicon film 100 of mobility.
The present invention also provides a kind of thin film transistor (TFT), and thin film transistor (TFT) includes the low-temperature polysilicon that preparation method as above is obtained
Silicon thin film.
The crystal grain of the low-temperature polysilicon film in the thin film transistor (TFT) that the present invention is provided is uniform, larger, and with very high
Electron mobility so that transistor has electron mobility and stable electrical property very high.
The present invention also provides a kind of array base palte, and array base palte includes thin film transistor (TFT) as above.
Thin film transistor (TFT) in the array base palte that the present invention is provided has electron mobility and stable electricity very high
Performance, substantially increases the quality of array base palte.
The present invention also provides a kind of liquid crystal display panel, and liquid crystal display panel includes array base palte as above.
The thin film transistor (TFT) that array base palte in the liquid crystal display panel that the present invention is provided is used has electronics very high
The electrical property of mobility and stabilization, so as to substantially increase the use quality and shown effect of liquid crystal display panel.
Embodiments of the present invention are the foregoing is only, the scope of the claims of the invention is not thereby limited, it is every using this
Equivalent structure or equivalent flow conversion that description of the invention and accompanying drawing content are made, or directly or indirectly it is used in other correlations
Technical field, is included within the scope of the present invention.
Claims (10)
1. a kind of preparation method of low-temperature polysilicon film, it is characterised in that methods described includes：
Metal level is formed on substrate；
Development is exposed to the metal level using the first light shield, metal pattern is obtained, the metal pattern includes hollow out
Silicon island area and positioned at silicon island area left and right sides or the metal area of upper and lower sides；
Amorphous silicon layer is formed on the metal pattern；
High-temperature process and laser annealing are carried out to the amorphous silicon layer, and then the amorphous silicon layer is formed polysilicon membrane.
2. preparation method according to claim 1, it is characterised in that it is described the amorphous silicon layer is carried out high-temperature process and
Laser annealing, so the step of the amorphous silicon layer is formed polysilicon membrane after, also include：
Development is exposed to the polysilicon membrane using first light shield, and then removes the metal area.
3. preparation method according to claim 1, it is characterised in that described the step of form metal level on substrate, bag
Include：
The first separation layer, metal level are sequentially formed on substrate.
4. preparation method according to claim 3, it is characterised in that the thickness range of first separation layer is 3000A-
1um。
5. preparation method according to claim 1, it is characterised in that described to form amorphous silicon layer on the metal pattern
The step of before, including：
The second separation layer is formed on the metal pattern；
The first auxiliary functional layers are formed on second separation layer；
Amorphous silicon layer is formed in first auxiliary functional layers.
6. preparation method according to claim 1, it is characterised in that it is described the amorphous silicon layer is carried out high-temperature process and
Laser annealing, so the step of the amorphous silicon layer is formed polysilicon membrane before, including：
The second auxiliary functional layers are formed on the amorphous silicon layer；
It is described that high-temperature process and laser annealing are carried out to the amorphous silicon layer, and then the amorphous silicon layer is formed polysilicon membrane
The step of, including：
The described pair of amorphous silicon layer for being formed with the silicon oxide layer carries out high-temperature process and laser annealing, and then makes described non-
Crystal silicon layer forms polysilicon membrane.
7. preparation method according to claim 1, it is characterised in that the thickness range of the amorphous silicon layer is 450A-
600A。
8. a kind of thin film transistor (TFT), it is characterised in that the thin film transistor (TFT) is included by described in claim any one of 1-7
The low-temperature polysilicon film that preparation method is obtained.
9. a kind of array base palte, it is characterised in that the array base palte includes the thin film transistor (TFT) described in claim 8.
10. a kind of liquid crystal display panel, it is characterised in that the liquid crystal display panel includes the array base described in claim 9
Plate.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108172543A (en) * | 2018-01-12 | 2018-06-15 | 武汉华星光电半导体显示技术有限公司 | The stripping means and underlay substrate of a kind of flexible substrates |
| CN112397379A (en) * | 2020-11-16 | 2021-02-23 | 浙江大学 | Laser local annealing amorphous polycrystalline composite photoelectron integration method |
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| US20140091410A1 (en) * | 2008-08-14 | 2014-04-03 | Board Of Regents, The University Of Texas System | Method and Apparatus for Fabricating Piezoresistive Polysilicon by Low-Temperature Metal Induced Crystallization |
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| CN1700429A (en) * | 2004-05-17 | 2005-11-23 | 统宝光电股份有限公司 | Polycrystalline silicon annealing arrangement applied to high-performance thin film transistor and method thereof |
| US20140091410A1 (en) * | 2008-08-14 | 2014-04-03 | Board Of Regents, The University Of Texas System | Method and Apparatus for Fabricating Piezoresistive Polysilicon by Low-Temperature Metal Induced Crystallization |
| CN102290335A (en) * | 2010-06-16 | 2011-12-21 | 三星移动显示器株式会社 | Method of forming a polycrystalline silicon layer and method of manufacturing thin film transistor |
| CN104465319A (en) * | 2014-10-30 | 2015-03-25 | 深圳市华星光电技术有限公司 | Manufacturing method for low-temperature polycrystalline silicon and manufacturing method for TFT substrate |
| CN105957805A (en) * | 2016-06-29 | 2016-09-21 | 京东方科技集团股份有限公司 | Manufacturing method of low-temperature polycrystalline silicon thin film, thin film transistor, array substrate and display device |
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| CN108172543A (en) * | 2018-01-12 | 2018-06-15 | 武汉华星光电半导体显示技术有限公司 | The stripping means and underlay substrate of a kind of flexible substrates |
| CN112397379A (en) * | 2020-11-16 | 2021-02-23 | 浙江大学 | Laser local annealing amorphous polycrystalline composite photoelectron integration method |
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