CN106782246B - GIP signal test circuit, GIP signal test method and display device - Google Patents
GIP signal test circuit, GIP signal test method and display device Download PDFInfo
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Abstract
The invention provides a GIP signal test circuit, a GIP signal test method and a display device, wherein the GIP signal test circuit comprises: a signal test line, a clock signal line, a first transistor, a plurality of second transistors, a plurality of third transistors, a plurality of capacitors and multi-level GIP signals; the second transistor, the third transistor, the capacitor and the GIP signals are in one-to-one correspondence; the first transistor is connected between the clock signal line and a signal test line; the signal testing line receives the multi-level GIP signals through the second transistors, the third transistors and the capacitors respectively and outputs testing signals according to the multi-level GIP signals, so that each level of GIP signals can be detected only by one signal testing line, the reliability of the GIP circuit is ensured on the basis that wiring is not increased basically, and meanwhile, the efficiency of poor analysis is improved.
Description
Technical Field
The invention relates to the technical field of panel display, in particular to a GIP signal testing circuit, a GIP signal testing method and a display device.
Background
In recent years, with the rapid development and application of information technology, wireless mobile communication and information appliances, people have increasingly depended on electronic products, and various display technologies and display devices have been developed. Flat panel display devices have been widely used because they are fully planar, light, thin, and power-saving.
Currently, with the development of flat Panel display technology, a Gate In Panel (GIP) technology, which is a novel technology for directly manufacturing a Gate driver of a flat Panel display device on a glass substrate through a mask plating technology, appears. Currently, the GIP technology integrates a scan chip on a display panel, thereby achieving the purposes of saving the scan chip, reducing material cost, reducing process steps and shortening process time, thereby reducing panel cost and realizing a narrower frame.
However, the display panel has many defects in the manufacturing process, and whether the GIP signal is normal or not needs to be tested during analysis, however, as the resolution of the screen body is higher and higher, it is impossible to lead out each stage by using a lead for signal measurement. In the prior art, a first-stage GIP signal and a last-stage GIP signal are generally led out by adopting lead wires for measurement. Please refer to fig. 1, which is a schematic diagram of a GIP signal testing circuit in the prior art. As shown in fig. 1, the gate driver circuit includes a first-stage cascade structure, a second-stage cascade structure …, an nth-stage cascade structure (a cascade structure of a last stage), which is generally a shift register. The gate driving circuit generates multi-stage GIP signals according to a signal sin input by an external circuit, a lead is adopted to lead out a 1 st-stage GIP signal S1 and a last-stage GIP signal Sn, a first-stage GIP signal S1 and a last-stage GIP signal Sn are tested, and the rest stages of GIP signals cannot be tested. Therefore, even if the GIP signals of the remaining stages are abnormal, the signals cannot be confirmed.
Therefore, how to solve the problem that the conventional flat panel display device cannot test each level of GIP signals without increasing the number of wires becomes a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
The invention aims to provide a GIP signal testing circuit, a GIP signal testing method and a display device, and aims to solve the problem that the display device in the prior art cannot test each level of GIP signals under the condition of not increasing routing lines.
To achieve the above object, the present invention provides a circuit for testing a GIP signal, comprising: a signal test line, a clock signal line, a first transistor, a plurality of second transistors, a plurality of third transistors, a plurality of capacitors and multi-level GIP signals; the second transistor, the third transistor, the capacitor and the GIP signals are in one-to-one correspondence; the first transistor is connected between the clock signal line and a signal test line; the signal test line receives the multi-level GIP signals through the plurality of second transistors, the plurality of third transistors and the plurality of capacitors, and outputs test signals according to the multi-level GIP signals.
Optionally, a first electrode of the first transistor is connected to the clock signal line, a second electrode of the first transistor is connected to the signal test line, and a gate of the first transistor is connected to the signal test line.
Optionally, a first electrode of the second transistor is connected to the signal test line, and a second electrode of the second transistor is connected to the corresponding GIP signal; the gate of the second transistor is connected to the second electrode of the corresponding third transistor.
Optionally, a first electrode of the third transistor is connected to the clock signal line, a second electrode and a gate of the third transistor are both connected to one end of the corresponding capacitor, and the other end of the capacitor is connected to the corresponding GIP signal.
Optionally, the first electrode is a source electrode, and the second electrode is a drain electrode; or, the first electrode is a drain electrode, and the second electrode is a source electrode; the first transistor to the third transistor are all thin film field effect transistors.
Correspondingly, the invention also provides a GIP signal testing method, which adopts the GIP signal testing circuit to test and comprises the following steps:
providing a clock signal and a multi-level GIP signal to the GIP signal test circuit; and
and outputting a test signal of the multi-stage GIP signal through the GIP signal test circuit.
Optionally, a falling edge of each stage of the GIP signal is delayed from a falling edge of the clock signal, and a rising edge of each stage of the GIP signal is advanced from a rising edge of the clock signal.
Optionally, the test cycle includes five phases:
in a first time period, the clock signal and a certain stage of GIP signal are both high potential, the first transistor and the third transistor are turned on, the second transistor is turned off, and the test signal is high potential;
in a second time period, the GIP signal is at a high potential, the clock signal is at a low potential, the first transistor, the second transistor and the third transistor are all turned off, and the test signal maintains at the high potential;
in a third time period, the GIP signal is at a low potential, the clock signal is at a low potential, the first transistor and the third transistor are turned off, the second transistor is turned on, and the test signal is at a low potential;
in a fourth time period, the GIP signal is at a high level, the clock signal is at a low level, the first transistor, the second transistor and the third transistor are all turned off, and the test signal is at a low level;
in a fifth time period, the GIP signal is at a high level, the clock signal is at a high level, the first transistor and the third transistor are turned on, the second transistor is turned off, and the test signal is at a high level.
Optionally, each low potential of the test signal corresponds to a stage GIP signal.
Optionally, the present invention further provides a display device, including: a GIP circuit, a plurality of scanning lines and the GIP signal test circuit;
the GIP circuit is connected with the GIP signal test circuit through the plurality of scanning lines and used for providing multi-stage GIP signals for the GIP signal test circuit, and the GIP signal test circuit outputs test signals according to the multi-stage GIP signals.
Compared with the prior art, the GIP signal test circuit, the GIP signal test method and the display device provided by the invention have the advantages that the novel GIP signal test circuit is adopted, each level of GIP signals can be detected only by one signal test line, the reliability of the GIP circuit is ensured on the basis that wiring is not basically added to the display device, and meanwhile, the efficiency of poor analysis is improved.
Drawings
Fig. 1 is a schematic structural diagram of a GIP signal test circuit in the prior art.
Fig. 2 is a schematic structural diagram of a GIP signal testing circuit according to an embodiment of the present invention.
Fig. 3 is a waveform diagram of a multi-stage GIP signal, a clock signal and a test signal according to an embodiment of the invention.
Detailed Description
In order to make the contents of the present invention more clearly understood, the contents of the present invention will be further described with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
The present invention is described in detail with reference to the drawings, and for convenience of explanation, the drawings are not enlarged partially according to the general scale, and should not be construed as limiting the present invention.
Referring to fig. 2, which is a schematic structural diagram of a GIP signal Test circuit according to an embodiment of the present invention, as shown in fig. 2, the GIP signal Test circuit includes a signal Test line Test L ine, a clock signal line CK, a first transistor T1 and a plurality of second transistors (T21 to T2n), a plurality of third transistors (T31 to T3n), a plurality of capacitors (C1 to Cn), and a plurality of stages of GIP signals, the second transistors (T21 to T2n), the third transistors (T31 to T3n), the capacitors (C1 to Cn), and the GIP signals correspond one-to-one, the first transistor T1 is connected between the clock signal line CK and the signal Test line Test L ine, the signal Test line Test L ine receives the plurality of stages of GIP signals through a plurality of second transistors (T21 to T2), a plurality of third transistors (T31 to T3n), and a plurality of capacitors (C1 to 3673729), and outputs the plurality of stages of GIP signals according to the plurality of stages of GIP signals, respectively.
The multi-stage GIP signals are respectively provided by first scan lines S1 to n-th scan lines Sn, the second transistors (T21 to T2n), the third transistors (T31 to T3 31), the capacitors (C31 to Cn) and the GIP signals are in one-to-one correspondence, that is, the second transistors (T31 to T2 31), the third transistors (T31 to T3 31) and the capacitors (C31 to Cn) are equal in number and number of stages of the GIP signals, for example, one second transistor is correspondingly connected with one third transistor, one capacitor and one scan line, the first scan line S31 provides a third stage GIP signal, the first stage GIP signal corresponds to the second transistor T31, the third transistor T31, the capacitor C31, the second scan line S31 provides a second stage GIP signal, the second stage GIP signal corresponds to the third transistor T31, the capacitor C31, the second scan line S31 provides a second stage GIP signal, the third transistor C31 and the third transistor Cn signal, the third transistor C31 receives the third signal, the third stage signal, the third transistor C31 and the third transistor C31, the third transistor C31 receives the third Test signal, the third transistor C31 and the third transistor C31 receive the third Test signal, the third transistor C31 and the third transistor C3 Test signal, the third transistor receives the third Test signal, the third transistor C3 signal, the third transistor receives the third Test.
Specifically, a first electrode of the first transistor T1 is connected to the clock signal line CK, a second electrode of the first transistor T1 is connected to the signal Test line Test L ine, and a gate of the first transistor T1 is connected to the signal Test line Test L ine.
The first electrodes of the second transistors (T21 to T2n) are connected to the signal Test line Test L ine, the second electrodes of the second transistors (T21 to T2n) are connected to the corresponding GIP signals, the gates of the second transistors (T21 to T2n) are connected to the second electrodes of the corresponding third transistors (T31 to T3n), in particular, the first electrode of the second transistor T21 is connected to the signal Test line Test L ine, the second electrode of the second transistor T21 is connected to the corresponding first stage GIP signal, the gates of the second transistors T21 are connected to the second electrodes of the corresponding third transistors T31, the first electrode of the second transistor T22 is connected to the signal Test line Test L ine, the second electrode of the second transistor T22 is connected to the corresponding second stage GIP signal, the gates of the second transistors T22 are connected to the corresponding second electrodes T32, the second electrodes of the second transistors T465 are connected to the corresponding second stage GIP signals, and so on the corresponding third transistors T6324.
A first electrode of the third transistor (T31 to T3n) is connected to the clock signal line CK, a second electrode and a gate of the third transistor (T31 to T3n) are connected to one end of the corresponding capacitor (C1 to Cn), and the other end of the capacitor (C1 to Cn) is connected to the corresponding GIP signal. Similarly, a first electrode of the third transistor T31 is connected to the clock signal line CK, a second electrode and a gate of the third transistor T31 are connected to one end of the corresponding capacitor C1, and the other end of the capacitor C1 is connected to the corresponding first stage GIP signal; a first electrode of the third transistor T32 is connected to the clock signal line CK, a second electrode and a gate electrode of the third transistor T32 are connected to one end of the corresponding capacitor C2, and the other end of the capacitor C2 is connected to the corresponding second stage GIP signal; by analogy, the first electrode of the third transistor T3n is connected to the clock signal line CK, the second electrode and the gate of the third transistor T3n are both connected to one end of the corresponding capacitor Cn, and the other end of the capacitor Cn is connected to the corresponding nth stage GIP signal.
In this embodiment, the first electrode is a source, and the second electrode is a drain; or, the first electrode is a drain electrode, and the second electrode is a source electrode. The transistors used in the embodiments of the present invention may all be thin film transistors or field effect transistors or other devices with the same characteristics, and preferably, the first transistor T1, the second transistor (T21 to T2n), and the third transistor (T31 to T3n) are all thin film field effect transistors.
The GIP signal Test circuit provided by the invention can detect each level of GIP signals only by one signal Test line Test L ine, so that the display device can ensure the reliability of the GIP circuit on the basis of not increasing the wiring basically, can find the abnormity of the GIP signals in time and improve the efficiency of poor analysis.
Correspondingly, the invention also provides a GIP signal test method, which adopts the GIP signal test circuit to carry out GIP signal test. Referring to fig. 3, which is a waveform diagram of multi-level GIP signals, clock signals and test signals according to an embodiment of the present invention, as shown in fig. 3, the GIP signal testing method includes:
the method comprises the following steps: providing a clock signal and a multi-level GIP signal to the GIP signal test circuit;
step two: and outputting a test signal of the multi-stage GIP signal through the GIP signal test circuit.
Specifically, first, a clock signal and a plurality of stages of GIP signals are provided to the GIP signal test circuit, where a falling edge of each stage of GIP signal in the plurality of stages of GIP signals is delayed with respect to a falling edge of the clock signal, and a rising edge of each stage of GIP signal is advanced with respect to a rising edge of the clock signal. In the present embodiment, each stage of GIP signals has a falling edge delayed by a period of T1 from the falling edge of the clock signal, and a rising edge advanced by a period of T3 from the rising edge of the clock signal.
As shown in fig. 3, the test cycle includes five stages, i.e., a first period T0, a second period T1, a third period T2, a fourth period T3 and a fifth period T4. At a first time period T0: the clock signal and a GIP signal of a certain stage are both high potential, the first transistor and the third transistor are turned on, the second transistor is turned off, and the test signal is high potential; in a second time period T1, the GIP signal is at a high level, the clock signal is at a low level, the first transistor, the second transistor, and the third transistor are all turned off, and the test signal maintains at the high level; in a third time period T2, the GIP signal is at a low potential, the clock signal is at a low potential, the first transistor and the third transistor are turned off, the second transistor is turned on, and the test signal is at a low potential; in a fourth time period T3, the GIP signal is at a high level, the clock signal is at a low level, the first transistor, the second transistor and the third transistor are all turned off, and the test signal is at a low level; in a fifth time period T4, the GIP signal is at a high level, the clock signal is at a high level, the first transistor and the third transistor are turned on, the second transistor is turned off, and the test signal is at a high level.
Specifically, in the first period T0, the first scan line S1 provides the first stage GIP signal, the clock signal CK and the first stage GIP signal are both at a high level, the first transistor T1 and the third transistor T31 are turned on, the second transistor T21 is turned off, and the Test signal Test L ine is at a high level.
In a second period T1, the first stage GIP signal is high, the clock signal CK is low, the first transistor T1, the second transistor T21, and the third transistor T31 are all turned off, and the Test signal Test L ine maintains a high level.
In a third time period T2, the GIP signal jumps to a low level, the clock signal CK is at a low level, the second transistor T21 is coupled by a capacitor C21, the second transistor T21 is turned on, the first transistor T1 and the third transistor T31 are turned off, and the Test signal Test L ine is connected to the first stage GIP signal and jumps to a low level.
During a fourth time period T3, the GIP signal jumps high, the clock signal maintains low, the first transistor T1, the second transistor T21, and the third transistor T31 are all turned off, and the Test signal Test L ine maintains low.
In a fifth period T4, the GIP signal is high, the clock signal CK is high, the first transistor T1 and the third transistor T31 are turned on, the second transistor T21 is turned off, and the Test signal Test L ine jumps to high.
Then, from the first time period T0, it is repeated again, as can be seen from fig. 3, at the time of the second repetition, the second scan line S2 provides the second stage GIP signal, at the first time period T0, the clock signal CK and the second stage GIP signal are both high, the first transistor T1, the third transistor T32 are turned on, the second transistor T22 is turned off, the Test signal Test L ine is high, at the second time period T1, the second stage GIP signal is high, the clock signal CK is low, the first transistor T1, the second transistor T22, and the third transistor T32 are all turned off, the Test signal Test L ine maintains high, at the third time period T2, the GIP signal jumps to low, the clock signal CK is low, the second transistor T2 is coupled by the capacitor C2, the third transistor T2 is turned on, the first transistor T2 and the first transistor T72 are turned on, the Test signal T2 is turned on, the third transistor T2, the Test signal T2 is turned off, the Test signal T2 is turned on the third transistor T2, the Test signal T2, the Test signal T2 is turned off, the Test signal T2 is turned on, the Test signal T2 is high, the Test signal T2 is turned off, the Test signal T2, the Test signal T2 is on the Test signal T2, the Test signal is on the Test signal is high, the Test signal is on the Test signal T2, the Test signal is on the.
This is repeated until the nth scan line provides the nth stage GIP signal, and finally the Test signal Test L ine is obtained, as shown in fig. 3, each low potential of the Test signal Test L ine corresponds to one stage GIP signal.
When each stage of GIP signals are normal, the Test signal output through the signal Test line Test L ine is as shown in fig. 3, the falling edge of each stage of GIP signal is delayed by a time period T1 from the falling edge of the clock signal, and the rising edge of each stage of GIP signal is advanced by time T3 from the rising edge of the clock signal.
Accordingly, the present invention further provides a display device, please refer to fig. 2, wherein the display panel includes: a GIP circuit (not shown in the drawing), a plurality of scan lines (S1 to Sn), and the GIP signal detection circuit as described above; the GIP circuit is connected to the GIP signal test circuit through the plurality of scan lines (S1 to Sn), and is configured to provide a multi-level GIP signal to the GIP signal test circuit, and the GIP signal test circuit outputs a test signal according to the multi-level GIP signal.
Specifically, the display device includes a display region in which a plurality of pixels (not shown) are arranged in a matrix and a non-display region (not shown) surrounding the display region, and the GIP circuit and the GIP signal Test circuit are generally disposed in the non-display region of the display device, wherein the GIP circuit respectively provides a plurality of stages of GIP signals through the plurality of scan lines (S1 to Sn), each stage of the GIP signals being for turning on one row of pixels, a plurality of second transistors (T21 to T2n), third transistors T31 to T3n), and capacitors (C1 to Cn) of the GIP signal Test circuit are in one-to-one correspondence with the plurality of scan lines and are connected to each other, and the signal Test line Test L ine respectively receives the plurality of stages of GIP signals through the plurality of second transistors (T21 to T2n), the plurality of third transistors (T31 to T3n), and the plurality of capacitors (C1 to Cn) and outputs the Test signals according to each stage of the GIP signals.
The conventional display device only leads out the GIP signals of the first stage and the last stage (the nth stage) for testing, not only needs two routing lines, but also cannot Test the GIP signals of the other stages except the first stage and the last stage, so that the reliability of the GIP circuit cannot be ensured.
The display device may be a liquid crystal display device (L CD), a plasma display device (PDP), an organic light emitting display device (O L ED), a flexible display device, or other types of display devices, and the specific type is not limited herein.
In summary, the GIP signal test circuit, the GIP signal test method and the display device provided by the invention adopt the novel GIP signal test circuit, and each level of GIP signal can be detected only by one signal test line, so that the display device ensures the reliability of the GIP circuit on the basis of not increasing the wiring basically, and improves the efficiency of bad analysis.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (6)
1. A GIP signal test circuit, comprising: a signal test line, a clock signal line, a first transistor, a plurality of second transistors, a plurality of third transistors, a plurality of capacitors and multi-level GIP signals; the second transistor, the third transistor, the capacitor and the GIP signals are in one-to-one correspondence; a first electrode of the first transistor is connected to the clock signal line, a second electrode of the first transistor is connected to the signal test line, and a gate electrode of the first transistor is connected to the signal test line; the signal test line receives multi-level GIP signals through a plurality of second transistors, a plurality of third transistors and a plurality of capacitors respectively, and outputs test signals according to the multi-level GIP signals; a first electrode of the second transistor is connected to the signal test line, and a second electrode of the second transistor is connected to the corresponding GIP signal; the grid electrode of the second transistor is connected to the second electrode of a corresponding third transistor, the first electrode of the third transistor is connected to the clock signal line, the second electrode and the grid electrode of the third transistor are both connected to one end of a corresponding capacitor, and the other end of the capacitor is connected to the corresponding GIP signal.
2. The GIP signal test circuit of claim 1, wherein the first electrode is a source electrode and the second electrode is a drain electrode; or, the first electrode is a drain electrode, and the second electrode is a source electrode; the first transistor to the third transistor are all thin film field effect transistors.
3. A method of performing a GIP signal test using the GIP signal test circuit of claim 1 or 2, comprising:
providing a clock signal and a multi-level GIP signal to the GIP signal test circuit; and
outputting a test signal of a multi-stage GIP signal through the GIP signal test circuit;
wherein, the test cycle includes five stages:
in a first time period, the clock signal and a certain stage of GIP signal are both high potential, the first transistor and the third transistor are turned on, the second transistor is turned off, and the test signal is high potential;
in a second time period, the GIP signal is at a high potential, the clock signal is at a low potential, the first transistor, the second transistor and the third transistor are all turned off, and the test signal maintains at the high potential;
in a third time period, the GIP signal is at a low potential, the clock signal is at a low potential, the first transistor and the third transistor are turned off, the second transistor is turned on, and the test signal is at a low potential;
in a fourth time period, the GIP signal is at a high level, the clock signal is at a low level, the first transistor, the second transistor and the third transistor are all turned off, and the test signal is at a low level;
in a fifth time period, the GIP signal is at a high level, the clock signal is at a high level, the first transistor and the third transistor are turned on, the second transistor is turned off, and the test signal is at a high level.
4. The GIP signal testing method as claimed in claim 3, wherein a falling edge of each stage of the GIP signal is delayed with respect to a falling edge of the clock signal, and a rising edge of each stage of the GIP signal is advanced with respect to a rising edge of the clock signal.
5. The GIP signal testing method of claim 4, wherein each low potential of the test signal corresponds to a one-level GIP signal.
6. A display device, comprising: a GIP circuit, a plurality of scan lines, and the GIP signal test circuit of claim 1 or 2;
the GIP circuit is connected with the GIP signal test circuit through the plurality of scanning lines and used for providing multi-stage GIP signals for the GIP signal test circuit, and the GIP signal test circuit outputs test signals according to the multi-stage GIP signals.
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| CN104299547B (en) * | 2014-09-26 | 2017-06-23 | 京东方科技集团股份有限公司 | A kind of method of testing of test circuit, display device and drive circuit |
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| CN105355163B (en) * | 2015-12-22 | 2019-01-04 | 昆山国显光电有限公司 | GIP signal deteching circuit, GIP signal detecting method and panel display apparatus |
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