CN106782240B - Test circuit based on CMOS GOA - Google Patents
Test circuit based on CMOS GOA Download PDFInfo
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
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Abstract
There is provided a CMOS GOA based test circuit comprising: a first PMOS transistor; a second PMOS transistor; a first NMOS transistor; a second NMOS transistor; the gate of the first PMOS transistor is connected with a first-level signal transmission end of the CMOS GOA, the gate of the second PMOS transistor is connected with an nth-level signal transmission end of the CMOS GOA, the first end of the first PMOS transistor is connected with a high level, the second end of the first PMOS transistor is connected with the first end of the second PMOS transistor, the second end of the second PMOS transistor is connected with an input end of the inverter, n is the total number of level transmission signals, the gate of the first NMOS transistor is connected with the first-level signal transmission end of the CMOS GOA, the gate of the second NMOS transistor is connected with the nth-level signal transmission end of the CMOS GOA, the first end of the first NMOS transistor and the first end of the second NMOS transistor are connected with the input end of the inverter, and the second end of the first NMOS transistor and the second end of the second NMOS transistor are connected with a low level.
Description
Technical Field
The invention relates to the field of GOA circuit design, in particular to an output test circuit design based on CMOS GOA.
Background
In recent years, with the trend of thin display, Liquid Crystal Displays (LCDs), Organic Light Emitting Diode (OLED) displays, and the like have been widely used in various electronic products (e.g., mobile phones, notebook computers, televisions, and the like).
The Gate Driver On Array (GOA) technology is a technology that directly manufactures a Gate driving circuit On an Array substrate by using the existing thin film transistor liquid crystal display Array manufacturing process to realize the driving mode of scanning the Gate line by line. The application of the technology can directly manufacture the grid drive circuit around the panel, thereby reducing manufacturing procedures, lowering product cost, improving panel integration level and enabling the panel to be thinner.
In current GOA circuit design, in order to detect GOA operation, a test circuit is usually used to monitor the first stage transmission signal and the last stage transmission signal of the GOA circuit.
Fig. 1 shows an array substrate architecture of a common LCD. Generally, a first-stage transmission signal and a last-stage transmission signal of a GOA circuit are monitored at design stages of Array Test (Array Test), Cell Test (Cell Test), Flexible Printed Circuit (FPC), and the like through Test circuit design and routing. And calculating the working condition of the GOA according to the monitored first-stage transmission signal and the last-stage transmission signal of the GOA circuit, thereby better controlling the yield of the product, analyzing the problem and the like.
Fig. 2 shows a cascaded circuit diagram in a panel of a conventional CMOS GOA circuit. Referring to fig. 2, STV denotes a start trigger signal, U2D denotes a top-down scan control signal (i.e., a forward scan control signal), D2U denotes a bottom-up scan control signal (i.e., a reverse scan control signal), Reset denotes a Reset signal, CK1 and CK3 denote clock signals, VGH denotes a high level signal, and VGL denotes a low level signal. According to the cascade circuit of fig. 2, when the CMOS GOA scans in a forward direction, a final-stage (i.e., 2n-1 st stage) level signal may be output as a test output signal (VT). However, when the CMOS GOA is scanned reversely, a final-stage (i.e., stage 1) level signal cannot be output as a test output signal (VT). Therefore, such a test circuit has a drawback that the last stage signal cannot be tested when the CMOS GOA is scanned in reverse.
Therefore, there is a need for a test circuit that can effectively monitor both the first stage signaling and the last stage signaling of a CMOS GOA.
Disclosure of Invention
The present invention is provided to solve at least the above problems and disadvantages and to provide at least the advantages described below.
According to an aspect of the present invention, there is provided a CMOS GOA based test circuit, including: a first PMOS transistor; a second PMOS transistor; a first NMOS transistor; a second NMOS transistor; the gate of the first PMOS transistor is connected with a first-level signal transmission end of the CMOS GOA, the gate of the second PMOS transistor is connected with an nth-level signal transmission end of the CMOS GOA, the first end of the first PMOS transistor is connected with a high level, the second end of the first PMOS transistor is connected with the first end of the second PMOS transistor, the second end of the second PMOS transistor is connected with an input end of the inverter, n is the total number of level transmission signals, the gate of the first NMOS transistor is connected with the first-level signal transmission end of the CMOS GOA, the gate of the second NMOS transistor is connected with the nth-level signal transmission end of the CMOS GOA, the first end of the first NMOS transistor and the first end of the second NMOS transistor are connected with the input end of the inverter, and the second end of the first NMOS transistor and the second end of the second NMOS transistor are connected with a low level.
When the CMOS GOA scans in the forward direction, the first-stage transmission signal end can output a first-stage transmission signal, and the nth-stage transmission signal end can output a last-stage transmission signal.
The output terminal of the inverter may output a test output signal including signals of both the first-stage signal terminal and the nth-stage signal terminal.
In another example, the test circuit further comprises a third NMOS transistor; and a fourth NMOS transistor, wherein a third NMOS transistor and a fourth NMOS transistor are respectively connected between the first end of the first NMOS transistor and the first end of the second NMOS transistor and the input end of the phase inverter, the grid electrode of the third NMOS transistor is connected with the first scanning direction control end, the grid electrode of the fourth NMOS transistor is connected with the second scanning direction control end, the first end of the third NMOS transistor and the first end of the fourth NMOS transistor are connected with the input end of the phase inverter, the second end of the third NMOS transistor is connected with the first end of the first NMOS transistor, and the second end of the fourth NMOS transistor is connected with the first end of the second NMOS transistor.
In another example, the first stage transmission signal terminal may output a first stage transmission signal and the nth stage transmission signal terminal may output a last stage transmission signal when the CMOS GOA scans in a forward direction, wherein the first stage transmission signal terminal may output the last stage transmission signal and the nth stage transmission signal terminal may output the first stage transmission signal when the CMOS GOA scans in a reverse direction.
In another example, when the CMOS GOA scans in the forward direction, the first scan direction control terminal outputs a low level and the second scan direction control terminal outputs a high level, wherein when the CMOS GOA scans in the reverse direction, the first scan direction control terminal outputs a high level and the second scan direction control terminal outputs a low level.
In another example, the output terminal of the inverter outputs a test output signal including a signal of an nth-stage pass signal terminal when the CMOS GOA scans in a forward direction, wherein the output terminal of the inverter outputs the test output signal including a signal of a first-stage pass signal terminal when the CMOS GOA scans in a reverse direction.
According to the CMOS GOA-based test circuit, new control signals do not need to be added, new ICs do not need to be developed, and real-time monitoring of first-stage transmission signals and last-stage transmission signals of the CMOS GOA circuit or real-time monitoring of last-stage transmission signals of the CMOS GOA circuit can be achieved only by adding a small number of thin film transistors during design of an array substrate.
Drawings
The above and other aspects, features and advantages of various embodiments of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:
FIG. 1 illustrates an array substrate architecture of a conventional LCD;
FIG. 2 is a circuit diagram of a conventional CMOS GOA circuit cascaded in a panel;
FIG. 3 is a circuit diagram of a CMOS GOA based test circuit according to an embodiment of the present invention;
FIG. 4 is a timing diagram of the output of test signals of the CMOS GOA based test circuit of FIG. 3;
FIG. 5 is a circuit diagram of a CMOS GOA based test circuit according to another embodiment of the present invention;
FIG. 6 is a timing diagram of test signal output of the CMOS GOA based test circuit of FIG. 5 when the CMOS GOA is scanned in a forward direction;
fig. 7 is a timing diagram of test signal output of the CMOS GOA-based test circuit of fig. 5 when the CMOS GOA is scanned in reverse.
Detailed Description
Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings to make it easier for those of ordinary skill in the art to understand. The exemplary embodiments of the invention presently claimed herein may take a variety of forms and are not limited to the examples shown and described herein. Descriptions of well-known structures and functions may be omitted for clarity, while inclusion of such structures and functions may not make clear the understanding of the present invention to those of ordinary skill in the art, and like reference numerals refer to like elements throughout the description.
Fig. 3 is a circuit diagram of a CMOS GOA based test circuit in accordance with an embodiment of the present invention.
Referring to fig. 3, a CMOS GOA based test circuit 300 according to an embodiment of the present invention includes a first PMOS transistor 301, a second PMOS transistor 302, a first NMOS transistor 303, a second NMOS transistor 304, and an inverter 305.
The CMOS GOA based test circuit 300 according to an embodiment of the present invention can monitor the first stage signaling and the last stage signaling of the CMOS GOA circuit. Here, for convenience of description, the total number of stage transmission signals is n, and the last stage transmission signal is the nth stage transmission signal.
Specifically, the gate G301 of the first PMOS transistor 301 is connected to the first-stage signal terminal ST (1) of the CMOS GOA circuit, the first terminal 301-1 of the first PMOS transistor 301 is connected to the high level VGH, and the second terminal 301-2 of the first PMOS transistor 301 is connected to the first terminal 302-1 of the second PMOS transistor 302.
The gate G302 of the second PMOS transistor 302 is connected to the nth pass signal terminal st (n) of the CMOS GOA circuit. A second terminal 302-2 of the second PMOS transistor 302 is connected to an input IN of an inverter 305.
The gate G303 of the first NMOS transistor 303 is connected to the first-stage signal terminal ST (1) of the CMOS GOA, the first terminal 303-1 of the first NMOS transistor 303 is connected to the input terminal IN of the inverter 305, and the second terminal 303-2 of the first NMOS transistor 303 is connected to the low level VGL.
The gate G304 of the second NMOS transistor 304 is connected to the nth pass signal terminal st (n) of the CMOS GOA circuit, the first terminal 304-1 of the second NMOS transistor 304 is connected to the input terminal IN of the inverter 305, and the second terminal 304-2 of the second NMOS transistor 304 is connected to the low level VGL.
The CMOS GOA-based test circuit 300 according to an embodiment of the present invention may output a test output signal VT through an output terminal OUT of the inverter 305, wherein the test output signal VT may include both a signal of a first-stage pass signal terminal ST (1) and a signal of an nth-stage pass signal terminal ST (n).
Specifically, according to the circuit of the CMOS GOA, when the CMOS GOA scans in the forward direction (i.e., scans from top to bottom), the first stage signal terminal ST (1) outputs a first stage signal, and the nth stage signal terminal ST (n) outputs a last stage signal. When the CMOS GOA performs a reverse scan (i.e., a bottom-to-top scan), the first stage signal terminal ST (1) outputs a last stage signal, and the nth stage signal terminal ST (n) outputs a first stage signal.
Accordingly, the CMOS GOA-based test circuit 300 according to an embodiment of the present invention can output a test output result including a first stage pass signal and a last stage pass signal regardless of whether the CMOS GOA forward scan or the reverse scan.
Fig. 4 is a timing diagram of a test signal output of the CMOS GOA-based test circuit of fig. 3.
Referring to fig. 4, when the first stage signal terminal ST (1) outputs a high level and the nth stage signal terminal ST (n) outputs a low level, the first PMOS transistor 301 is turned off, the second PMOS transistor 302 is turned on, the first NMOS transistor 303 is turned on, and the second NMOS transistor 304 is turned off, so that the input terminal IN of the inverter 305 inputs a low level and the output terminal OUT of the inverter 305 outputs a high level.
When the first stage signal terminal ST (1) outputs a high level and the nth stage signal terminal ST (n) outputs a high level, the first PMOS transistor 301 is turned off, the second PMOS transistor 302 is turned off, the first NMOS transistor 303 is turned on, and the second NMOS transistor 304 is turned on, so that the input terminal IN of the inverter 305 inputs a low level and the output terminal OUT of the inverter 305 outputs a high level.
When the first stage signal terminal ST (1) outputs a low level and the nth stage signal terminal ST (n) outputs a high level, the first PMOS transistor 301 is turned on, the second PMOS transistor 302 is turned off, the first NMOS transistor 303 is turned off, and the second NMOS transistor 304 is turned on, so that the input terminal IN of the inverter 305 inputs a low level and the output terminal OUT of the inverter 305 outputs a high level.
When the first stage signal terminal ST (1) outputs a low level and the nth stage signal terminal ST (n) outputs a low level, the first PMOS transistor 301 is turned on, the second PMOS transistor 302 is turned on, the first NMOS transistor 303 is turned off, and the second NMOS transistor 304 is turned off, so that the input terminal IN of the inverter 305 inputs a high level and the output terminal OUT of the inverter 305 outputs a low level.
It can be seen that the connection structure of the first PMOS transistor 301, the second PMOS transistor 302, the first NMOS transistor 303, and the second NMOS transistor 304 corresponds to a nor gate. That is, the CMOS GOA-based test circuit 300 according to the embodiment of the present invention implements the function of simultaneously monitoring the first-stage transmission signal and the last-stage transmission signal of the CMOS GOA circuit through one nor gate and one inverter.
It can be seen that the test circuit 300 based on CMOS GOA according to the embodiment of the present invention does not need to add new control signals or develop new ICs, and can implement real-time monitoring of the first-stage transmission signals and the last-stage transmission signals of the CMOS GOA circuit by only adding a small number of thin film transistors during the design of the array substrate.
Fig. 5 is a circuit diagram of a CMOS GOA based test circuit according to another embodiment of the present invention.
Referring to fig. 5, a CMOS GOA based test circuit 500 according to another embodiment of the present invention adds two NMOS transistors compared to the CMOS GOA based test circuit 300 shown in fig. 3. As shown in fig. 5, the CMOS GOA based test circuit 500 includes a first PMOS transistor 501, a second PMOS transistor 502, a first NMOS transistor 503, a second NMOS transistor 504, a third NMOS transistor 505, a fourth NMOS transistor 506, and an inverter 50.
The CMOS GOA based test circuit 500 according to another embodiment of the present invention adds two scan direction control terminals to the CMOS GOA based test circuit 300 of fig. 3, i.e. a third NMOS transistor 504 and a fourth NMOS transistor 504 are connected between the first terminal 503-1 of the first NMOS transistor 503 and the first terminal 504-1 of the second NMOS transistor 504, respectively, and the input terminal IN of the inverter 507. In this case, the CMOS GOA based test circuit 500 according to another embodiment of the present invention can monitor the last stage signaling of the CMOS GOA circuit. Here, for convenience of description, the total number of stage transmission signals is n, and the last stage transmission signal is the nth stage transmission signal.
Specifically, the gate G501 of the first PMOS transistor 501 is connected to the first-stage signal terminal ST (1) of the CMOS GOA, the first terminal 501-1 of the first PMOS transistor 501 is connected to the high level VGH, and the second terminal 301-2 of the first PMOS transistor 501 is connected to the first terminal 502-1 of the second PMOS transistor 502.
The gate G502 of the second PMOS transistor 502 is connected to the nth stage signal terminal st (n) of the CMOS GOA. A second terminal 502-2 of the second PMOS transistor 502 is connected to the input IN of the inverter 507.
The gate G503 of the first NMOS transistor 503 is connected to the first-stage signal terminal ST (1) of the CMOS GOA, the first terminal 503-1 of the first NMOS transistor 503 is connected to the second terminal 505-2 of the third NMOS transistor 505, and the second terminal 503-2 of the first NMOS transistor 503 is connected to the low level VGL.
The gate G504 of the second NMOS transistor 504 is connected to the nth stage signal terminal st (n) of the CMOS GOA, the first terminal 504-1 of the second NMOS transistor 504 is connected to the second terminal 506-2 of the fourth NMOS transistor 506, and the second terminal 504-2 of the second NMOS transistor 504 is connected to the low level VGL.
The gate G505 of the third NMOS transistor 505 is connected to the first scan direction control terminal D2U, and the first terminal 505-1 of the third NMOS transistor 505 is connected to the input terminal IN of the inverter 507.
The gate G506 of the fourth NMOS transistor 506 is connected to the second scan direction control terminal U2D, and the first terminal 506-1 of the fourth NMOS transistor 506 is connected to the input terminal IN of the inverter 507.
According to the circuit of the CMOS GOA, when the CMOS GOA scans in the forward direction, the first stage transfer signal terminal ST (1) outputs a first stage transfer signal, the nth stage transfer signal terminal ST (n) outputs a last stage transfer signal, and the first scan direction control terminal D2U outputs a low level and the second scan direction control terminal U2D outputs a high level. When the CMOS GOA performs the reverse scan, the first pass signal terminal ST (1) outputs the last pass signal, the nth pass signal terminal ST (n) outputs the first pass signal, the first scan direction control terminal D2U outputs the high level, and the second scan direction control terminal U2D outputs the low level.
In this way, the CMOS GOA-based test circuit 500 according to another embodiment of the present invention may output the test output signal VT including a signal of the nth stage pass signal terminal (i.e., a last stage pass signal at the time of the CMOS GOA forward scan) through the output terminal OUT of the inverter 507 at the time of the CMOS GOA forward scan, and may output the test output signal including a signal of the first stage pass signal terminal (i.e., a last stage pass signal at the time of the CMOS GOA reverse scan) through the output terminal OUT of the inverter 507 at the time of the CMOS GOA reverse scan.
Accordingly, the CMOS GOA-based test circuit 500 according to another embodiment of the present invention can output a test output result including a final stage pass signal regardless of the GOA forward scan or reverse scan.
Fig. 6 is a test signal output timing diagram of the CMOS GOA-based test circuit of fig. 5 when the CMOS GOA scans in a forward direction.
The CMOS GOA-based test circuit 500 according to another embodiment of the present invention monitors the signal of the nth stage signal terminal st (n) when the CMOS GOA is scanned in the forward direction.
Specifically, when the CMOS GOA scans in the forward direction, the first scanning-direction control terminal D2U outputs a low level, and the second scanning-direction control terminal U2D outputs a high level. IN this case, when the nth stage signal terminal ST (n) outputs a low level, the input terminal IN of the inverter 507 inputs a high level and the output terminal OUT of the inverter 507 outputs a low level regardless of whether the first stage signal terminal ST (1) outputs a high level or a low level. When the nth stage signal terminal ST (n) outputs a high level, the input terminal IN of the inverter 507 inputs a low level and the output terminal OUT of the inverter 507 outputs a high level regardless of whether the first stage signal terminal ST (1) outputs a high level or a low level.
Fig. 7 is a timing diagram of test signal output of the CMOS GOA-based test circuit of fig. 5 when the GOA is scanned in reverse.
The CMOS GOA-based test circuit 500 according to another embodiment of the present invention monitors a signal of the first-stage pass signal terminal ST (1) when the CMOS GOA is scanned in reverse.
Specifically, when the CMOS GOA is scanned in reverse, the first scanning-direction control terminal D2U outputs a high level, and the second scanning-direction control terminal U2D outputs a low level. IN this case, when the first-stage signal terminal ST (1) outputs a low level, the input terminal IN of the inverter 507 inputs a high level and the output terminal OUT of the inverter 507 outputs a low level regardless of whether the nth-stage signal terminal ST (n) outputs a high level or a low level. When the first-stage signal terminal ST (1) outputs a high level, the input terminal IN of the inverter 507 inputs a low level and the output terminal OUT of the inverter 507 outputs a high level regardless of whether the nth-stage signal terminal ST (n) outputs a high level or a low level.
It can be seen that the test circuit 500 based on CMOS GOA according to the embodiment of the present invention does not need to add new control signals or develop new ICs, and can implement real-time monitoring of the last-stage transmission signals of the CMOS GOA circuit by only adding a small number of thin film transistors during the design of the array substrate.
While the present invention has been shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.
Claims (6)
1. A CMOS GOA based test circuit comprising:
a first PMOS transistor;
a second PMOS transistor;
a first NMOS transistor;
a second NMOS transistor;
an inverter is provided to convert the voltage of the power source into a voltage,
wherein the grid of the first PMOS transistor is connected with the first-stage signal transmission end of the CMOS GOA, the grid of the second PMOS transistor is connected with the nth-stage signal transmission end of the CMOS GOA, the first end of the first PMOS transistor is connected with a high level, the second end of the first PMOS transistor is connected with the first end of the second PMOS transistor, the second end of the second PMOS transistor is connected with the input end of the phase inverter, wherein n is the total number of stage transmission signals,
wherein, the grid of the first NMOS transistor is connected with the first-stage signal transmission end of the CMOS GOA, the grid of the second NMOS transistor is connected with the nth-stage signal transmission end of the CMOS GOA, the first end of the first NMOS transistor and the first end of the second NMOS transistor are connected with the input end of the phase inverter, the second end of the first NMOS transistor and the second end of the second NMOS transistor are connected with low level,
under the condition that the CMOS GOA carries out forward scanning, the test circuit outputs a test output result comprising a first-stage transmission signal and a last-stage transmission signal; and under the condition that the CMOS GOA carries out reverse scanning, the test circuit outputs a test output result comprising a first stage transmission signal and a last stage transmission signal.
2. The test circuit of claim 1, further comprising:
a third NMOS transistor;
a fourth NMOS transistor having a first terminal connected to a second terminal,
wherein a third NMOS transistor and a fourth NMOS transistor are respectively connected between the first ends of the first and second NMOS transistors and the input end of the inverter,
the grid electrode of the third NMOS transistor is connected with the first scanning direction control end, the grid electrode of the fourth NMOS transistor is connected with the second scanning direction control end, the first end of the third NMOS transistor and the first end of the fourth NMOS transistor are connected with the input end of the phase inverter, the second end of the third NMOS transistor is connected with the first end of the first NMOS transistor, and the second end of the fourth NMOS transistor is connected with the first end of the second NMOS transistor.
3. The test circuit of claim 1 or 2, wherein the first stage pass signal terminal outputs a first stage pass signal, the nth stage pass signal terminal outputs a last stage pass signal when the CMOS GOA scans in a forward direction,
when the CMOS GOA performs reverse scanning, the first-stage signal transmission end outputs a last-stage signal transmission, and the nth-stage signal transmission end outputs a first-stage signal transmission.
4. The test circuit of claim 1, wherein the output of the inverter outputs a test output signal comprising signals of both the first stage signal terminal and the nth stage signal terminal.
5. The test circuit of claim 2, wherein the first scan direction control terminal outputs a low level and the second scan direction control terminal outputs a high level when the CMOS GOA is scanned in a forward direction,
when CMOS GOA is scanned reversely, the first scanning direction control end outputs high level, and the second scanning direction control end outputs low level.
6. The test circuit of claim 2, wherein the output terminal of the inverter outputs a test output signal including a signal of the nth stage pass signal terminal when the CMOS GOA is scanned in a forward direction,
when the CMOS GOA is scanned reversely, the output end of the phase inverter outputs a test output signal comprising a signal of the first-stage signal transmission end.
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| CN110085183B (en) * | 2019-04-23 | 2021-07-06 | 深圳市华星光电半导体显示技术有限公司 | Display panel and GOA circuit testing method thereof |
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| CN105047115B (en) * | 2015-08-10 | 2018-03-27 | 武汉华星光电技术有限公司 | Detect drive circuit, detection drive device and detection method |
| CN105047159B (en) * | 2015-08-24 | 2017-11-10 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and liquid crystal display |
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