CN106777621A - A kind of neutral net space reflection modeling method for packaged transistor - Google Patents
A kind of neutral net space reflection modeling method for packaged transistor Download PDFInfo
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Abstract
Set up accurate packaged transistor model most important to improving wireless communication system circuit precision.To overcome existing packaged transistor modeling method to need internal structural information and computationally intensive shortcoming, the present invention to propose the neutral net space reflection modeling method for packaged transistor.The method is that packaged transistor model is divided into input package circuit module, nonlinear circuit module and the part of output encapsulated circuit module three, and building structure respectively.Model after training can not only accurately reflect the characteristic of packaged transistor, and simulation velocity is fast, greatly shortens the design cycle, and possibility is provided further to design more massive circuit.
Description
Technical field
Built in microwave the present invention relates to microwave circuits and devices modeling method, more particularly to neutral net Method with Space Mapping Technique
The application in mould field.
Background technology
To meet low cost, low-power consumption, high accuracy, highly reliable, intelligent electronic product demand for development, for channel radio
Power transistor structure in letter system becomes increasingly complex, in addition to increasing multiple tube cores and power be provided, transistor internal envelope
Bonding line and MOS capacitor in dress circuit also increase, to ensure the stability and performance of transistor.Each element of transistor internal
Between coupling and encapsulated circuit ghost effect on transistor performance influence it is increasing, this is carried to CAD modeling techniques
Huge challenge is gone out.
The modeling method to packaged transistor mainly has two kinds at present：Equivalent circuit method and Electromagnetic Simulation method.Document has been demonstrate,proved
Bright existing equivalent circuit method and Electromagnetic Simulation method can accurately set up transistor encapsulated circuit model, but both approaches
There is certain application limitation.But both approaches have certain application limitation.The crystalline substance set up with equivalent circuit method
Body pipe encapsulated circuit model structure is simple, it is easy to operate, but the parameter in equivalent circuit influences each other, only by simulation software certainly
Dynamic optimization is extremely difficult to precision higher.The transistor encapsulated circuit model built with electromagnetism emulation modelling method is substantially increased
The precision of model, but model needs the specific structural information in known device inside, and constantly tune is needed in modeling process
The physical parameter and electrical parameter of integral mould structure, this needs powerful computer resource, and needs the optimization time grown very much.Remove
Outside this, document electrical equivalent method and Electromagnetic Simulation method are directed to the model that the encapsulated circuit of power transistor is built, and do not wrap
Modeling containing transistor non-linear partial.Cannot also complete to build the packaged transistor of unknown internal structure using both approaches
Mould.
In recent years, in microwave/radio frequency modeling field, artificial neural network is acknowledged as being that instead of traditional modeling
Effective ways.Neutral net space reflection modeling method is one kind of knowledge type neural network modeling approach, and the method is merged
The advantage of artificial neural network and space reflection., the precision of existing model can be greatly improved.But existing neutral net space
Primarily directed to the modeling of transistor dies, model cannot reflect shadow of the encapsulated circuit to transistor performance to mapping, modeling method
Ring.
Packaged transistor turned into irreplaceable device in contemporary communication system, and present invention research packaged transistor is built
Mould method, sets up high precision, fireballing model, not only greatly shortens the design cycle, and further to design more extensive
Circuit provide may, be with a wide range of applications.
The content of the invention
The purpose of the present invention is the above-mentioned deficiency for overcoming prior art, proposes a kind of neutral net for packaged transistor
Space reflection modeling method, is that packaged transistor model is divided into input package circuit module, nonlinear circuit module and output
The part of encapsulated circuit module three, and building structure respectively.
A kind of neutral net space reflection modeling method for packaged transistor, comprises the following steps：
Step 1：Packaged transistor model is divided into three parts：Input package circuit module, nonlinear circuit module, output
Encapsulated circuit module.Simulate the line of the input/output encapsulated circuit of packaged transistor respectively with input/output encapsulated circuit module
Property characteristic, with the nonlinear characteristic of nonlinear circuit module simulation packaged transistor tube core.
Step 2：Build nonlinear circuit module.From existing model (referred to as roughcast type) as the packaged transistor mould
The nonlinear circuit module of type.(its performance should try one's best and be modeled the transistor model of the optional device manufacturer research of the module
Packaged transistor similar nature), also can select the universal transistor model provided in simulation software (needs first with sample data pair
The model optimization, makes its performance to try one's best and is modeled packaged transistor Performance Match).
Step 3：Build input/output encapsulated circuit module.Because the encapsulated circuit of transistor is mainly passive device group
Into, so encapsulated circuit is passive circuit, that is, there is S11=S22.Encapsulated circuit part in packaged transistor model is recognized
To be loss-free, then the modulus value quadratic sum of the loss of its network echo and insertion loss is 1, i.e., | S11|2+|S21|2=1 and | S12
|2+|S22|2=1.The relation established between frequency and S parameter using above property, is completed input/output encapsulated circuit module and built
It is vertical.
Step 4：Build mapping network circuit.The present invention further adjusts model accuracy using mapping network.Used in model
VCVS and CCCS realize that mapping network is built.
Step 5：Packaged transistor model is trained with sample data.With direct current sample data with exchange sample data to model
In parameter adjustment, make the DC characteristic of model and AC characteristic consistent with sample data.
In this patent step 3, the relation in input/output encapsulated circuit module between frequency and S parameter can use two
The method of kind is realized.The first realizes that it is frequency, output neuron to be input into neuron with the neural network structure of multilayer perceptron
It is the real part and imaginary part of S parameter, its expression formula is：
Wherein fANNNeutral net mapping relations are represented, w represents neutral net inside weight, and R and I represent S parameter respectively
Real part and imaginary part.
Realized with numerical computations for second, i.e.,
Wherein x1, x2, x3, x4Expression is Optimal Parameters, and f () represents the algebraic relation of input and output, i.e. frequency, excellent
Change the real part and the relation of imaginary part of parameter and S parameter, can be converted by the amplitude of S parameter and phase and obtained.
In this patent step 4, output mapping network is realized using CCCS, formula is
igf.dc=fANN1(vgf.dc, vdf.dc, igc.dc, idc.dc, w1) (3)
idf.dc=fANN2(vgf.dc, vdf.dc, igc.dc, idc.dc, w2) (4)
Wherein fANN1And fANN2Represent neutral net mapping relations, w1And w2Represent neutral net inside weight.
In this patent step 4, input mapping network is realized using VCVS, formula is
vgc.ac=hANN1(vgf.ac, vdf.ac, w3) (5)
vdc.ac=hANN2(vgf.ac, vdf.ac, w4) (6)
Wherein hANN1And hANN2Represent neutral net mapping relations, w3And w4Represent neutral net inside weight.
It is first that the input mapping network in model and output mapping network is unitization in this patent step 5, so as to ensure mould
Type does not make model performance be deteriorated because introducing mapping network；Then the direct current of packaged transistor model is adjusted with output mapping network
Characteristic；The AC characteristic of packaged transistor model is adjusted with input mapping network again；Finally to the input mapping network in model
Finely tuned with output mapping network parameter, make the DC characteristic of model and AC characteristic and measure or emulate packaged transistor performance
It is identical.
The neutral net space reflection modeling method that this patent is proposed does not need packaged transistor internal structural information not only,
And neural network structure is simple, the output of Optimal Parameters independent control model different qualities, model DC characteristic and AC characteristic
Between be independent of each other, can accurately reflect the characteristic of packaged transistor.
Brief description of the drawings：
Fig. 1 is structured flowchart of the present invention；
Fig. 2 is the sample data and model output characteristic curve of the embodiment of the present invention.
Specific embodiment：
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to implementation of the invention
Example is described in detail.
When being modeled to packaged transistor using modeling method proposed by the present invention, its model structure is as shown in Figure 1.Model master
It is divided into input package circuit module, thick model module, output encapsulated circuit module and mapping circuit four parts, wherein with defeated
Enter/export the linear characteristic that encapsulated circuit module simulates the input/output encapsulated circuit of packaged transistor respectively, use roughcast pattern
Block simulates the nonlinear characteristic of packaged transistor tube core, and the characteristic of whole model is adjusted with mapping circuit.
From existing model as the packaged transistor model thick model module.If from the crystalline substance of device manufacturer research
Body tube model is used as roughcast type, then it is required that its performance should try one's best and be modeled packaged transistor similar nature；If from emulation
The universal transistor model provided in software is used as roughcast type, then needs first with sample data to the model optimization, makes it
Performance should try one's best and be modeled packaged transistor Performance Match.
Because the DC characteristic of packaged transistor is only controlled by DC offset voltage, therefore for adjusting AC signal
Input mapping network can be ignored.The characteristic of encapsulated circuit module simulation encapsulated circuit, the bias point with work is unrelated, does not influence
The DC characteristic of transistor, so can ignore encapsulated circuit module during adjustment model DC characteristic.It is special in Optimized model direct current
Property when, with sample DC data to model training, the parameter value in mapping 1 and output 2 networks of mapping is exported in adjustment Fig. 1, make
Model obtains accurate DC characteristic, and output mapping network uses three layer perceptron structure, and its relational expression is as shown in Figure 1.
The encapsulated circuit of transistor is mainly what is be made up of bonding line, MOS capacitor and integrated capacitance, and these devices are
Passive device, so encapsulated circuit is passive circuit.Relation between the characteristic frequency and S parameter of passive network is represented.Envelope
Relation in dress circuit module between frequency and S parameter can be realized using two methods.The first uses the god of multilayer perceptron
Realized through network structure, that is, it is frequency to be input into neuron, and output neuron is the real part and imaginary part of S parameter, and its expression formula is：
Wherein fANNNeutral net mapping relations are represented, w represents neutral net inside weight, and R and I represent S parameter respectively
Real part and imaginary part.
Realized with numerical computations for second, its expression formula is：
Wherein x1, x2, x3, x4Expression is Optimal Parameters, and f () represents the algebraic relation of input and output, i.e. frequency, excellent
Change the real part and the relation of imaginary part of parameter and S parameter, can be converted by the amplitude of S parameter and phase and obtained.
The present invention adjusts the AC characteristic of model using encapsulated circuit module.When the step is trained, fixed output mapping
Network parameter values, make following set-up procedure no longer influence the DC characteristic of model.With sample S parameter data to model training,
The parameter value in input and output package module is adjusted simultaneously, model is obtained accurate AC characteristic.
Further to improve the precision of model, the present invention is adjusted using input mapping network to the AC characteristic of model.
The parameter value being input into mapping 1 and input 2 networks of mapping in data point reuse Fig. 1 is exchanged with sample, model is accurately handed over
Properties of flow, input mapping network uses three layer perceptron structure, and its relational expression is as shown in Figure 1.
Fig. 2 is to set up packaged transistor model output characteristic curve using modeling method of the present invention to compare with sample data
Figure, it can be seen that the curve of output of model is consistent with sample data.
Claims (5)
1. a kind of neutral net space reflection modeling method for packaged transistor, comprises the following steps：
Step 1：Packaged transistor model is divided into three parts：Input package circuit module, nonlinear circuit module, output encapsulation
Circuit module, the linear spy for simulating the input/output encapsulated circuit of packaged transistor respectively with input/output encapsulated circuit module
Property, with the nonlinear characteristic of nonlinear circuit module simulation packaged transistor tube core；
Step 2：Nonlinear circuit module is built, from existing model (referred to as roughcast type) as the packaged transistor model
Nonlinear circuit module, (its performance should try one's best and be modeled encapsulation the transistor model of the optional device manufacturer research of the module
Transistor performance is close), also can select the universal transistor model provided in simulation software (needs first with sample data to the mould
Type optimizes, and its performance is tried one's best and is modeled packaged transistor Performance Match)；
Step 3：Input/output encapsulated circuit module is built, because the encapsulated circuit of transistor is mainly passive device composition,
So encapsulated circuit is passive circuit, that is, there is S11=S22, the encapsulated circuit part in packaged transistor model is considered nothing
Loss, then the modulus value quadratic sum of the loss of its network echo and insertion loss is 1, i.e., | S11|2+|S21|2=1 and | S12|2+|S22
|2=1, the relation established between frequency and S parameter using above property is completed input/output encapsulated circuit module and set up；
Step 4：Mapping network circuit is built, the present invention further adjusts model accuracy, voltage is used in model using mapping network
Control voltage source and CCCS realize that mapping network is built；
Step 5：With sample data train packaged transistor model, with direct current sample data with exchange sample data in model
Parameter adjustment, makes the DC characteristic of model and AC characteristic consistent with sample data.
2. a kind of neutral net space reflection modeling method for packaged transistor according to claim 1, its feature
It is that in step 3, the relation in input/output encapsulated circuit module between frequency and S parameter can use two methods reality
Existing, the first is realized with the neural network structure of multilayer perceptron, that is, it is frequency to be input into neuron, and output neuron is S parameter
Real part and imaginary part, its expression formula is：
Wherein fANNNeutral net mapping relations are represented, w represents neutral net inside weight, and R and I represents the real part of S parameter respectively
With imaginary part；
Realized with numerical computations for second, i.e.,
Wherein x1, x2, x3, x4Expression is Optimal Parameters, and f () represents the algebraic relation of input and output, i.e. frequency, Optimal Parameters
With the real part and the relation of imaginary part of S parameter, can be converted by the amplitude of S parameter and phase and obtained.
3. a kind of neutral net space reflection modeling method for packaged transistor according to claim 1, its feature
It is in step 4, output mapping network to be realized using CCCS, formula is
igf.dc=fANN1(vgf.dc, vdf.dc, igc.dc, idc.dc, w1) (3)
idf.dc=fANN2(vgf.dc, vdf.dc, igc.dc, idc.dc, w2) (4)
Wherein fANN1And fANN2Represent neutral net mapping relations, w1And w2Represent neutral net inside weight.
4. a kind of neutral net space reflection modeling method for packaged transistor according to claim 1, its feature
It is in step 4, input mapping network to be realized using VCVS, formula is
vgc.ac=hANN1(vgf.ac, vdf.ac, w3) (5)
vdc.ac=hANN2(vgf.ac, vdf.ac, w4) (6)
Wherein hANN1And hANN2Represent neutral net mapping relations, w3And w4Represent neutral net inside weight.
5. a kind of neutral net space reflection modeling method for packaged transistor according to claim 1, its feature
Be, in step 5, first by the input mapping network in model and output mapping network it is unitization so that ensure model not because
Introducing mapping network makes model performance be deteriorated；Then the DC characteristic of packaged transistor model is adjusted with output mapping network；Again
The AC characteristic of packaged transistor model is adjusted with input mapping network；Finally the input mapping network in model and output are reflected
Penetrate network parameter to finely tune, make the DC characteristic of model and AC characteristic and measure or emulate packaged transistor performance identical.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109241622A (en) * | 2018-09-06 | 2019-01-18 | 天津工业大学 | A kind of neural network modeling approach based on small signal knowledge type packaged transistor |
| CN111695230A (en) * | 2019-12-31 | 2020-09-22 | 天津工业大学 | Neural network space mapping multi-physics modeling method for microwave passive device |
| CN113536661A (en) * | 2021-06-15 | 2021-10-22 | 西安电子科技大学 | TFET device structure optimization and performance prediction method based on neural network |
| CN114492253A (en) * | 2022-01-20 | 2022-05-13 | 电子科技大学 | Rapid optimization method for half-space mapping of microstrip circuit in combination with Gaussian process |
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2016
- 2016-12-05 CN CN201611106417.1A patent/CN106777621A/en active Pending
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| SHUXIA YAN 等: "Neuro-Space Mapping Method for Nonlinear Device Modeling", 《PROCEEDINGS OF THE 2015 INTERNATIONAL CONFERENCE IN COMMUNICATIONS,SIGNAL PROCESSING ,AND SYSTEM》 * |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109241622A (en) * | 2018-09-06 | 2019-01-18 | 天津工业大学 | A kind of neural network modeling approach based on small signal knowledge type packaged transistor |
| CN111695230A (en) * | 2019-12-31 | 2020-09-22 | 天津工业大学 | Neural network space mapping multi-physics modeling method for microwave passive device |
| CN111695230B (en) * | 2019-12-31 | 2023-05-02 | 天津工业大学 | Neural network space mapping multi-physical modeling method for microwave passive device |
| CN113536661A (en) * | 2021-06-15 | 2021-10-22 | 西安电子科技大学 | TFET device structure optimization and performance prediction method based on neural network |
| CN113536661B (en) * | 2021-06-15 | 2022-12-13 | 西安电子科技大学 | TFET device structure optimization and performance prediction method based on neural network |
| CN114492253A (en) * | 2022-01-20 | 2022-05-13 | 电子科技大学 | Rapid optimization method for half-space mapping of microstrip circuit in combination with Gaussian process |
| CN114492253B (en) * | 2022-01-20 | 2024-05-10 | 电子科技大学 | Microstrip circuit half-space mapping rapid optimization method combined with Gaussian process |
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Application publication date: 20170531 |