CN106776442B - FPGA transistor size adjusting method - Google Patents
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- CN106776442B CN106776442B CN201611105208.5A CN201611105208A CN106776442B CN 106776442 B CN106776442 B CN 106776442B CN 201611105208 A CN201611105208 A CN 201611105208A CN 106776442 B CN106776442 B CN 106776442B
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Abstract
The invention relates to an FPGA (field programmable gate array) architecture exploration method, which combines an accurate model with a GA (genetic algorithm) algorithm and adjusts the modelAnd the size of the transistor realizes the compromise optimization of time delay and area. Therefore, the invention discloses a method for adjusting the size of an FPGA transistor, which comprises the following steps: 1) determining key parameters influencing FPGA delay; 2) establishing a corresponding Elmore delay model for each circuit; 3) combining an Elmore delay model of the FPGA with a neural network, establishing a KBNN delay model, training the KBNN delay model, and determining a training error EtAnd a verification error EvThe minimum weights Ω and Φ and the number of hidden neurons m; 4) establishing an improved minimum width transistor area model, and estimating the area of an FPGA island; 5) and the delay model, the area model and the GA algorithm are combined to realize rapid transistor size adjustment. The invention is mainly applied to FPGA design occasions.
Description
Technical Field
The invention relates to an FPGA architecture exploration method, in particular to an FPGA transistor size adjusting method.
Background
In the Field-Programmable Gate Array (FPGA) architecture exploration process, a transistor-level design tool is indispensable because it can provide accurate delay and area estimation for different architectures, thereby implementing architecture evaluation. The transistor level design includes the selection of circuit topologies for the different sub-circuits to achieve the architecture. And the transistor sizing can also improve the area, delay and power consumption of the FPGA. The design of FPGAs is a complex iterative process of transistor-level design for different architectures. Accurate delay and area models are essential to obtain correct transistor sizing results.
Currently, there are three methods that can be used to estimate the delay of an FPGA. In the first method, delay estimation is performed based on a numerical analysis model. The Elmore model is typically used to calculate the delay of an FPGA. Smith et al uses an Elmore model to obtain FPGA delay, and combines it with GP (geometrical Programming) algorithm to optimize high-level architecture parameters and transistor size simultaneously to realize area and delay compromise. The above-described analytical model-based method, although having great advantages in speed, is not highly accurate because it linearly equalizes transistors. In the second method, a complete layout is established for the FPGA circuit and a circuit simulation tool is used to determine the delay. Although the method is accurate, 6-15 hours are needed for completing one complete architecture exploration by using a circuit simulation tool HSPICE, and the time is long. In a third approach, an analytical model is combined with circuit simulation. If a two-stage method is adopted to optimize the area and the time delay, a linear model is used in the exploration stage, and a TILOS algorithm is used in the fine adjustment stage based on HSPICE to adjust the transistor size. This method is a compromise between accuracy and speed of the two methods described above. However, the use of circuit emulators still reduces the efficiency of the architecture exploration.
In order to accelerate the design process and accurately find a proper framework, the invention utilizes a Knowledge-based Neural Network (KBNN) to obtain the delay of the FPGA, utilizes an improved minimum width transistor model to obtain a corresponding area, and combines the delay and the area with a GA (genetic Algorithm) algorithm to quickly and accurately finish the transistor size adjustment. The KBNN combines the strong learning capacity provided by the neural network and the delay change trend of the established FPGA analysis model, so that the neural network and the analysis model are complementary with each other, the physical significance between problems is kept, and the relationship between parameters can be intuitively reflected. Therefore, the KBNN is used for constructing the relation between the delay and the FPGA architecture parameter and the transistor size, and the method can improve the model precision and does not obviously increase the estimation time.
Reference documents:
[1]A.M.Smith,G.A.Constantinides,P.Y.K.Cheung.FPGA architectureoptimization using geometric programming[J].Computer-Aided Design ofIntegrated Circuits and Systems.2010,29(8):1163-1176.
[2]C.Chiasson,V.Betz.COFFE:Fully-automated transistor sizing forFPGAs[C].Field-Programmable Technology(FPT),Kyoto,2013:34-41.
[3]I.Kuon,J.Rose.Exploring area and delay tradeoffs in FPGAs witharchitecture and automated transistor design[J].Very Large Scale Integration(VLSI)Systems.2011,19(1):71-84。
disclosure of Invention
To overcome the deficiencies of the prior art, the present invention is directed to a method for quickly and accurately adjusting transistor dimensions. The KBNN delay model can keep the nonlinearity of the circuit and takes account of the delay of a connecting line between logic and wiring resources which is usually ignored and the connection delay inside the multiplexer MUX and the lookup table LUT; the improved minimum width transistor area model improves accuracy by calculating the area of the NMOS and CMOS, respectively. The accurate model is combined with the GA algorithm, and the compromise optimization of time delay and area is realized by adjusting the size of the transistor. Therefore, the technical scheme adopted by the invention is that the FPGA transistor size adjusting method comprises the following steps:
1) determining key parameters influencing FPGA delay;
2) establishing a corresponding Elmore delay model for each circuit according to the influence of parameters on the delay of each sub-circuit in the FPGA;
3) combining an Elmore delay model of the FPGA with a neural network, establishing a KBNN delay model, training the KBNN delay model, and determining a training error EtAnd a verification error EvThe minimum weights Ω and Φ and the number of hidden neurons m;
4) establishing an improved minimum width transistor area model, and estimating the area of an FPGA island;
5) and the delay model, the area model and the GA algorithm are combined to realize rapid transistor size adjustment.
The key parameters refer to 8 architecture parameters, which are respectively: width W of wiring channel, number N of basic logic units in logic block, input number K of look-up table LUT, line length L, input number I of logic block, flexibility F of switch blocksNumber of routing tracks F to which the input pins of the logic block can be connectedcinNumber of routing tracks F to which the output pins of the logic block can be connectedcout(ii) a The sub-circuit delays of an FPGA can be expressed in the form of equation (1):
Tn＝fn(N,K,W,L,I,Fs,Fcin,Fcout,S1,...,Sl) (1)
wherein, TnRepresenting the delay of the FPGA sub-circuit n, 1<＝n<＝7，SiIs the transistor size of the sub-circuit n, 1<＝i<L. Switching block Elmore delay model:
wherein, Cj,SBmux1，Cj,SBmux2Junction capacitances, C, of a primary transistor and a secondary transistor in the switch block multiplexer, respectivelyg,SBdrv 1、Cg,SBdrv 2Is the gate capacitance of the transistor in the switch block buffer, Cj,SBdrv1、Cj,SBdrv2Is the junction capacitance of the transistor in the switch block buffer, Cj,CBmux1Is a transistor junction capacitor connecting the block multiplexer; the delay model for the remaining subcircuits is similar to equation (2).
The KBNN delay model structure comprises a multilayer perceptron MLP (Multi layer Perceptron) neural network and a knowledge neuron, and the input parameters in the formula (1) determine the number of input neurons in the KBNN structure. Input gamma of each hidden neuroniThe sum of the weights of the input parameters is, an activation function in a hidden neuron adopts a sigmoid function, an output neuron of a 3-layer MLP is a weighted sum of outputs of the hidden neuron, the output of the 3-layer MLP is a difference between an estimated value and a true value of delay, a knowledge neuron is an established FPGA delay model based on Elmore, and the output of KBNN is the sum of the outputs of the 3-layer MLP and the knowledge neuron;
finally, the KBNN time-delay model is trained through the following algorithm, and the training error E is determinedtAnd a verification error EvThe weight between the smallest input neuron and the hidden neuron omega and the weight between the hidden neuron and the MLP output neuron phi and the number of hidden neurons m.
The invention has the characteristics and beneficial effects that:
1. compared with the traditional transistor size adjusting method based on HSPICE, the transistor size adjusting method can quickly finish the transistor size adjustment under the condition of a large number of iterations, not only can the parameters influencing the time delay be comprehensively considered, but also the relation between each parameter and the time delay is more intuitively reflected, and the obtained result can be applied to a framework exploration tool.
2. By utilizing the knowledge-based neural network, the training data volume is reduced, and meanwhile, the nonlinear relation in the FPGA delay is kept, so that the result is more accurate.
Description of the drawings:
FIG. 1 illustrates the effect of architectural parameters on latency.
FIG. 2 is a transistor level structure and equivalent RC model of a switch block in an FPGA sub-circuit.
Fig. 3 is a neural network structure of the delay model.
Fig. 4 is a minimum width transistor area model.
Detailed Description
The invention provides a method for accurately adjusting the size of a transistor, which can quickly find a result meeting a design target under the requirement of a large number of design iterations, and the finally obtained optimization result can be applied to a framework exploration tool to accelerate the framework exploration process. The specific technical scheme is as follows:
1) and determining key parameters influencing the FPGA delay.
2) And establishing a corresponding Elmore delay model for each circuit according to the influence of parameters on the delay of each sub-circuit in the FPGA.
3) Combining an Elmore delay model of the FPGA with a neural network, establishing a KBNN delay model, training the KBNN delay model, and determining a training error EtAnd a verification error EvThe minimum weights Ω and Φ and the number of hidden neurons m.
4) And establishing an improved minimum width transistor area model and estimating the area of the FPGA island.
5) And the delay model, the area model and the GA algorithm are combined to realize rapid transistor size adjustment.
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The following description will take the connection block in the FPGA sub-circuit as an example.
1. Determining key parameters affecting FPGA delay
In order to explain that the change of the architecture parameters can influence the time delay of each sub-circuit in the FPGA, the invention utilizes HSPICE to carry out a series of experiments on a connecting block in the FPGA, under the condition of keeping the process parameters unchanged, the values of 8 architecture parameters are sequentially changed, the change of the time delay is observed, and the result is as shown in figure 1Shown in the figure. As can be seen from the figure, the delay of the connection block varies significantly with the variation of the architecture parameter, so the influence of 8 architecture parameters on each sub-circuit is fully considered in the delay model, that is, each sub-circuit has 8 input parameters. Wherein, 8 architectural parameters are respectively: width W of wiring channel, number N of basic logic units in logic block, input number K of look-up table LUT, line length L, input number I of logic block, flexibility F of switch blocksNumber of routing tracks F to which the input pins of the logic block can be connectedcinNumber of routing tracks F to which the output pins of the logic block can be connectedcout。
Each transistor in the FPGA circuit can be equivalent to an RC network, and the resistance and capacitance in the transistor are related to the transistor size, which in turn affects the delay. Furthermore, to achieve transistor sizing, transistor size is used as part of the delay model input parameters. Therefore, the sub-circuit delays of the FPGA can be expressed in the form of equation (1).
Tn＝fn(N,K,W,L,I,Fs,Fcin,Fcout,S1,...,Sl) (1)
Wherein, TnRepresenting the delay of the FPGA sub-circuit n (1)<＝n<＝7)，Si(1<＝i<I.e. l) are the transistor sizes of the sub-circuit n, the number of transistors is different for different sub-circuits, i.e. the number of input parameters of the delay model is different for different sub-circuits.
2. Establishing Elmore delay model for each sub-circuit of FPGA
All subcircuits in the FPGA are made of transistors, which can be modeled using the Elmore model. Due to space limitations, the invention takes a switch block as an example for analysis, the delays of other sub-circuits can be obtained by a similar method, and the transistor model and the equivalent RC network of the switch block are shown in FIG. 2. The switch block includes a switch block buffer and a two-stage multiplexer.
The time delay of the switch block can be obtained by calculating the formula (2)
Wherein, Cj,SBmux1，Cj,SBmux2Junction capacitances, C, of a primary transistor and a secondary transistor in the switch block multiplexer, respectivelyg,SBdrv 1，Cg,SBdrv 2(Cj,SBdrv1,Cj,SBdrv2) Is the gate capacitance (junction capacitance) of the transistor in the switch block buffer, Cj,CBmux1Is a transistor junction capacitance connecting the block multiplexer.
3. Establishing KBNN delay model
The structure of KBNN is shown in FIG. 3, and includes a Multilayer Perceptron (MLP) neural network and a knowledge neuron. The input parameters in equation (1) determine the number of input neurons in the KBNN structure. Input gamma of each hidden neuroniIs the weighted sum of these input parameters. The activation function in the hidden neuron adopts a sigmoid function. The output neuron of the 3-layer MLP is a weighted sum of the hidden neuron outputs. The output of the 3-layer MLP is the difference between the estimated value of the delay and the true value. The knowledge neuron is an established FPGA delay model based on Elmore. The output of KBNN is the sum of the outputs of the 3-layer MLP and the knowledge neurons.
Finally, the KBNN time-delay model is trained through the following algorithm, and the training error E is determinedtAnd a verification error EvThe weight between the smallest input neuron and the hidden neuron omega and the weight between the hidden neuron and the MLP output neuron phi and the number of hidden neurons m.
4. Establishing minimum width transistor area model
The minimum width transistor area model is shown in fig. 4, which is defined as the smallest accessible transistor under a particular process technology, the area being the sum of the area of the transistor itself and the space adjacent to it.
The present invention will use an improved version of the minimum width transistor area model. And (3) calculating the area of the NMOS transistor by using a formula (3), and calculating the area of the CMOS by using a formula (4) so as to realize the purpose of reducing the area by inserting the PMOS transistor into the N-well space. Where x is the drive strength of the transistor.
5. Transistor size adjusting method
As shown in formula (5), the optimization target is that the product of the delay T and the area a of the FPGA island is minimum, and the weight of the delay and the area is determined by adjusting the weight α, Si(1<＝i<L) is the size of each transistor in the circuit.
minimize Tα(S1,S2...Sl)×A1-α(S1,S2...Sl) (5)
Since the GA algorithm can solve various optimization problems and can be quickly implemented in the present invention. Therefore, the time delay model, the area model and the GA algorithm are combined, and the transistor size adjustment result is obtained quickly and accurately. Finally, the speed of the architecture exploration by using the method is improved by nearly 2863 times compared with the method based on HSPICE, and the error is less than 3 percent.
Claims (1)
1. A method for adjusting the size of an FPGA transistor is characterized by comprising the following steps:
1) determining key parameters influencing FPGA delay;
2) establishing a corresponding Elmore delay model for each circuit according to the influence of parameters on the delay of each sub-circuit in the FPGA;
3) combining an Elmore delay model of the FPGA with a neural network, establishing a KBNN delay model, training the KBNN delay model, and determining a training error EtAnd a verification error EvThe weight omega between the minimum input neuron and the hidden neuron, the weight phi between the hidden neuron and the MLP output neuron and the number m of the hidden neurons are calculated;
4) establishing an improved minimum width transistor area model, and estimating the area of an FPGA island;
the minimum width transistor area is defined as the minimum accessible transistor under a specific process technology, the area is the sum of the area of the transistor and the space adjacent to the transistor, the area of the NMOS transistor is calculated by using a formula (3), and the area of the CMOS transistor is calculated by using a formula (4):
wherein x is the drive strength of the transistor;
5) utilizing the KBNN delay model in the step 3), the area model in the step 4) and a GA algorithm represented by the following formula:
minimize Tα(S1,S2...Sl)×A1-α(S1,S2...Sl)
the optimization target is that the product of the delay T and the area A of the FPGA island is minimum, the emphasis on the delay and the area is determined by adjusting the weight alpha, Si is the size of each transistor in the circuit, and 1< ═ i < ═ l, so that the size adjustment of the transistors can be realized quickly;
the key parameters refer to 8 architecture parameters, which are respectively: width W of wiring channel, number N of basic logic units in logic block, input number K of look-up table LUT, line length L, input number I of logic block, flexibility F of switch blocksNumber of routing tracks F to which the input pins of the logic block can be connectedcinNumber of routing tracks F to which the output pins of the logic block can be connectedcout(ii) a The sub-circuit delay of the FPGA is represented in the form of equation (1):
Tn＝fn(N,K,W,L,I,Fs,Fcin,Fcout,S1,...,Sl) (1)
wherein, TnRepresenting the delay of the FPGA sub-circuit n, 1<＝n<＝7，SiIs the transistor size of the sub-circuit n;
switching block Elmore delay model:
TSB＝RSBdrv2*(Cj,SBdrv2+Fs*Cj,SBmux1+Fcin*0.5*I*Cj,CBmux1)+(RSBdrv2+Rj,SBmux1)*(Cj,SBmux1+Cj,SBmux2)+(RSBdrv2+Rj,CBmux1+Rj,CBmux2)*(Cj,SBmux2+Cg,SBdrv1)+0.69*RSBdrv1*(Cj,SBdrv1+Cg,SBdrv2) (2)
wherein, Cj,SBmux1，Cj,SBmux2Junction capacitances, C, of a primary transistor and a secondary transistor in the switch block multiplexer, respectivelyg,SBdrv1、Cg,SBdrv2Is the gate capacitance of the transistor in the switch block buffer, Cj,SBdrv1、Cj,SBdrv2Is the junction capacitance of the transistor in the switch block buffer, Cj,CBmux1Is the transistor junction capacitance of the connecting block multiplexer:
the KBNN time-delay model structure comprises a multilayer perceptron MLP (Multi layer Perceptron) neural network and a knowledge neuron, the input parameter in the formula (1) determines the number of input neurons in the KBNN structure, and the input gamma of each hidden neuroniThe sum of the weights of the input parameters is adopted as an activation function in the hidden neurons, the sigmoid function is adopted as an output neuron of the 3-layer MLP, the weighted sum of the output of the hidden neurons is adopted as the output of the 3-layer MLP, the output of the 3-layer MLP is the difference between an estimated value and a real value of delay, the knowledge neuron is an established FPGA delay model based on Elmore, and the output of KBNN is the sum of the output of the 3-layer MLP and the knowledge neuron.
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