CN106773957A - It is a kind of be applied to airborne radar countermeasure system detect receipts beam steering system and method - Google Patents
It is a kind of be applied to airborne radar countermeasure system detect receipts beam steering system and method Download PDFInfo
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- CN106773957A CN106773957A CN201611165128.9A CN201611165128A CN106773957A CN 106773957 A CN106773957 A CN 106773957A CN 201611165128 A CN201611165128 A CN 201611165128A CN 106773957 A CN106773957 A CN 106773957A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/021—Auxiliary means for detecting or identifying radar signals or the like, e.g. radar jamming signals
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- Computer Networks & Wireless Communication (AREA)
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Abstract
The invention discloses it is a kind of be applied to airborne radar countermeasure system detect receipts beam steering system and method.Detecing receipts beam steering system includes central beam control unit, multiple front Beamsteering Units multigroup unit block corresponding with multiple front Beamsteering Units.Every group of unit block includes weighting amplifying unit, beam selection switch element, compensation amplifying unit.The central beam control unit obtains the control instruction in the mster-control centre from airborne radar countermeasure system, and packing treatment is carried out to control instruction and data by regulation agreement, and the control instruction and data after packing are distributed into corresponding front Beamsteering Unit.The front Beamsteering Unit for being connected to distribution command sends wave beam selecting switch order to corresponding beam selection switch element, simultaneously, amplitude weighting code and phase compensation code are sent respectively to corresponding weighting amplifying unit and corresponding compensation amplifying unit, for compensating amplification to the wave beam for receiving.
Description
Technical field
Receipts beam steering system is detectd the present invention relates to one kind and its detect receipts beam-steering methods, more particularly to one kind is applied to
Detecing for airborne radar countermeasure system is received beam steering system and its detects receipts beam-steering methods.
Background technology
Radar countermeasure systems in the case where receipts pattern is detectd, realize receiving multi-beam shape by antenna array combination multiple beam forming network unit
Into the signal that system detects the different ripples positions of receipts need to only be scheduled to multi-beam, you can realize quick quickly beam scanning.Wave beam
Another direction quickly is swept to from a direction, produces multiple independent wave beams, or the single wave beam of rapid translating to watch many
Individual target.These are required for quickly being scheduled to detecing receipts wave beam, and beam position is needed into the region of scanning or tracking is needed
Target.
The PC-104 computer modules of the beam control scheme mainly industrial control field that current countermeasure system is used+
Fpga chip framework, PC-104 modules are to dock to be electrically connected with module by base plate, in airborne circumstance high vibration magnitude
Under environment, there is the hidden danger of loose contact in the framework, it is impossible to meet the requirement of system high reliability.Meanwhile, in order to as many as possible
Intercepting and capturing target radar signal, detection equipment generally needs the 360 degrees omnidirection to carry out wave beam control, for the simplification of control, leads to
Big front is often divided into the treatment of several submatrixs, instruction is distributed to each submatrix wave beam control by a central beam control unit
Unit processed, meanwhile, central beam control unit design can with design sameization, the modularization of submatrix Beamsteering Unit,
Simplify system design, be easy to system to expand.Traditional ripple control instruction and data is by electric signal transmission to each submatrix, electric signal
Under airborne bad electromagnetic environment, easily disturbed by airborne electromagnetic environment high, and communication link is more long, and the weight of cable is got over
Weight.In order to shorten the weight of cloth phase time and mitigation transmission cable to sub- front antenna, data are controlled using optical fiber
The transmission of stream.Power PC Processor possesses the advantage for being usually embedded formula system high reliability, and FPGA is used as the special integrated electricity of one kind
Road, solves the deficiency of custom circuit, the limited shortcoming of original programming device gate circuit number amount is overcome again, with system knot
Structure and logic unit is flexible, integrated level high and the features such as the scope of application wide.The radar electronic warfare system that PowerPC and FPGA is combined
System detects receipts beam steering system and can make full use of the high-performance treatments ability of PowerPC and the custom circuit design energy of FPGA
Power, while taking into account the factors such as power consumption, cost, design cycle, is small to volume requirement, load request is light, computing capability requirement is high
Radar countermeasure systems detect receive beam steering system effective workaround.In circuit design, from Freescale companies
QorlQ P2020 are main control chip, the parameters of system are configured, because system will be entered with multiple working cells of countermeasure system
Row data interaction, in order to reduce the species of interface chip, the linking of line interface is entered using FPGA.
The content of the invention
In view of the technical problem of above-mentioned fast wave beam control, the present invention provides a kind of airborne radar countermeasure system that is applied to
Detect receipts beam steering system and its detect receipts beam-steering methods.
Solution of the invention is：It is a kind of be applied to airborne radar countermeasure system detect receipts beam steering system, its bag
Include central beam control unit, multiple front Beamsteering Units multigroup list corresponding with multiple front Beamsteering Units
First component；Every group of unit block includes weighting amplifying unit, beam selection switch element, compensation amplifying unit；The central beam
Control unit obtains the control instruction in the mster-control centre from airborne radar countermeasure system, by regulation agreement to control instruction and
Data carry out packing treatment, and the control instruction and data after packing are distributed into corresponding front Beamsteering Unit；It is connected to point
The front Beamsteering Unit for saying the word sends the order of wave beam selecting switch to corresponding beam selection switch element, meanwhile, will
Amplitude weighting code and phase compensation code are sent respectively to corresponding weighting amplifying unit and corresponding compensation amplifying unit, for right
The wave beam of reception compensates amplification；
Wherein, the central beam control unit includes PowerPC modules, FPGA module；PowerPC modules are cardiac waves in this
The core devices of beam control unit, on the one hand, PowerPC modules receive the control instruction and data that mster-control centre sends, separately
On the one hand, after PowerPC modules are parsed to the control instruction, the control of each front Beamsteering Unit will be corresponded to
Instruction and data processed passes to FPGA module, and FPGA module is packed by the agreement of regulation to control instruction and data.
Used as the further improvement of such scheme, the central beam control unit resists system by network with the airborne radar
Mster-control centre's communication of system, the central beam control unit is communicated by optical fiber with each front Beamsteering Unit, the battle array
Face Beamsteering Unit sends corresponding beam selection switch command to corresponding beam selection switch element by serial port protocol.
Used as the further improvement of such scheme, every group of unit block is also including the ripple to corresponding front Beamsteering Unit
The positive unit of self calibration of Shu Jinhang self-inspections correction.
Used as the further improvement of such scheme, the central beam control unit also includes that DDR3 memory modules, FLASH are deposited
Storage module, two temperature monitoring modules, CPLD configuration modules, optic module, RS232 serial port modules, RS422 serial port modules, when
Clock module, 10M/100M Ethernet interface modules；PowerPC modules and FPGA module, DDR3 memory modules, FLASH memory modules,
Temperature monitoring module A, CPLD configuration module, the interconnection of 10M/100M Ethernet interfaces module；FPGA module also with optic module,
RS232 serial port modules, RS422 serial port modules, FLASH memory modules, temperature monitoring module B interconnection；Clock module is PowerPC
Module provides clock with FPGA module.
Further, the data that FPGA module will be received switch to optical signal by optic module, are passed to by optical fiber
Each front Beamsteering Unit；Meanwhile, FPGA module complete UART controller, parallel port controller, DDR3SDRAM controllers and
The function of FLASH controller.
Further, the production method of clock needed for each functional module of system, clock module comes with 4 crystal oscillators, frequency
Respectively 25MHz, 100MHz, 14.7456MHz, 33MHz, wherein, after 25M clocks drive IDT2305NZ through oversampling clock, directly
25M clocks are provided to CPLD configuration modules and 10M/100M Ethernet interfaces module, meanwhile, clock drives 2 road clocks of output, defeated
Enter to 2 clock generator CDCM61004RHBT, wherein a piece of generation 125M differential clocks, are FPGA module and PowerPC moulds
The SRIO of block provides work clock, and a piece of generation 156.25M differential clocks are supplied to FPGA high speed GTX in addition, are used to send number
According to front Beamsteering Unit；100M crystal oscillator clocks access PowerPC modules after IDT2305NZ is driven through oversampling clock, use
To provide the 100M clocks of the LocalBus agreements that communicated between PowerPC modules and FPGA module, 14.7456MHz is supplied to
FPGA module is used to the asynchronous serial communication of RS232 serial port modules, and 33MHz crystal oscillators work to FPGA module and back up.
Further, 2 DDR3 address wires are connected to the identical of PowerPC modules by the circuit design of DDR3 memory modules
Address pipe leg, so that 16 bit wides are expanded into 32 bit data widths；The reset transistor leg RESET# of DDR3 memory modules accesses CPLD
Configuration module, to be resetted during electricity in DDR3 initialization.
Further, the controller production method of FLASH memory modules：Select corresponding according to FLASH memory modules
The IP types of nuclear of FPGA module, after determining parameter, is compiled.
Further, FPGA module is input to configuration CPLD by the configurable clock generator FPGA_CFG_CCLK that fpga chip is produced
Configuration module, while FPGA module and FLASH memory modules are interconnected using 16 position datawires and 26 bit address lines, based on and configure
Pattern.
Used as the further improvement of such scheme, this is detectd receipts beam-steering methods and comprises the following steps：
The central beam control unit obtains the control instruction in the mster-control centre from airborne radar countermeasure system；
The central beam control unit carries out packing treatment by regulation agreement to control command and data, or the control is referred to
Order and data are distributed to corresponding front Beamsteering Unit；
The front Beamsteering Unit transmission wave beam selecting switch order for being connected to distribution command is opened to corresponding beam selection
Close unit；
Amplitude weighting code and phase compensation code are sent respectively to correspondence by the front Beamsteering Unit for being connected to distribution command
Weighting amplifying unit and corresponding compensation amplifying unit, for receive wave beam compensate amplification.
The present invention enables to radar countermeasure systems antenna beam control module, while making the raising of module integrated level, body
Product reduces, weight saving, and the reliability to improving equipment is extremely beneficial to, and may advantageously facilitate the development of airborne radar countermeasure system.
Brief description of the drawings
Fig. 1 is that the present invention detects the application block diagram for receiving beam steering system；
Fig. 2 is the hardware block diagram that the central beam control unit for receiving beam steering system is detectd in Fig. 1；
Fig. 3 is the timing topology tree of central beam control unit in Fig. 2；
Fig. 4 is all kinds of power supply architecture trees of central beam control unit in Fig. 2；
Fig. 5 is the circuit theory diagrams of the DDR3 memory modules of central beam control unit in Fig. 2；
Fig. 6 is LocalBus interface circuits between the PowerPC modules of central beam control unit in Fig. 2 and FPGA module
Schematic diagram；
Fig. 7 is the DC/DC power-switching circuit schematic diagrams of central beam control unit in Fig. 2；
Fig. 8 is the BPI configuration circuit schematic diagrams of the FPGA module of central beam control unit in Fig. 2；
Fig. 9 is the configuration circuit schematic diagram of the PowerPC modules of central beam control unit in Fig. 2；
Figure 10 is the P2020JTAG interface circuit schematic diagrams of the PowerPC modules of central beam control unit in Fig. 2；
Figure 11 is the interface circuit schematic diagram of the RS232 serial port modules of central beam control unit in Fig. 2；
Figure 12 is the interface circuit schematic diagram of the RS422 serial port modules of central beam control unit in Fig. 2；
Figure 13 is the serial communication protocol information format of central beam control unit in Fig. 2.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Fig. 1 is that the present invention detects the application block diagram for receiving beam steering system, of the invention in Fig. 1 to be applied to airborne radar pair
The receipts beam steering system of detecing of anti-system includes central beam control unit, multiple front Beamsteering Units and multiple fronts
The corresponding multigroup unit block of Beamsteering Unit.
Every group of unit block includes weighting amplifying unit, beam selection switch element, compensation amplifying unit.Master control on machine
Center is that control instruction and data are sent to central beam control by the mster-control centre of airborne radar countermeasure system by network
Unit, after central beam control unit is processed instruction and data, the control data for corresponding to respective scanning angle is led to
Cross optical fiber and be distributed to respective front i.e. front Beamsteering Unit, different front is by beam selection data is activation to beam selection
Switch element, is used to select each switch beam, while the decay code and phase shift code of wave beam are sent into weighting amplifies single
Unit and compensation amplifying unit, are used to carry out width and mutually compensate to receiving wave beam.
Referring to Fig. 2, central beam control unit of the present invention and front Beamsteering Unit carry out United design, are easy to set
Standby modularization, ripple control unit be central beam control unit it is main by PowerPC modules (main using PowerPC P2020),
FPGA module (mainly using fpga chip), DDR3 memory modules, FLASH memory modules, two temperature monitoring modules, CPLD match somebody with somebody
Put module, power module, optic module, RS232 serial port modules, RS422 serial port modules, clock module, 10M/100M Ethernets
Mouth mold block etc. is constituted.
Referring to Fig. 3, the clock tree construction of central beam control unit of the present invention, module comes with 4 crystal oscillators, frequency difference
It is 25MHz, 100MHz, 14.7456MHz, 33MHz, wherein, after 25M clocks drive IDT2305NZ through oversampling clock, directly to
CPLD configuration modules (hereinafter referred to as CPLD) and network PHY (i.e. the main element of 10M/100M Ethernet interfaces module) provide 25M
Clock, meanwhile, clock drives 2 road clocks of output, is input into 2 clock generator CDCM61004RHBT, wherein a piece of generation
125M differential clocks, for the SRIO of FPGA module and PowerPC modules provides work clock, a piece of generation 156.25M is poor in addition
Timesharing clock is supplied to FPGA module (hereinafter referred to as FPGA) high speed GTX, is used to send data to front Beamsteering Unit.100M
Crystal oscillator clock accesses P2020 (hereinafter referred to as PowerPC modules) after IDT2305NZ is driven through oversampling clock, is used to provide
The 100M clocks of the LocalBus agreements that communicated between P2020 and FPGA, 14.7456MHz is supplied to FPGA to be used to the asynchronous strings of RS232
Mouth (i.e. RS232 serial port modules) communication.33MHz crystal oscillators work to FPGA and back up.
Referring to Fig. 4, this is the power supply architecture tree of ripple control unit, and input power is 12V, by 4 DCDC chips LTM4616
3.3V, 5.0V, 1.0V, 1.2V, 1.05V, 1.8V, 2.5V, 1.5V are produced respectively.3.3V be supplied to CPLD, optic module, with
And 422 and 232 interface level chips；5.0V is supplied to TTL interface chips；1.0V is supplied to FPGA kernels and high-speed module；
1.2V is supplied to FPGA high-speed module reference voltages；1.8V is supplied to FLASH and FPGA boost voltages；1.05V is supplied to P2020
Kernel and ethernet PHY chip；2.5V is supplied to ethernet PHY chip；1.5V is supplied to the DDR3 of P2020 and FPGA.
It is the DDR3SDRAM i.e. circuit theory diagrams of DDR3 memory modules referring to Fig. 5, U2, U3 are DDR3 storage chips
MT41K128M16, the data width that monolithic storage chip is provided is 16bits, therefore, 2 DDR3 address wires are connected to P2020
Identical address pipe leg, 16 bit wides are just expanded into 32 bit data widths.DDR3 reset transistor legs RESET# accesses CPLD, so as to first
Beginningization is resetted when upper electric.Chip pipe leg VREFCA and VERFDQ is connected into 1.5V electric power networks by capacitor filtering.Bank ground
Location input pipe leg BA0~BA2 two panels chip is connected to identical FPGA pipe legs, and differential clocks pipe leg CK, CK# introduce clock and drive
The difference 100M clocks of IDT2305NZ outputs, RAS#, CAS#, WE# select control signal for read-write piece, access FPGA.
It is the Localbus bus circuit schematic diagrams between P2020 and FPGA referring to Fig. 6.By 32 bit address of P2020/
Data-reusing line is connected to 32 pipe legs of FPGA, meanwhile, control port writes enable, reads to enable and piece choosing is enabled and also accesses FPGA
Corresponding pipe leg.
It is VDD1V0 and VDD1V0_MGT power supply LTM4616 circuit theory diagrams referring to Fig. 7, PGOOD1 is that 1.0V is exported just
Normal pipe leg, the external LEDs of PGOOD1, LED positive pole is pulled to 3.3V by 470 Ohmic resistances, if voltage output is normal,
LED light is bright.
Referring to Fig. 8, fpga chip BPI configuration circuit schematic diagrams.U39 is configuration device JS28F00AP30BFA, by FPGA
The configurable clock generator FPGA_CFG_CCLK that chip is produced is input to configuration device U39, while FPGA and FLASH configuration chips have 16
Position datawire and 26 bit address lines are interconnected, it can thus be appreciated that based on and configuration mode；Other control pipe legs, enable pipe leg OE, piece choosing
Pipe leg CE, writes enable WE, reset signal RST and accesses the corresponding pipe legs of FPGA.
Referring to Fig. 9, Figure 10, the configuration circuit schematic diagram and P2020JTAG schematic diagrams of P2020.
Referring to Figure 11, U69 is RS232 electrical level transferring chip MAX3232, is 2 to enter 2 and go out, and FPGA is by efferent duct leg by number
Amplify according to being sent to compensation according to serial port protocol, while the MAX3232 pipes leg for connecting FPGA ends need to be pulled upward to by 4.7K ohm
3.3V voltages.
Referring to Figure 12, U48 is that RS422 receives electrical level transferring chip, and U55 is RS422 transmission level conversion chips.FPGA sends out
Send data to the A ends of U55, via conversion produce a pair of differential signals of Tx+ and Tx-, Y be Tx+ ends, plus 1K Europe pull-up resistor, Z
Add the pull down resistor in 10K Europe for Tx- ends, and for receiving chip, external input accesses RX+ the and RX- ports of U48, two ends
Need to increase the build-out resistor in 100 Europe between mouthful, RX+ ends add 1K ohm of pull-up resistor, and RX- ends add 10K ohm of drop-down electricity
Resistance, completes the rational Design on Plane of whole serial port circuit.
Referring to Figure 13, substation Beamsteering Unit is switched with beam selection and weighting is amplified, and compensates the serial ports between amplifying
Communication protocol information form, using two 0FFH bytes as the start information of structure, the 3rd byte is the word length of protocol data,
4th byte is function number, and function Unified number, each function number is unique, each function distribution one in system
Individual unique function number, since the 5th byte for transmission instruction and data content, the quantity of content byte determines length
Degree parameter；Check and=- (length+function number+content 1+ ...+content i).Designed based on more than, this detects receipts beam-steering methods
Following steps can be realized：The central beam control unit obtains the control in the mster-control centre from airborne radar countermeasure system
Order；The central beam control unit implements the control being adapted with the control command, or the control command is distributed at least
One front Beamsteering Unit；The front Beamsteering Unit for being connected to distribution command sends the order of wave beam selecting switch to right
The beam selection switch element answered；The front Beamsteering Unit of distribution command is connected to also by amplitude weighting code and phase compensation code
Corresponding weighting amplifying unit and corresponding compensation amplifying unit are sent respectively to, are put for being compensated to the wave beam for receiving
Greatly.
The radar countermeasure systems that PowerPC and FPGA is combined are detectd into receipts beam steering system can make full use of PowerPC
High-performance treatments ability and FPGA custom circuit designed capacity, while taking into account the factors such as power consumption, cost, design cycle, be
The radar countermeasure systems that, weight demands small to volume requirement are light, computing capability requirement is high detect the effective solution for receiving beam steering system
Certainly method.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Any modification, equivalent and improvement made within god and principle etc., should be included within the scope of the present invention.
Claims (10)
1. it is a kind of be applied to airborne radar countermeasure system detect receipts beam steering system, it is characterised in that：It includes central beam
Control unit, multiple front Beamsteering Units multigroup unit block corresponding with multiple front Beamsteering Units；Every group
Unit block includes weighting amplifying unit, beam selection switch element, compensation amplifying unit；The central beam control unit is obtained
The control instruction in the mster-control centre from airborne radar countermeasure system, packs by regulation agreement to control instruction and data
Treatment, or the control instruction and data are distributed to corresponding front Beamsteering Unit；It is connected to the front wave beam of distribution command
Control unit sends the order of wave beam selecting switch to corresponding beam selection switch element, meanwhile, by amplitude weighting code and phase
Compensation codes are sent respectively to corresponding weighting amplifying unit and corresponding compensation amplifying unit, for being mended to the wave beam for receiving
Repay amplification；
Wherein, the central beam control unit includes PowerPC modules, FPGA module；PowerPC modules are the central beam controls
The core devices of unit processed, on the one hand, PowerPC modules receive the control instruction and data that mster-control centre sends, the opposing party
Face, after PowerPC modules are parsed to the control instruction, the control for corresponding to each front Beamsteering Unit is referred to
Order and data pass to FPGA module, and FPGA module is packed by the agreement of regulation to control instruction and data.
2. be applied to airborne radar countermeasure system as claimed in claim 1 detects receipts beam steering system, it is characterised in that：Should
Central beam control unit is communicated by network with the mster-control centre of the airborne radar countermeasure system, and central beam control is single
Unit is communicated by optical fiber with each front Beamsteering Unit, and the front Beamsteering Unit sends corresponding by serial port protocol
Beam selection switch command is to corresponding beam selection switch element.
3. be applied to airborne radar countermeasure system as claimed in claim 1 detects receipts beam steering system, it is characterised in that：Often
Group unit block also includes carrying out the wave beam of corresponding front Beamsteering Unit the positive unit of self calibration of self-inspection correction.
4. be applied to airborne radar countermeasure system as claimed in claim 1 detects receipts beam steering system, it is characterised in that：Should
Central beam control unit also includes DDR3 memory modules, FLASH memory modules, two temperature monitoring modules, CPLD configuration moulds
Block, optic module, RS232 serial port modules, RS422 serial port modules, clock module, 10M/100M Ethernet interface modules；PowerPC
Module and FPGA module, DDR3 memory modules, FLASH memory modules, temperature monitoring module A, CPLD configuration module, 10M/100M
Ethernet interface module is interconnected；FPGA module also stores mould with optic module, RS232 serial port modules, RS422 serial port modules, FLASH
Block, temperature monitoring module B interconnection；Clock module is that PowerPC modules and FPGA module provide clock.
5. be applied to airborne radar countermeasure system as claimed in claim 4 detects receipts beam steering system, it is characterised in that：
The data that FPGA module will be received switch to optical signal by optic module, and passing to each front wave beam by optical fiber controls list
Unit；Meanwhile, FPGA module completes the function of UART controller, parallel port controller, DDR3SDRAM controllers and FLASH controller.
6. be applied to airborne radar countermeasure system as claimed in claim 4 detects receipts beam steering system, it is characterised in that：System
Unite the production method of clock needed for each functional module, clock module comes with 4 crystal oscillators, frequency be respectively 25MHz, 100MHz,
14.7456MHz, 33MHz, wherein, after 25M clocks drive IDT2305NZ through oversampling clock, directly to CPLD configuration modules and 10M/
100M Ethernet interfaces module provides 25M clocks, meanwhile, clock drives 2 road clocks of output, input to 2 clock generators
CDCM61004RHBT, wherein a piece of generation 125M differential clocks, for the SRIO of FPGA module and PowerPC modules provides work
Clock, in addition a piece of generation 156.25M differential clocks be supplied to FPGA high speed GTX, be used to send data to the control of front wave beam
Unit；100M crystal oscillator clocks access PowerPC modules after IDT2305NZ is driven through oversampling clock, are used to provide PowerPC moulds
The 100M clocks of the LocalBus agreements that communicated between block and FPGA module, 14.7456MHz is supplied to FPGA module to be used to RS232
The asynchronous serial communication of serial port module, 33MHz crystal oscillators work to FPGA module and back up.
7. be applied to airborne radar countermeasure system as claimed in claim 4 detects receipts beam steering system, it is characterised in that：
The circuit design of DDR3 memory modules, 2 DDR3 address wires are connected to the identical address pipe leg of PowerPC modules, so as to by 16
Bit wide expands to 32 bit data widths；The reset transistor leg RESET# of DDR3 memory modules accesses CPLD configuration modules, so as to DDR3
Resetted during electricity in initialization.
8. be applied to airborne radar countermeasure system as claimed in claim 4 detects receipts beam steering system, it is characterised in that：
The controller production method of FLASH memory modules：The IP types of nuclear of corresponding FPGA module is selected according to FLASH memory modules,
After determining parameter, it is compiled.
9. be applied to airborne radar countermeasure system as claimed in claim 4 detects receipts beam steering system, it is characterised in that：
FPGA module is input to configuration CPLD configuration modules by the configurable clock generator FPGA_CFG_CCLK that fpga chip is produced, while FPGA
Module and FLASH memory modules are interconnected using 16 position datawires and 26 bit address lines, based on and configuration mode.
10. a kind of receipts wave beam of detecing for being applied to airborne radar countermeasure system as in one of claimed in any of claims 1 to 9 is controlled
System detects receipts beam-steering methods, it is characterised in that：This is detectd receipts beam-steering methods and comprises the following steps：
The central beam control unit obtains the control instruction in the mster-control centre from airborne radar countermeasure system；
The central beam control unit carries out packing treatment by regulation agreement to control instruction and data, and the control after packing is referred to
Order and data are distributed to corresponding front Beamsteering Unit；
The front Beamsteering Unit for being connected to distribution command sends wave beam selecting switch order to corresponding beam selection switch list
Unit；
Amplitude weighting code and phase compensation code are sent respectively to corresponding adding by the front Beamsteering Unit for being connected to distribution command
Power amplifying unit and corresponding compensation amplifying unit, for compensating amplification to the wave beam for receiving.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108267720A (en) * | 2018-01-31 | 2018-07-10 | 中国电子科技集团公司第三十八研究所 | For multi-beam selecting switch while multiple target Search/Track and dispatching method |
| CN109541550A (en) * | 2018-11-29 | 2019-03-29 | 成都锐芯盛通电子科技有限公司 | A kind of method of phased array antenna fast beam switching |
| CN112241281A (en) * | 2020-10-14 | 2021-01-19 | 四川九洲空管科技有限责任公司 | Digital radar TR component FPGA program batch upgrading method and system |
| CN112256313A (en) * | 2020-10-14 | 2021-01-22 | 四川九洲空管科技有限责任公司 | Method and system for managing FPGA (field programmable Gate array) program remote upgrading system of secondary radar equipment |
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| CN108267720A (en) * | 2018-01-31 | 2018-07-10 | 中国电子科技集团公司第三十八研究所 | For multi-beam selecting switch while multiple target Search/Track and dispatching method |
| CN108267720B (en) * | 2018-01-31 | 2021-08-13 | 中国电子科技集团公司第三十八研究所 | Simultaneous multi-beam selection switch for multi-target search and tracking and scheduling method |
| CN109541550A (en) * | 2018-11-29 | 2019-03-29 | 成都锐芯盛通电子科技有限公司 | A kind of method of phased array antenna fast beam switching |
| CN112241281A (en) * | 2020-10-14 | 2021-01-19 | 四川九洲空管科技有限责任公司 | Digital radar TR component FPGA program batch upgrading method and system |
| CN112256313A (en) * | 2020-10-14 | 2021-01-22 | 四川九洲空管科技有限责任公司 | Method and system for managing FPGA (field programmable Gate array) program remote upgrading system of secondary radar equipment |
| CN112241281B (en) * | 2020-10-14 | 2024-02-06 | 四川九洲空管科技有限责任公司 | Batch upgrading method and system for digital radar TR (transmitter/receiver) module FPGA (field programmable Gate array) program |
| CN112256313B (en) * | 2020-10-14 | 2024-04-30 | 四川九洲空管科技有限责任公司 | Secondary radar equipment FPGA program remote upgrading system management method and system |
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