CN106767921A - A kind of implementation method for fibre optic gyroscope test circuit FPGA - Google Patents
A kind of implementation method for fibre optic gyroscope test circuit FPGA Download PDFInfo
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- CN106767921A CN106767921A CN201611179366.5A CN201611179366A CN106767921A CN 106767921 A CN106767921 A CN 106767921A CN 201611179366 A CN201611179366 A CN 201611179366A CN 106767921 A CN106767921 A CN 106767921A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C25/00—Manufacturing, calibrating, cleaning, or repairing instruments or devices referred to in the other groups of this subclass
- G01C25/005—Manufacturing, calibrating, cleaning, or repairing instruments or devices referred to in the other groups of this subclass initial alignment, calibration or starting-up of inertial devices
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Abstract
The invention discloses a kind of FPGA implementation method for optical fibre gyro test circuit, by modularized design, FPGA realizes the function that serial ports reception, data smoothing, temperature acquisition, data buffer storage, serial ports send.Serial ports receives baud rate, check bit, data smoothing number of times, the width and depth of FIFO are cached, the baud rate of data, check bit is sent and is realized by the parameter setting in FPGA design code, the fibre optic gyroscope serial ports output of different sequential can be received after the completion of parameter setting.Highly versatile of the present invention, solves the test problem of the fibre optic gyroscope of different output timings.
Description
Technical field
The present invention relates to a kind of implementation method for fibre optic gyroscope test circuit FPGA.
Background technology
It is serial port-shaped that fibre optic gyroscope is used to measure one of the angular speed of inertial space, output form of angular rate data
Formula, fibre optic gyroscope externally sends under different situations baud rate, check bit difference, causes the test job of fibre optic gyroscope difficult
Degree is big；Simultaneously because fibre optic gyroscope is temperature sensor, combination temperature data are needed to carry out angular rate data during test
Analysis, therefore it is badly in need of a kind of flexible, general method of testing, the fibre optic gyroscope of different sequential exports is received, while can adopt
Collection temperature data.In the prior art also without this method.
The content of the invention
It is an object of the invention to provide a kind of FPGA implementation method for fibre optic gyroscope test circuit, by modularization
Design, by the parameter setting in FPGA design code, can test the fibre optic gyroscope of different output timings, implementation method letter
It is single quick, highly versatile.
The present invention is achieved by the following technical programs：A kind of FPGA realization sides for fibre optic gyroscope test circuit
Method, the described method comprises the following steps：
Step one：The serial ports receiving unit receives fibre optic gyroscope angular rate data, and the angular rate data is sent
To the data smoothing unit；
Step 2：The data smoothing unit receives the angular rate data, and will be obtained after angular rate data smoothing processing
The data buffer storage unit is given to average angular rate data and by the average angular rate data is activation, while output smoothing is completed
Marking signal, and give the temperature collecting cell by the smooth complement mark signal output；
Step 3：The temperature collecting cell receives collecting temperature after the smooth complement mark signal, and temperature is sent out
Give the data buffer storage unit；
Step 4：The data buffer storage unit is received after the average angular rate data and the temperature and stored, and will
The average angular rate data and the temperature are exported to the data transmission unit；
Step 5：The average angular rate data and the temperature are sent to PC by the data transmission unit.
In the above-mentioned FPGA implementation method for fibre optic gyroscope test circuit, in step one, serial ports receiving unit connects
Receiving fibre optic gyroscope angular rate data includes：Input of the serial ports receiving unit according to reception baud rate clock division parameter to FPGA
Clock is divided, and is obtained serial ports and is received baud rate clock, and serial data is received successively under the enable for receiving baud rate clock
Start bit, byte data position, check bit sum stop position, check bit is judged, one byte when check bit is correct
Data are received as correct byte data；Each correct byte data arrival hour counter adds 1；Received when counter is 0
Frame head, counter receives 3 byte angular rate datas when being 1-3, and postamble is received when being 4；When the frame head and postamble that receive are correct
When, the angular rate data that serial ports receiver module will be received is sent to data smoothing module.
In the above-mentioned FPGA implementation method for fibre optic gyroscope test circuit, in step 2, angular rate data is smoothed
Treatment includes：2 for receivingNIndividual angular rate data add up and obtains angular speed accumulated value, and angular speed accumulated value is divided by 2NObtain
Average angular rate data.
In the above-mentioned FPGA implementation method for fibre optic gyroscope test circuit, in step 3, the temperature acquisition list
First output temperature gathers clock, the collecting temperature in the case where clock is gathered at each after receiving smooth complement mark signal.
In the above-mentioned FPGA implementation method for fibre optic gyroscope test circuit, in step 4, the data buffer storage list
The average angular rate data and temperature data storage that unit will receive are n to data width, and storage depth is 2mCaching FIFO
In, the data output that will be cached when in caching FIFO for non-NULL is to the data transmission unit.
In the above-mentioned FPGA implementation method for fibre optic gyroscope test circuit, in step 5, the data is activation list
Unit to the input clock of FPGA divide and obtains serial ports transmission baud rate clock according to send wave spy's rate clock division parameter,
The average angular rate data and temperature data of data cache module are sent by serial ports under the enable of transmission baud rate clock.
The present invention has the following advantages that compared with prior art：
1) the reception baud rate clock and check bit of serial ports receiving unit of the invention can be set in FPGA code, therefore
Can test the fibre optic gyroscope of different sequential exports, implementation method flexibly and fast, highly versatile；
2) data smoothing unit of the invention causes data smoothing, it is ensured that data stabilization reliability；
3) the baud rate clock of data transmission unit data is activation of the invention, check bit can be set in FPGA code,
Different data is activation demands can be met.
Brief description of the drawings
Fig. 1 is the functional block diagram of optical fibre gyro test circuit FPGA implementation method；
Fig. 2 is optical fibre gyro test circuit FPGA function module configuration parameter explanatory diagram；
Fig. 3 is the interface schema of optical fibre gyro test circuit FPGA and A/D chip；
Fig. 4 is fibre optic gyroscope hardware principle block diagram.
Specific embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings：
Fibre optic gyroscope is used to measure the angular speed of inertial space, and its hardware principle block diagram is as shown in figure 4, its angular speed number
According to one of output form be serial port form.Serial ports end periodically sends a frame data, data frame format be byte frame head,
Three byte angular rate data words and a byte postamble.The baud rate of data is activation is usually 115200bps or 230400bps,
Include a start bit, byte data position, bit check position and a stop position when each byte data sends.
The present embodiment provides a kind of FPGA implementation method of fibre optic gyroscope test circuit, as shown in Fig. 2 passing through modularization
Design, sets the parameter of each functional module in FPGA code, can test the fibre optic gyroscope of different output timings.
A kind of FPGA implementation method of fibre optic gyroscope test circuit is illustrated below in conjunction with Fig. 1：
Step one：Serial ports receiving unit 1 receives fibre optic gyroscope angular rate data, angular rate data is sent into data and is put down
Sliding unit 2.
Specifically, serial ports receiving unit 1 is divided the input clock of FPGA according to baud rate clock division parameter is received
Frequently, obtain serial ports and receive baud rate clock, receive start bit, one of serial data successively under the enable for receiving baud rate clock
Individual byte data position, check bit sum stop position, judge check bit, one byte data is used as correct when check bit is correct
Byte data received；
Each correct byte data arrival hour counter value adds 1；Counter receives frame head when being 0, counter connects when being 1-3
3 byte angular rate datas are received, postamble is received when being 4；When the frame head and correct postamble that receive, serial ports receiver module will be received
To angular rate data be sent to data smoothing module.
Step 2：Data smoothing unit 2 receives angular rate data, and will obtain average angle after angular rate data smoothing processing
Speed data and by average angular rate data is activation to data buffer storage unit 4, while output smoothing complement mark signal, and will be flat
Sliding complement mark signal output is to temperature collecting cell 3；
Specifically, angular rate data smoothing processing includes：2 for receivingNIndividual angular rate data add up and obtains angle speed
Rate accumulated value, angular speed accumulated value is divided by 2NObtain average angular rate data.
Step 3：Temperature collecting cell 3 receives collecting temperature after smooth complement mark signal, and sends a temperature to data
Buffer unit 4.
Specifically, temperature acquisition is realized by the data of acquisition chip AD7686, interface such as Fig. 3 institutes of AD7683 and FPGA
Show.Temperature collecting cell 3 exports chip selection signal CS and collection clock DCLOCK to AD7683, is receiving smooth complement mark signal
Afterwards in the Dout outputs of each collection clock DCLOCK collections AD7683, the data sampling time sequence of AD7683 can be found in the chip
User's manual.
Step 4：Data buffer storage unit 4 is received after average angular rate data and temperature and stored, and by average angular rate number
Exported to data transmission unit 5 according to temperature.
Specifically, the average angular rate data that will receive of data buffer storage unit 4 and temperature data storage are to data width
It is n, storage depth is 2mCaching FIFO in, when cache FIFO in for non-NULL when by cache data output give data is activation list
Unit 5.
Step 5：Average angular rate data and temperature are sent to PC by data transmission unit 5.
Specifically, data transmission unit 5 is divided the input clock of FPGA according to baud rate clock division parameter is sent
Frequency obtains serial ports and sends baud rate clock, by the average angular rate number of data cache module under the enable for sending baud rate clock
Sent by serial ports according to temperature data.
The present embodiment gathers the angular rate data and temperature of fibre optic gyroscope by application optical fibre gyro test circuit FPGA
Data, serial ports receives baud rate clock, check bit, and angular rate data smooths number of times；The width and storage depth of FIFO；Send number
According to baud rate clock, check bit can be programmed by FPGA and changed, therefore the fibre optic gyroscope of different sequential exports can be tested, together
When can collecting temperature data, implementation method flexibly and fast, highly versatile.
Embodiment of the present invention is described further with a specific embodiment below.
Assuming that the frame format of fibre optic gyroscope output angular rate data is x " 53 " (frame head), the high byte of angular rate data
Data, middle byte data, low byte data and x " 45 " (postamble), output baud rate are 115200bps, the verification of each byte
Position is even parity check, and the input clock of optical fibre gyro test circuit FPGA is 11.0592MHz, and it is 128 to smooth number of times requirement, caching
FIFO requirement width is 8Bits and depth is 1024, and the baud rate requirement for sending data is 230400bps, each word of transmission
Section check bit is odd.
By calculating, by 11.0592 × 10696 are obtained divided by 115200, baud rate clock division parameter is received and is set to
96,11.0592 × 10648 are obtained divided by 230400；Therefore each parameter is set in FPGA design code as follows：
Serial ports receiving unit：It is 96 to receive baud rate clock division parameter, and it is 0, a byte frame head to receive checking parameter
Data are x " 53 ", and byte postamble is x " 45 ", the output data frame format of correspondence fibre optic gyroscope is x " 53 " (frame head),
The high byte data of angular rate data, middle byte data, low byte data and x " 45 " (postamble)；Data output baud rate
115200bps, the check bit of each byte is even parity check, data smoothing unit：Data smoothing number of times 2NIt is set to 27, i.e. N=7,
The smooth number of times of correspondence is 128；
Data buffer storage unit：Data width is set to n=8, and storage depth is 210=1024, i.e. n=8, m=10, correspondence
The width for caching FIFO is 8Bits, and depth is 1024；
Data transmission unit：Send baud rate clock division parameter and be set to 48, send checking parameter and be set to 1, data
Transmission baud rate is 230400bps, and each byte check bit of transmission is odd.
Above-mentioned parameter can be used for the fibre optic gyroscope after the FPGA code of fibre optic gyroscope test circuit is provided with
Test.
The reception baud rate clock and check bit of serial ports receiving unit of the invention can be set in FPGA code, therefore can
Test the fibre optic gyroscope of different sequential exports, implementation method flexibly and fast, highly versatile；Data smoothing unit of the invention makes
Obtain data smoothing, it is ensured that data stabilization reliability；The baud rate clock of data transmission unit data is activation of the invention, check bit can
Set in FPGA code, different data is activation demands can be met.
Embodiment described above is the present invention more preferably specific embodiment, and those skilled in the art is in this hair
The usual variations and alternatives carried out in the range of bright technical scheme all should be comprising within the scope of the present invention.
Claims (6)
1. a kind of FPGA implementation method for fibre optic gyroscope test circuit, it is characterised in that methods described includes following step
Suddenly：
Step one：The serial ports receiving unit (1) receives fibre optic gyroscope angular rate data, and the angular rate data is sent to
The data smoothing unit (2)；
Step 2：The data smoothing unit (2) receives the angular rate data, and will be obtained after angular rate data smoothing processing
The average angular rate data is activation is simultaneously given the data buffer storage unit (4) by average angular rate data, while output smoothing is complete
Into marking signal, and the temperature collecting cell (3) is given by the smooth complement mark signal output；
Step 3：The temperature collecting cell (3) receives collecting temperature after the smooth complement mark signal, and temperature is sent
Give the data buffer storage unit (4)；
Step 4：The data buffer storage unit (4) receives after the average angular rate data and the temperature and stores, and by institute
State average angular rate data and the temperature is exported and gives the data transmission unit (5)；
Step 5：The average angular rate data and the temperature are sent to PC by the data transmission unit (5).
2. the FPGA implementation method for fibre optic gyroscope test circuit according to claim 1, it is characterised in that：In step
In rapid one, serial ports receiving unit (1) receives fibre optic gyroscope angular rate data to be included：
Serial ports receiving unit (1) is divided according to baud rate clock division parameter is received to the input clock of FPGA, is gone here and there
Mouth receives baud rate clock, receives start bit, a byte number of serial data successively under the enable for receiving baud rate clock
According to position, check bit sum stop position, check bit is judged, one byte data is used as correct byte number when check bit is correct
According to being received；
Each correct byte data arrival hour counter adds 1；Counter receives frame head when being 0, counter receives 3 words when being 1-3
Section angular rate data, receives postamble when being 4；When the frame head and correct postamble that receive, serial ports receiver module will be received
Angular rate data is sent to data smoothing module.
3. the FPGA implementation method for fibre optic gyroscope test circuit according to claim 1, it is characterised in that：In step
In rapid two, angular rate data smoothing processing includes：2 for receivingNIndividual angular rate data add up and obtains angular speed accumulated value,
Angular speed accumulated value is divided by 2NObtain average angular rate data.
4. the FPGA implementation method for fibre optic gyroscope test circuit according to claim 1, it is characterised in that：In step
In rapid three, temperature collecting cell (3) output temperature gathers clock, in each collection after smooth complement mark signal is received
Collecting temperature under clock.
5. the FPGA implementation method for fibre optic gyroscope test circuit according to claim 1, it is characterised in that：In step
In rapid four, the average angular rate data and temperature data storage that the data buffer storage unit (4) will receive are to data width
N, storage depth is 2mCaching FIFO in, when cache FIFO in for non-NULL when will cache data output give the data is activation
Unit (5).
6. the FPGA implementation method for fibre optic gyroscope test circuit according to claim 1, it is characterised in that：In step
In rapid five, the data transmission unit (5) divides according to baud rate clock division parameter is sent to the input clock of FPGA
Obtain serial ports and send baud rate clock, by the average angular rate data of data cache module under the enable for sending baud rate clock
Sent by serial ports with temperature data.
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