CN106711274A - Avalanche photodiode and manufacturing method thereof - Google Patents
Avalanche photodiode and manufacturing method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
- H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1828—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe
- H01L31/1832—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe comprising ternary compounds, e.g. Hg Cd Te
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Abstract
The invention relates to the technical field of photovoltaics, and provides an avalanche photodiode and a manufacturing method thereof. The avalanche photodiode comprises a I-type light absorbing layer, a I-type cap layer and a P-type contact layer. First channels are arranged on both sides of the p-type semiconductor region. Second channels which are engaged with the first channels are arranged on a I-type multiplication layer and a P-type electric field control layer. A third channel which is engaged with the second channels is arranged on an N-type contact layer. Each first channel is wider than each second channel. Each second channel is wider than the third channel. Compared with the prior art, the avalanche photodiode provided by the invention has the advantages that three-stepped channel design is used in the existing avalanche photodiode; the engagement problem that a sidewall N contact metal layer easily appears, which is caused by too deep channels, can be improved; and the processing yield of the avalanche photodiode is improved.
Description
【Technical field】
The present invention relates to field of photoelectric technology, more particularly to a kind of avalanche photodide and its manufacture method.
【Background technology】
(Avalanche Photodiode, are abbreviated as avalanche photodide：APD) because it has internal gain, can
To provide than PIN detector, (Positive-Intrinsic-Negative Detector, are abbreviated as：PD) high sensitivity, quilt
It is widely used in optical communication system.In recent years, towards the height of 100Gbit/s, even 400Gbit/s high-speed communication system applications
The speed of response, highly sensitive APD have become association area focus of attention.Relative to below 10Gbit/s's
InP/InGaAs materials As PD, InAlAs/InGaAs materials A PD is substantially favored.Because InAlAs impact ionization characteristics
Better than InP, the excess noise fact produced in multiplicative process is small, more suitable for the requirement of the speed of response high over long distances.
The epitaxial structure of InAlAs/InGaAs materials As PD is usually on the semi-insulating type substrate slice for mix Fe, to use molecular beam
(Molecular Beam Epitaxy, are abbreviated as epitaxy：MBE N-type InP cushions, N-type heavy doping contact) are produced successively
Layer, I type InAlAs dynode layers, p-type InP electrical wires, I type InGaAs light absorbing zones, I type InP cap layers, p-type InGaAs connects
Contact layer.
Inventor has found because InAlAs materials are in molecular beam chemical vapor epitaxy (Molecular Beam
Epitaxy, is abbreviated as：MBE) growth temperature so diffusion temperature should not be too high, and reduces temperature, I probably at 480 degrees Celsius
Type InAlAs materials again cannot be by diffusing into p-type.On the other hand, raceway groove of the prior art is too deep, and side-wall metallic cannot chain
The problem for connecing.Accordingly, it would be desirable to design new process conditions to solve the above problems.
【The content of the invention】
One of the technical problem to be solved in the present invention is improved in the prior art because channel depth requirement, may be brought
The problem that trench sidewalls metal cannot well be connected.
The technical problem further to be solved of the invention is to provide a kind of avalanche photodide and its manufacture method.
The present invention is adopted the following technical scheme that：
In a first aspect, the embodiment of the invention provides a kind of avalanche photodide, SI-substrate stacks gradually N-type and connects
Contact layer, I types dynode layer, p-type electrical wires, I types light absorbing zone, I types cap layers and p-type contact layer, wherein, profit in I type cap layers
Being generated with diffusion technique has P-type semiconductor region,
On I types light absorbing zone, I types cap layers and p-type contact layer, the both sides positioned at the P-type semiconductor region are provided with
First raceway groove；On I types dynode layer and p-type electrical wires, it is connected first raceway groove and is provided with the second raceway groove；In N-type
On contact layer, it is connected second raceway groove and is provided with triple channel；
Wherein, the first raceway groove is wider than the second raceway groove, and the second raceway groove is wider than triple channel；First raceway groove, the second raceway groove
All being grown with the both side surface of triple channel has dielectric passivation layer, positioned at first raceway groove, the second raceway groove and triple channel
N-type contact layer Surface Creation N contact metal layers in the dielectric passivation layer surface and raceway groove of outer rim side.
Optionally, connect in N-type contact layer, I types dynode layer, p-type electrical wires, I types light absorbing zone, I types cap layers and p-type
Contact layer is respectively：N-type InP contact layers, I type InAlAs dynode layers, p-type InP electrical wires, I type InGaAs light absorbing zones, I
When type InP cap layers and p-type InGaAs contact layers,
One layer of I type InAlAs covering is then additionally provided between the I types light absorbing zone and I type cap layers, wherein, the p-type
Semiconductor regions are processed by the designated area in I types cap layers and I type InAlAs coverings by Closed Tube Diffusion.
Optionally, the N-type InP contact layer doping concentrations 1e19cm-3, 0.5 μm of thickness；I type InAlAs dynode layers, doping
Concentration is less than 5e15cm-3, 0.2 to 0.4 μm of thickness；P-type InP electrical wires, doping concentration 1e18cm-3, thickness 0.32-
0.35μm；I type InGaAs light absorbing zones doping concentration is less than 5e15cm-3, 1 to 1.2 μm of thickness；I types InAlAs is clad doped dense
Degree is less than 5e15cm-3, 1 to 1.5 μm of thickness；I type InP cap layers doping concentration is less than 5e15cm-3, 1 to 1.5 μm of thickness；P-type
InGaAs contact layer doping concentrations 1e19cm-3, 0.15 μm of thickness.
Optionally, silicon nitride medium reflecting layer and reflective metal layer are arranged at the SI-substrate bottom, and silicon nitride medium is anti-
Penetrate thickness degreeShown reflective metal layer is made up of Ti/Pt/Au, and the thickness of wherein Ti, Pt, Au is respectivelyWith
Second aspect, the embodiment of the invention provides a kind of manufacture method of avalanche photodide, the manufacture method
Including：
On SI-substrate N-type contact layer, I types dynode layer, P are stacked gradually with the method for molecular beam meteorology epitaxial deposition
Type electrical wires, I types light absorbing zone, I types cap layers and p-type contact layer, wherein, there is P using diffusion technique generation in I type cap layers
Type semiconductor regions；
On I types light absorbing zone, I types cap layers and p-type contact layer, the both sides positioned at the P-type semiconductor region etch
First raceway groove；On I types dynode layer and p-type electrical wires, it is connected the bottom section of first raceway groove, etches second
Raceway groove, on N-type contact layer, is connected the bottom section of second raceway groove, etches triple channel；Wherein, the first raceway groove
Wider than the second raceway groove, the second raceway groove is wider than triple channel；
In the both side surface somatomedin passivation layer of first raceway groove, the second raceway groove and triple channel；Positioned at described
N-type contact layer Surface Creation N in the dielectric passivation layer surface and raceway groove of the first raceway groove, the second raceway groove and triple channel outer rim side
Contact metal layer.
Optionally, connect in N-type contact layer, I types dynode layer, p-type electrical wires, I types light absorbing zone, I types cap layers and p-type
Contact layer is respectively：N-type InP contact layers, I type InAlAs dynode layers, p-type InP electrical wires, I type InGaAs light absorbing zones, I
It is also meteorological outer by molecular beam between the I types light absorbing zone and I type cap layers when type InP cap layers and p-type InGaAs contact layers
Prolonging deposition has one layer of I type InAlAs covering, wherein, the P-type semiconductor region is by I types cap layers and I type InAlAs coverings
Designated area is processed by Closed Tube Diffusion.
Optionally, described P-type semiconductor region is completed by zinc Closed Tube Diffusion, wherein, diffusion source is zinc phosphide, diffusion temperature
Spend is 460 to 480 degrees Celsius.
Optionally, the N-type InP contact layer doping concentrations 1e19cm-3, 0.5 μm of thickness；I type InAlAs dynode layers, doping
Concentration is less than 5e15cm-3, 0.2 to 0.4 μm of thickness；P-type InP electrical wires, doping concentration 1e18cm-3, thickness 0.32-
0.35μm；I type InGaAs light absorbing zones doping concentration is less than 5e15cm-3, 1 to 1.2 μm of thickness；I types InAlAs is clad doped dense
Degree is less than 5e15cm-3, 1 to 1.5 μm of thickness；I type InP cap layers doping concentration is less than 5e15cm-3, 1 to 1.5 μm of thickness；P-type
InGaAs contact layer doping concentrations 1e19cm-3, 0.15 μm of thickness.
Optionally, the first raceway groove is etched, the second raceway groove is etched and etches triple channel, is specifically included
Photoetching and the use of hydrobromic acid, saturation bromine water and water ratio is 1:1:1 solution corrosion is to I type light absorbing zones；Use
The concentrated sulfuric acid, hydrogen peroxide and water ratio 1:1:5 solution corrosion is on p-type electrical wires, completing the corrosion of the first raceway groove；
Photoetching simultaneously uses hydrobromic acid, saturation bromine water and water ratio 1:2:5 solution corrosion is to N-type contact layer；
Photoetching simultaneously uses hydrobromic acid, saturation bromine water and water ratio 1:1:1 solution corrosion N-type contact layer, stops at half absolutely
Edge substrate.
Optionally, by epitaxial wafer attenuated polishing to about 150 μm, in epitaxial wafer burnishing surface enhancing plasma gas-phase depositSilicon nitride medium reflecting layer；
Using electron-beam evaporation mode, the formation Ti/Pt/Au reflective metal layers on silicon nitride medium reflecting layer, wherein Ti,
The thickness of Pt, Au is respectivelyWith
Compared with prior art, the beneficial effects of the present invention are：The embodiment of the present invention is by existing avalanche optoelectronic
The raceway grooves design of three layers of step is provided in diode, can improve that raceway groove is too deep, the rank that side wall N contact metal layers easily occur
Problem is connect, the machining yield of avalanche photodide is improve.Above-mentioned trench sidewalls metal linking is produced in the prior art
Problem, it is usually because degree of corrosion of the different layers in corrosive liquid can be different, so as to possible in disposable corrosion process
Calabash shape raceway groove is produced, so as to when generating N contact metal layers to follow-up side wall, leave the hidden danger that linking is interrupted.
【Brief description of the drawings】
Fig. 1 is a kind of cross-sectional view of avalanche photodide provided in an embodiment of the present invention；
Fig. 2 is a kind of cross-sectional view of avalanche photodide provided in an embodiment of the present invention；
Fig. 3 is a kind of manufacture method flow chart of avalanche photodide provided in an embodiment of the present invention；
Fig. 4 is a kind of channel etching method flow diagram of avalanche photodide provided in an embodiment of the present invention；
Fig. 5 is a kind of channel etching structural representation of avalanche photodide provided in an embodiment of the present invention；
Fig. 6 is a kind of channel etching structural representation of avalanche photodide provided in an embodiment of the present invention；
Fig. 7 is a kind of channel etching structural representation of avalanche photodide provided in an embodiment of the present invention；
Fig. 8 is a kind of channel etching structural representation of avalanche photodide provided in an embodiment of the present invention；
Fig. 9 is a kind of channel etching structural representation of avalanche photodide provided in an embodiment of the present invention；
Figure 10 is a kind of channel etching structural representation of avalanche photodide provided in an embodiment of the present invention；
Figure 11 is a kind of manufacture method flow chart of avalanche photodide provided in an embodiment of the present invention；
Figure 12 is a kind of overlooking the structure diagram of avalanche photodide provided in an embodiment of the present invention.
【Specific embodiment】
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
In the description of the invention, term " interior ", " outward ", " longitudinal direction ", " transverse direction ", " on ", D score, " top ", " bottom " etc. refer to
The orientation or position relationship for showing be based on orientation shown in the drawings or position relationship, be for only for ease of description the present invention rather than
It is required that the present invention with specific azimuth configuration and operation, therefore must be not construed as limitation of the present invention.
As long as additionally, technical characteristic involved in invention described below each implementation method is each other not
Constituting conflict can just be mutually combined.
Embodiment 1:
The embodiment of the present invention 1 provides a kind of avalanche photodide, as shown in figure 1, SI-substrate 10 stacks gradually N
Type contact layer 20, I types dynode layer 30, p-type electrical wires 40, I types light absorbing zone 50, I types cap layers 70 and p-type contact layer 80,
Wherein, there is P-type semiconductor region using diffusion technique generation in I types cap layers 70, in I types light absorbing zone 50, I types cap layers 70 and P
On type contact layer 80, the both sides of the P-type semiconductor region are provided with the first raceway groove 21；In I types dynode layer 30 and p-type electricity
On the key-course 40 of field, it is connected first raceway groove and is provided with the second raceway groove 22；On N-type contact layer 20, it is connected described
Two raceway grooves 22 are provided with triple channel；
Wherein, the raceway groove 22 of the first raceway groove 21 to the second is wide, and the triple channel of the second raceway groove 22 to the is wide by 23；First raceway groove
21st, the both side surface of the second raceway groove 22 and triple channel 23 all grows and has dielectric passivation layer 5, positioned at first raceway groove 21,
The Surface Creation N of N-type contact layer 20 in the surface of dielectric passivation layer 5 and raceway groove of the second raceway groove 22 and the outer rim side of triple channel 23 connects
Touch metal level 3.
The raceway grooves that the embodiment of the present invention passes through to be provided in existing avalanche photodide three layers of step are designed, can be with
Improvement raceway groove is too deep, the connection problem that side wall N contact metal layers easily occur, and improves the processed finished products of avalanche photodide
Rate.The problem of above-mentioned trench sidewalls metal linking is produced in the prior art, it is usually because corrosion of the different layers in corrosive liquid
Degree can be different, so that there may be calabash shape raceway groove in disposable corrosion process, so as to give the generation N contacts of follow-up side wall
During metal level, the hidden danger that linking is interrupted is left.
In embodiment of the present invention implementation process, inventor has found avalanche photodide of the prior art, and it is formed
P-type semiconductor region is shallower, and the radius of curvature of P-type semiconductor region bottom is smaller in the prior art, there is obvious edge
Field effect.Therefore, based on the embodiment of the present invention, additionally provide a kind of improvement project to improve above mentioned problem.Specifically, as schemed
Shown in 2, in N-type contact layer 20, I types dynode layer 30, p-type electrical wires 40, I types light absorbing zone 50, I types cap layers 70 and p-type
Contact layer 80 is respectively：N-type InP contact layers, I type InAlAs dynode layers, p-type InP electrical wires, I type InGaAs light absorbs
Under the APD application scenarios of the InAlAs/InGaAs materials of layer, I type InP cap layers and p-type InGaAs contact layers, the I types light is inhaled
Receive and be additionally provided with one layer of I type InAlAs covering 60 between layer 50 and I types cap layers 70, wherein, the P-type semiconductor region is by I types
Designated area in cap layers 70 and I type InAlAs coverings 60 is processed by Closed Tube Diffusion.
In the expansion scheme, I type InGaAs light absorbing zones 50 are low bandgap material, I type InP cap layers 70 and I types
InAlAs coverings 60 are wide bandgap materials, and I type InAlAs coverings 60 are also wider than I type InP 70 band gap of cap layers.
Embodiment 2:
A kind of structure of avalanche photodide is proposed in embodiment 1, the embodiment of the present invention is based on the basis of embodiment 1
It is upper that one group of parameter combination for being available for the avalanche photodide of realization is provided.Wherein, the N-type InP contact layer doping concentrations
1e19cm-3, 0.5 μm of thickness；I type InAlAs dynode layers, doping concentration is less than 5e15cm-3, 0.2 to 0.4 μm of thickness；P-type InP
Electrical wires, doping concentration 1e18cm-3, 0.32-0.35 μm of thickness；I type InGaAs light absorbing zone doping concentrations are less than
5e15cm-3, 1 to 1.2 μm of thickness；The doping concentration of I type InAlAs coverings 60 is less than 5e15cm-3, 1 to 1.5 μm of thickness；I types InP
Cap layers doping concentration is less than 5e15cm-3, 1 to 1.5 μm of thickness；P-type InGaAs contact layer doping concentrations 1e19cm-3, thickness 0.15
μm, described I type InAlAs coverings 60, doping is less than 5e15cm-3, 1 to 1.5 μm of thickness.
In embodiments of the present invention, because 1 to 1.2 μm of band gap I type InGaAs light absorbing zones thickness is relatively wide, can be fine
Reduction dark current.And, thick InAlAs coverings 60 (1 to 1.5 μm of thickness) can increase the bottom of P-type semiconductor region 90
Radius of curvature, reduce fringe field.
In embodiment of the present invention implementation process, inventor has found one group of reflecting film structure, can effectively improve photoelectricity
The responsiveness of diode.Specifically, silicon nitride medium reflecting layer 2 and reflective metal layer 1, nitrogen are arranged at the bottom of the SI-substrate 10
The thickness of SiClx dielectric reflective layer 2Reflective metal layer 1 is by Ti/Pt/AuComposition.It is logical
Cross and test the reflecting layer reflectivity of this combination and have 75%, for the InGaAs absorbed layers of 1.2um thickness, detector responsivity can
0.94A/W is brought up to from 0.71A/W.
Embodiment 3:
The embodiment of the present invention additionally provides a kind of manufacture method of avalanche photodide, for fabricating such as embodiment
1 or embodiment 2 described in avalanche photodide, as shown in Figure 3 (and using for reference Fig. 1 or Fig. 2), the manufacture method bag
Include：
In step 201, N-type is stacked gradually with the method for molecular beam meteorology epitaxial deposition on SI-substrate 10 to contact
Layer 20, I types dynode layer 30, p-type electrical wires 40, I types light absorbing zone 50, I types cap layers 70 and p-type contact layer 80, wherein, I
There is P-type semiconductor region using diffusion technique generation in type cap layers 70.
In step 202., on I types light absorbing zone 50, I types cap layers 70 and p-type contact layer 80, partly led positioned at the p-type
The both sides of body region etch the first raceway groove 21.
In step 203, on I types dynode layer 30 and p-type electrical wires 40, it is connected the bottom of first raceway groove 21
Portion region, etches the second raceway groove 22.
In step 204, on N-type contact layer 20, it is connected the bottom section of second raceway groove 22, etches the 3rd
Raceway groove 23；Wherein, the raceway groove 22 of the first raceway groove 21 to the second is wide, and the triple channel 23 of the second raceway groove 22 to the is wide.
In step 205, in the both side surface somatomedin of first raceway groove 21, the second raceway groove 22 and triple channel 23
Passivation layer.
In step 206, in the dielectric passivation layer table positioned at first raceway groove, the second raceway groove and triple channel outer rim side
N-type contact layer Surface Creation N contact metal layers in face and raceway groove.
The raceway grooves that the embodiment of the present invention passes through to be provided in existing avalanche photodide three layers of step are designed, can be with
Improvement raceway groove is too deep, the connection problem that side wall N contact metal layers easily occur, and improves the processed finished products of avalanche photodide
Rate.
In embodiment of the present invention implementation process, inventor has found avalanche photodide of the prior art, and it is formed
P-type semiconductor region 90 is shallower, and the radius of curvature of the bottom of P-type semiconductor region 90 is smaller in the prior art, exists significantly
Fringe field effects.Therefore, based on the embodiment of the present invention, additionally provide a kind of improvement project to improve above mentioned problem.Specifically,
In N-type contact layer 20, I types dynode layer 30, p-type electrical wires 40, I types light absorbing zone 50, I types cap layers 70 and p-type contact layer
80 are respectively：N-type InP contact layers 20, I type InAlAs dynode layers 30, p-type InP electrical wires 40, I type InGaAs light absorbs
When layer 50, I type InP cap layers 70 and p-type InGaAs contact layers 80, in the I types InGaAs light absorbing zones 50, I type InP cap layers 70
Between also by molecular beam meteorology epitaxial deposition have one layer of I type InAlAs covering 60, wherein, the P-type semiconductor region is by I types
Designated area in InP cap layers 70 and I type InAlAs coverings 60 is processed by Closed Tube Diffusion.
In above-mentioned extension embodiment, in order to diffusion material can be realized in the I types InAlAs coverings 60 and I type caps
Spread in layer 70, also to ensure diffusion temperature less than I type InAlAs growth temperatures (less than 480 degree), it is to avoid cause dark current to increase
Greatly.In order to overcome above-mentioned technological difficulties, with reference to the embodiment of the present invention, there is a kind of expansible implementation, specifically：It is described
P-type semiconductor region 90 completed by zinc Closed Tube Diffusion, wherein, diffusion source is zinc phosphide, and diffusion temperature is 460 to 480 Celsius
Degree.Wherein, it is on the premise of cannot ensureing I type InAlAs covering stability using diffusion temperature 500-550 of the prior art,
Complete corresponding diffusion process.
Based on the embodiment of the present invention, there is provided one group of parameter combination of the avalanche photodide for being available for realizing, wherein, it is described
The doping concentration 1e19cm of N-type InP contact layers 20-3, 0.5 μm of thickness；I type InAlAs dynode layers 30, doping concentration is less than 5e15cm-3, 0.2 to 0.4 μm of thickness；P-type InP electrical wires 40, doping concentration 1e18cm-3, 0.32-0.35 μm of thickness；I types
The doping concentration of InGaAs light absorbing zones 50 is less than 5e15cm-3, 1 to 1.2 μm of thickness；The doping concentration of I type InAlAs coverings 60 is less than
5e15cm-3, 1 to 1.5 μm of thickness；The doping concentration of I type InP cap layers 70 is less than 5e15cm-3, 1 to 1.5 μm of thickness；P-type InGaAs
The doping concentration 1e19cm of contact layer 80-3, 0.15 μm of thickness.
In embodiments of the present invention, because 1 to 1.2 μm of 50 thickness of band gap I type InGaAs light absorbing zones is relatively wide, can be very
Good reduction dark current.And, thick InAlAs coverings 60 (1 to 1.5 μm of thickness) can increase the bottom of P-type semiconductor region 90
The radius of curvature in portion, reduces fringe field.
Also there is a kind of optional expansion scheme with reference to the embodiment of the present invention, by epitaxial wafer attenuated polishing to about 150 μm,
Epitaxial wafer burnishing surface enhancing plasma gas-phase depositSilicon nitride medium reflecting layer 2；
Using electron-beam evaporation mode, Ti/Pt/Au reflective metal layers 1 are formed on silicon nitride medium reflecting layer 2, wherein
The thickness of Ti, Pt, Au is respectivelyWith
Have 75% by the reflecting layer reflectivity for testing this combination, for the InGaAs absorbed layers 50 of 1.2um thickness, visit
Surveying device responsiveness can bring up to 0.94A/W from 0.71A/W.
In embodiments of the present invention, in order to etch the first raceway groove 21, the second raceway groove 22 and triple channel 23, there is provided one
Preferred implementation is planted, as shown in figure 4, specifically including step performed below：
In step 301, photoetching and the use of hydrobromic acid, saturation bromine water and water ratio is 1:1:1 solution corrosion is to I type light
Absorbed layer 50.
Wherein, hydrobromic acid, saturation bromine water and water ratio are 1:1:1 corrosive liquid belongs to indistinction, can corrode and appoint
The corrosive liquid of layer of material, therefore, in the corrosion process in carrying out step 301, typically first carry out photoresist system 31 and treat
First raceway groove figure of corrosion, as shown in figure 5, then, being corroded by way of timing.The also permission portion in practical operation
Divide excessive erosion, you can with erodable section I types light absorbing zone 50, certain free space is left to operation.Execution of step 301 it
Chip structure profile afterwards is as shown in fig. 6, it is the region of the first raceway groove 21 to be etched wherein to draw dotted portion.
In step 302, the concentrated sulfuric acid, hydrogen peroxide and water ratio 1 are used:1:5 solution corrosion is to p-type electrical wires 40
On, complete the first raceway groove 21 and corrode.
Wherein, the concentrated sulfuric acid, hydrogen peroxide and water ratio 1:1:5 solution does not corrode InP, so InP electrical wires 40 can
To play a part of etch stop layer.Chip structure profile after execution of step 302 is as shown in Figure 7.
In step 303, photoetching and use hydrobromic acid, saturation bromine water and water ratio 1:2:5 solution corrosion is contacted to N-type
Layer 20.
Now photoetching process can override two walls of the first raceway groove such that it is able to avoid corroding carrying out the second raceway groove
Cheng Zhong, the side wall to the first raceway groove produces anticaustic such that it is able to improve issuable Pear-Shaped raceway groove in the prior art.
As shown in figure 8, after generally being intended to the photoresist in removal step 301 before carrying out step 303 photoetching process, photoresist is applied again
32, and make the figure of the second raceway groove by lithography.Execution of step 303, and remove the chip structure profile after corresponding photoresist 32
As shown in Figure 9.
Use hydrobromic acid, saturation bromine water and water ratio 1:2:5 solution is that hydrobromic acid, saturation bromine water and water ratio are 1:1:
/ 3rd of 1 solution corrosion speed, can avoid excessive corrosion.
In step 304, photoetching and use hydrobromic acid, saturation bromine water and water ratio 1:1:1 solution corrosion N-type contact layer
20, stop at SI-substrate 10.
As shown in Figure 10, illustrate to complete photoresist coating and accordingly making the chip structure after triple channel figure by lithography
Figure.
The embodiment of the present invention not only ensure that raceway groove in shape by the three-wheel photoetching process carried out for three-level raceway groove
Quality requirement, also improve using ledge structure when be subsequently formed N contact metal layers, continuity is attached to trench sidewalls
Success rate.
Embodiment 4:
The angle that the embodiment of the present invention is manufactured from a more complete industry, by a kind of snowslide proposed in embodiment 3
The manufacture method of photodiode is applied in actual production process, wherein, had been completed before step 401 is carried out half
In dielectric substrate 10 N-type contact layer 20, I types dynode layer 30, p-type electric field are stacked gradually with the method for molecular beam meteorology epitaxial deposition
Key-course 40, I types light absorbing zone 50, I type InAlAs coverings 60 and I types cap layers 70, respective chip structure in reference implementation example 1-3
Profile, as shown in figure 11, the embodiment of the present invention specifically includes following steps：
In step 401, the p-type InGaAs for forming annular by photoetching and etching process contacts ring 80；
In step 402, silica dioxide medium diffusion barrier is deposited by plasma reinforced chemical vapour deposition (PECVD)
Layer, and circular propagation region is formed by photoetching and etching process, P semiconductor regions are formed by low temperature Closed Tube Diffusion, remove
Diffusion impervious layer.
Closed Tube Diffusion technique is carried out in the prior art generally uses 500-550, and in embodiments of the present invention due to using
Zinc phosphide as diffusion source, therefore, diffusion temperature can be controlled in 460 to 480 degrees Celsius, and can complete accordingly to spread times
Business.
In step 403, the first raceway groove, the second raceway groove and triple channel are completed by step 301-304 in embodiment 3
Corrosion process.
In step 404, strengthen chemical vapor deposition (LPPECVD) by low-temperature plasma to depositSilicon nitride is situated between
Matter layer 5, exposes p-type InGaAs and contacts ring 80 by etching technics.
In step 405, using electron beam evaporation and stripping technology, P contact metal layers 4, N contact metal layers 3, P are formed
Area's pad and N areas pad.
In a step 406, it is heat-treated 1~3 minute at epitaxial wafer piece is in 300~360 DEG C.
In step 407, by epitaxial wafer attenuated polishing to about 150 μm, in epitaxial wafer burnishing surface enhancing plasma gas phase
Deposition process (PECVD) is depositedSilicon nitride medium reflecting layer 2.
In a step 408, using electron beam evaporation process, finally Ti/Pt/Au is formed on the anti-reflection dielectric layer 6 of silicon nitride
The thickness of reflective metal layer, wherein Ti, Pt, Au is respectivelyWith
In step 409, chip forms 300X300 μm 2 of avalanche photodide chip by cleavage.
After step 409 is completed, the top view of the avalanche photodide chip for obtaining is as shown in figure 12, wherein, p-type
It is photosurface 11 in the middle of metal contact layer 4, P areas contact pad 12 is connected across raceway groove 13 with p-type metal contact layer 4.N-type metal
Contact layer 3 is covered in the bottom of raceway groove 13 and outside, and N areas contact pad 14 is drawn in both sides.Wherein, in embodiment 1 and embodiment 3
The sectional view of related chip is that the observation of A-A ' angles is obtained from top view shown in Figure 12.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Any modification, equivalent and improvement made within god and principle etc., should be included within the scope of the present invention.
Claims (10)
1. a kind of avalanche photodide, SI-substrate stack gradually N-type contact layer, I types dynode layer, p-type electrical wires,
I types light absorbing zone, I types cap layers and p-type contact layer, wherein, there is P-type semiconductor region using diffusion technique generation in I type cap layers,
Characterized in that,
On I types light absorbing zone, I types cap layers and p-type contact layer, the both sides positioned at the P-type semiconductor region are provided with first
Raceway groove；On I types dynode layer and p-type electrical wires, it is connected first raceway groove and is provided with the second raceway groove；In N-type contact
On layer, it is connected second raceway groove and is provided with triple channel；
Wherein, the first raceway groove is wider than the second raceway groove, and the second raceway groove is wider than triple channel；First raceway groove, the second raceway groove and
The both side surface of triple channel all grows and has dielectric passivation layer, positioned at first raceway groove, the second raceway groove and triple channel outer shroud
N-type contact layer Surface Creation N contact metal layers in the dielectric passivation layer surface and raceway groove of side.
2. avalanche photodide according to claim 1, it is characterised in that in N-type contact layer, I types dynode layer, p-type
Electrical wires, I types light absorbing zone, I types cap layers and p-type contact layer are respectively：N-type InP contact layers, I type InAlAs dynode layers,
When p-type InP electrical wires, I type InGaAs light absorbing zones, I type InP cap layers and p-type InGaAs contact layers,
One layer of I type InAlAs covering is then additionally provided between the I types light absorbing zone and I type cap layers, wherein, the p-type is partly led
Body region is processed by the designated area in I types cap layers and I type InAlAs coverings by Closed Tube Diffusion.
3. avalanche photodide according to claim 2, it is characterised in that the N-type InP contact layer doping concentrations
1e19cm-3, 0.5 μm of thickness；I type InAlAs dynode layers, doping concentration is less than 5e15cm-3, 0.2 to 0.4 μm of thickness；P-type InP
Electrical wires, doping concentration 1e18cm-3, 0.32-0.35 μm of thickness；I type InGaAs light absorbing zone doping concentrations are less than
5e15cm-3, 1 to 1.2 μm of thickness；The clad doped concentration of I types InAlAs is less than 5e15cm-3, 1 to 1.5 μm of thickness；I type InP caps
Layer doping concentration is less than 5e15cm-3, 1 to 1.5 μm of thickness；P-type InGaAs contact layer doping concentrations 1e19cm-3, the μ of thickness 0.15
m。
4. avalanche photodide according to claim 3, it is characterised in that silicon nitride is arranged at the SI-substrate bottom
Dielectric reflective layer and reflective metal layer, silicon nitride medium reflector thicknessShown reflective metal layer is by Ti/Pt/Au structures
Into the thickness of wherein Ti, Pt, Au is respectivelyWith
5. a kind of manufacture method of avalanche photodide, it is characterised in that the manufacture method includes：
On SI-substrate N-type contact layer, I types dynode layer, p-type electricity are stacked gradually with the method for molecular beam meteorology epitaxial deposition
Field key-course, I types light absorbing zone, I types cap layers and p-type contact layer, wherein, there is p-type half using diffusion technique generation in I type cap layers
Conductive region；
On I types light absorbing zone, I types cap layers and p-type contact layer, the both sides positioned at the P-type semiconductor region etch first
Raceway groove；On I types dynode layer and p-type electrical wires, it is connected the bottom section of first raceway groove, etches the second ditch
Road, on N-type contact layer, is connected the bottom section of second raceway groove, etches triple channel；Wherein, the first raceway groove ratio
Second raceway groove is wide, and the second raceway groove is wider than triple channel；
In the both side surface somatomedin passivation layer of first raceway groove, the second raceway groove and triple channel；Positioned at described first
N-type contact layer Surface Creation N contacts in the dielectric passivation layer surface and raceway groove of raceway groove, the second raceway groove and triple channel outer rim side
Metal level.
6. manufacture method according to claim 5, it is characterised in that in N-type contact layer, I types dynode layer, p-type electric field control
Preparative layer, I types light absorbing zone, I types cap layers and p-type contact layer are respectively：N-type InP contact layers, I type InAlAs dynode layers, p-type InP
When electrical wires, I type InGaAs light absorbing zones, I type InP cap layers and p-type InGaAs contact layers, in the I types light absorbing zone
Also there is one layer of I type InAlAs covering by molecular beam meteorology epitaxial deposition and I type cap layers between, wherein, the P-type semiconductor area
Domain is processed by the designated area in I types cap layers and I type InAlAs coverings by Closed Tube Diffusion.
7. manufacture method according to claim 6, it is characterised in that described P-type semiconductor region is by zinc Closed Tube Diffusion
Complete, wherein, diffusion source is zinc phosphide, and diffusion temperature is 460 to 480 degrees Celsius.
8. manufacture method according to claim 6, it is characterised in that the N-type InP contact layer doping concentrations 1e19cm-3,
0.5 μm of thickness；I type InAlAs dynode layers, doping concentration is less than 5e15cm-3, 0.2 to 0.4 μm of thickness；P-type InP electric field controls
Layer, doping concentration 1e18cm-3, 0.32-0.35 μm of thickness；I type InGaAs light absorbing zones doping concentration is less than 5e15cm-3, thickness
1 to 1.2 μm；The clad doped concentration of I types InAlAs is less than 5e15cm-3, 1 to 1.5 μm of thickness；I type InP cap layers doping concentrations are less than
5e15cm-3, 1 to 1.5 μm of thickness；P-type InGaAs contact layer doping concentrations 1e19cm-3, 0.15 μm of thickness.
9. according to any described manufacture methods of claim 5-8, it is characterised in that etch the first raceway groove, etch second
Raceway groove and triple channel is etched, specifically included
Photoetching and the use of hydrobromic acid, saturation bromine water and water ratio is 1:1:1 solution corrosion is to I type light absorbing zones；Use dense sulphur
Acid, hydrogen peroxide and water ratio 1:1:5 solution corrosion is on p-type electrical wires, completing the corrosion of the first raceway groove；
Photoetching simultaneously uses hydrobromic acid, saturation bromine water and water ratio 1:2:5 solution corrosion is to N-type contact layer；
Photoetching simultaneously uses hydrobromic acid, saturation bromine water and water ratio 1:1:1 solution corrosion N-type contact layer, stops at semi-insulating lining
Bottom.
10. manufacture method according to claim 5, it is characterised in that by epitaxial wafer attenuated polishing to about 150 μm, outside
Prolong piece burnishing surface enhancing plasma gas-phase depositSilicon nitride medium reflecting layer；
Using electron-beam evaporation mode, on silicon nitride medium reflecting layer formed Ti/Pt/Au reflective metal layers, wherein Ti, Pt,
The thickness of Au is respectivelyWith
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| CN110571300A (en) * | 2019-08-01 | 2019-12-13 | 武汉电信器件有限公司 | epitaxial wafer, planar photodiode and preparation method thereof |
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| CN113964237A (en) * | 2021-09-30 | 2022-01-21 | 北京英孚瑞半导体科技有限公司 | Preparation method of avalanche photodetector with secondary epitaxial collector region and electric field protection ring |
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