CN106711050A - Method for preparing thin film transistor - Google Patents
Method for preparing thin film transistor Download PDFInfo
- Publication number
- CN106711050A CN106711050A CN201611174455.0A CN201611174455A CN106711050A CN 106711050 A CN106711050 A CN 106711050A CN 201611174455 A CN201611174455 A CN 201611174455A CN 106711050 A CN106711050 A CN 106711050A
- Authority
- CN
- China
- Prior art keywords
- layer
- film transistor
- thin film
- insulating barrier
- tft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000000463 material Substances 0.000 claims abstract description 20
- 238000002360 preparation method Methods 0.000 claims abstract description 17
- 238000001312 dry etching Methods 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims description 32
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052681 coesite Inorganic materials 0.000 claims description 5
- 229910052906 cristobalite Inorganic materials 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910052682 stishovite Inorganic materials 0.000 claims description 5
- 229910052905 tridymite Inorganic materials 0.000 claims description 5
- 239000011787 zinc oxide Substances 0.000 claims description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 1
- 238000004062 sedimentation Methods 0.000 claims 1
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 2
- 239000007769 metal material Substances 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 56
- 238000010586 diagram Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Abstract
The present invention relates to the technical field of liquid crystal displays, and particularly discloses a method for preparing a thin film transistor. According to the technical scheme of the invention, a metal material for conducting the patterning treatment in the dry etching manner is adopted to replace the existing preparation material of a top gate layer. In this way, the top gate layer and a gate insulating layer are treated in the dry etching manner. As a result, the line width difference between the top gate layer and the gate insulating layer is reduced or eliminated. The characteristics of the thin film transistor are optimized.
Description
Technical field
The invention belongs to technical field of liquid crystal display, specifically, it is related to a kind of film crystal tube preparation method.
Background technology
At present, IGZO (indium gallium zinc oxide) is top gate layer of the indium gallium zinc oxide as active layer
(Top Gate) structure can reduce the parasitic capacitance of source-drain electrode and gate electrode.But, using self-registered technology to top gate layer
Problem occurs when being performed etching with insulating barrier (GI).As shown in figure 1, because existing thin film transistor (TFT) is wrapped successively from bottom to up
Include：Substrate 10, light shield layer 20, cushion 30, active layer 40, insulating barrier 50, top gate layer 60.Wherein, top gate layer material is generally
Copper, is so typically carried out by the way of wet etching, causes line width loss larger.And insulating barrier 50 is typically adopted for non-metallic film
Carried out with the method for dry etching, line width loss amount is smaller.Therefore the line between a top gate layer 60 and insulating barrier 50 occurs
Shown in width difference Δ L.Follow-up conductorization treatment had not both been done in the region, and controlling for the electric field also not caused by top gate layer grid voltage causes
There is the problem of deterioration in the device of top gate structure.
The content of the invention
In order to solve the problems, such as above-mentioned prior art, a kind of preparation method of thin film transistor (TFT) of the invention, it includes
Following steps：
Lay conducting wire and light shield layer on the glass substrate using conductive material；
The depositing first insulator layer on the light shield layer；
Indium gallium zinc oxide is deposited on first insulating barrier as active layer；
The second insulating barrier is deposited on the active layer；And deposit top gate layer on second insulating barrier；
The top gate layer, the second insulating barrier are performed etching successively using dry etching method；
The 3rd insulating barrier is deposited on the active layer, and default Jie electricity areas on the active layer are entered at column conductor
Reason；
Sedimentary origin, drain electrode, the source, drain electrode are corresponding with the Jie electricity areas；And by the top gate layer and the conduction
Circuit is electrically connected.
Wherein, the top gate layer material is the metal that can be patterned by dry etching.
Wherein, the top gate layer material is molybdenum or titanium.
Wherein, the conductive material includes conductive layer and metal connecting layer stacked on top of one another.
Wherein, the conductive layer material is copper；The metal connecting layer material is molybdenum or titanium.If conductive copper is directly
It is sputtered on glass and is not easy attachment, it is therefore desirable to makes glass more firm with the connection of copper by metal connecting layer.
Wherein, the metal connecting layer thickness is 10~50nm；The conductive layer thickness is 200~600nm.
Wherein, first insulating barrier, the second insulating barrier, the material of the 3rd insulating barrier are SiO2。
Wherein, first insulating barrier, the second insulating barrier, the 3rd insulating barrier are heavy by PECVD
What area method was obtained.
Wherein, the active layer is obtained by physical vaporous deposition.
Beneficial effect：
The present invention disclosure satisfy that conducting wire is the purpose of ground resistance wiring, while can also reduce gate insulator with top
Linewidth difference between gate layer, improves the performance of device, can largely be used in the preparation of the thin film transistor backplane of top gate type, especially
The electrical of thin film transistor (TFT) can be improved.
Brief description of the drawings
By the following description carried out with reference to accompanying drawing, above and other aspect of embodiments of the invention, feature and advantage
Will become clearer, in accompanying drawing：
Fig. 1 is the thin-film transistor structure schematic diagram of prior art.
Fig. 2 is thin film transistor (TFT) preparation flow schematic diagram of the present invention.
Fig. 3 is thin-film transistor structure schematic diagram of the present invention.
Specific embodiment
Hereinafter, with reference to the accompanying drawings to describing embodiments of the invention in detail.However, it is possible to come real in many different forms
Apply the present invention, and the present invention should not be construed as limited to the specific embodiment that illustrates here.Conversely, there is provided these implementations
Example is in order to explain principle of the invention and its practical application, so that others skilled in the art are it will be appreciated that the present invention
Various embodiments and be suitable for the various modifications of specific intended application.
The present invention provides a kind of preparation method of thin film transistor (TFT), with reference to shown in Fig. 2, comprises the following steps：
Step one：Conducting wire 21 and light shield layer are laid in glass substrate (not shown) using conductive material
22；Wherein, the conductive material is by conductive layer (not shown) and metal connecting layer (not shown) stacked on top of one another
Constitute.Wherein, conductive layer thickness is generally 200~600nm, and material is copper；Metal connecting layer thickness is generally 10~50nm, material
Matter is molybdenum or titanium.If this is directly to process to be not easy attachment on the glass substrate due to the material copper of conductive layer, product is influenceed
Can, in order to stablize the connection of conductive layer and glass substrate, it is necessary to introduce metal connecting layer therebetween.
Specifically, as shown in Fig. 2 (a), formed on the glass substrate by magnetically controlled sputter method metal light shield layer 22 and
The cabling for completing conducting wire 21 is laid.Wherein, the material of light shield layer and conducting wire can be with identical.
Step 2：As shown in Fig. 2 (b), using plasma strengthens chemical vapour deposition technique (PECVD) in the light shield layer
Depositing first insulator layer 23 on 22, usually, the material of first insulating barrier 23 uses SiO2。
Then indium gallium zinc oxide (IGZO) is deposited on first insulating barrier 23 using physical vaporous deposition (PVD)
As active layer 24, and the active layer 24 patterned simultaneously.
Step 3：As shown in Fig. 2 (c), deposited on the active layer 24 second insulating barrier (and as gate insulator,
Not shown in figure, can combine shown in Fig. 3)；And top gate layer 26 is deposited on second insulating barrier, and to the top gate layer 26
Patterned.Wherein, in order to subsequent etching method can be unified, the material selection of top gate layer 26 disclosure satisfy that dry etching will
The metal material for asking to be patterned, preferably molybdenum or titanium.Usually, the material of second insulating barrier uses SiO2。
In etching procedure, with reference to shown in Fig. 3, first the top gate layer 26 is performed etching using dry etching method, then
Second insulating barrier 25 is performed etching, due to the insulating barrier 25 of top gate layer 26 and second by way of dry etching come pattern
Change, the line width loss after etching is smaller so that linewidth difference Δ L between the two is reduced and even disappeared, with reference to shown in Fig. 3, with this
Obtain the optimization of device performance.
Step 4：Continue to deposit on the active layer 24 not shown in the 3rd insulating barrier figure (interlayer insulating film is also called,
Material is generally SiO2), and to default Jie electricity areas, i.e. active layer on the active layer 24 and subsequent source, drain electrode contact zone
Domain, enters column conductorization treatment.
Step 5：Sedimentary origin, drain electrode 28 simultaneously carry out patterned process, shown in such as Fig. 2 (d).
The source, a part for drain electrode 28 will be corresponding with the Jie electricity areas and be deposited on the active layer 24.So simultaneously
The top gate layer 28 is formed with the conducting wire 21 and is electrically connected, now obtain thin film transistor (TFT).
The preparation method of the thin film transistor (TFT) that the present invention is provided, disclosure satisfy that the purpose that conducting wire is ground resistance wiring,
The linewidth difference between gate insulator and top gate layer can be also reduced simultaneously, the performance of device is improved, and can largely be used in top-gated
In prepared by the thin film transistor backplane of type, can especially improve the electrical of thin film transistor (TFT).
Although the present invention has shown and described with reference to specific embodiment, it should be appreciated by those skilled in the art that：
In the case where the spirit and scope of the present invention limited by claim and its equivalent are not departed from, can carry out herein form and
Various change in details.
Claims (9)
1. a kind of preparation method of thin film transistor (TFT), it is characterised in that comprise the following steps：
Lay conducting wire and light shield layer on the glass substrate using conductive material；
The depositing first insulator layer on the light shield layer；
Indium gallium zinc oxide is deposited on first insulating barrier as active layer；
The second insulating barrier is deposited on the active layer；And deposit top gate layer on second insulating barrier；
The top gate layer, the second insulating barrier are performed etching successively using dry etching method；
The 3rd insulating barrier is deposited on the active layer, and enters column conductorization treatment to default Jie electricity areas on the active layer；
Sedimentary origin, drain electrode, the source, drain electrode are corresponding with the Jie electricity areas；And by the top gate layer and the conducting wire
Electrical connection.
2. the preparation method of thin film transistor (TFT) according to claim 1, it is characterised in that the top gate layer material is can to lead to
Cross the metal that dry etching is patterned.
3. the preparation method of thin film transistor (TFT) according to claim 1, it is characterised in that the top gate layer material be molybdenum or
Titanium.
4. the preparation method of thin film transistor (TFT) according to claim 1, it is characterised in that the conductive material includes levels
Folded conductive layer and metal connecting layer.
5. the preparation method of thin film transistor (TFT) according to claim 4, it is characterised in that the conductive layer material is copper；Institute
Metal connecting layer material is stated for molybdenum or titanium.
6. according to claim 4 or 5 thin film transistor (TFT) preparation method, it is characterised in that the metal connecting layer thickness
It is 10~50nm；The conductive layer thickness is 200~600nm.
7. the preparation method of thin film transistor (TFT) according to claim 1, it is characterised in that first insulating barrier, second exhausted
Edge layer, the material of the 3rd insulating barrier are SiO2。
8. the preparation method of thin film transistor (TFT) according to claim 1, it is characterised in that first insulating barrier, second exhausted
Edge layer, the 3rd insulating barrier are obtained by plasma enhanced chemical vapor deposition method.
9. the preparation method of thin film transistor (TFT) according to claim 1, it is characterised in that the active layer is by physics gas
What phase sedimentation was obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611174455.0A CN106711050A (en) | 2016-12-19 | 2016-12-19 | Method for preparing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611174455.0A CN106711050A (en) | 2016-12-19 | 2016-12-19 | Method for preparing thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106711050A true CN106711050A (en) | 2017-05-24 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611174455.0A Pending CN106711050A (en) | 2016-12-19 | 2016-12-19 | Method for preparing thin film transistor |
Country Status (1)
| Country | Link |
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| CN (1) | CN106711050A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107359126A (en) * | 2017-07-11 | 2017-11-17 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte and display panel |
| WO2020232747A1 (en) * | 2019-05-17 | 2020-11-26 | 深圳市华星光电半导体显示技术有限公司 | Thin-film transistor device and preparation method therefor |
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| CN103811559A (en) * | 2014-02-21 | 2014-05-21 | 苏州大学 | Thin film transistor with bipolar operating characteristics |
| CN105372891A (en) * | 2015-12-04 | 2016-03-02 | 上海天马微电子有限公司 | Array substrate, display device |
| CN106097949A (en) * | 2014-04-29 | 2016-11-09 | 乐金显示有限公司 | Shift register and use the display device of this shift register |
-
2016
- 2016-12-19 CN CN201611174455.0A patent/CN106711050A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020001048A1 (en) * | 2000-06-29 | 2002-01-03 | Lee Deuk Su | Method of fabricating liquid crystal display with a high aperture ratio |
| JP2009117620A (en) * | 2007-11-07 | 2009-05-28 | Casio Comput Co Ltd | Image reading device and method of manufacturing same |
| WO2013011257A1 (en) * | 2011-07-21 | 2013-01-24 | Cambridge Display Technology Limited | Method of forming a top gate transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107359126A (en) * | 2017-07-11 | 2017-11-17 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte and display panel |
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| WO2020232747A1 (en) * | 2019-05-17 | 2020-11-26 | 深圳市华星光电半导体显示技术有限公司 | Thin-film transistor device and preparation method therefor |
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Application publication date: 20170524 |