CN106710554B - Flashing drift optimization circuit and optimization method, array substrate, display device - Google Patents

Flashing drift optimization circuit and optimization method, array substrate, display device Download PDF

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Publication number
CN106710554B
CN106710554B CN201710049150.5A CN201710049150A CN106710554B CN 106710554 B CN106710554 B CN 106710554B CN 201710049150 A CN201710049150 A CN 201710049150A CN 106710554 B CN106710554 B CN 106710554B
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switch
flashing
output end
control
charge
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CN106710554A (en
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李云松
陆旭
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BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The phenomenon that drifting about the present invention provides a kind of flashing and optimize circuit and optimization method, array substrate, display device, be related to field of display technology, the residual charge in capacitor can be eliminated, improving flashing drift.Wherein, flashing drift optimization circuit includes trigger module, charge outflow control module, first switch tube and second switch；First switch tube control terminal is connected with trigger module, and input terminal is connected with driving signal input, and output end is connected with charge outflow control module；First switch tube eliminates period conducting in charge, makes charge outflow control module work, flows out the residual charge in the capacitor of each sub-pixel；Second switch control terminal is connected with trigger module output end, and input terminal is connected with driving signal input；Second switch is connected in the display control period, so that the output end of second switch is exported control signal, controls each sub-pixel and show.Above-mentioned flashing drift optimization circuit is for improving the phenomenon that flashing drift in display picture.

Description

Flashing drift optimization circuit and optimization method, array substrate, display device
Technical field
The present invention relates to technical field of liquid crystal display more particularly to a kind of flashing drift optimization circuits and optimization method, battle array Column substrate, display device.
Background technique
Currently, liquid crystal display has been widely used in people's lives, and with the development of display technology, people Requirement to picture shown by liquid crystal display it is also higher and higher.
For liquid crystal display after each power-off, the capacitor in each sub-pixel of array substrate can remain part electricity Lotus.After booting liquid crystal display next time, charge in capacitor of the source electrode driver to each sub-pixel aobvious to carry out picture During showing, there is deviation in the voltage positive-negative polarity that this remaining Partial charge will lead to each pixel electrode in capacitor, this is partially Difference will lead to the voltage deviation standard value of public electrode, and the phenomenon that flashing drift occurs in the picture for showing liquid crystal display, lead Causing the quality of picture shown by liquid crystal display reduces, and can also make one to generate sense of discomfort when serious.
Summary of the invention
It drifts about the present invention provides a kind of flashing and optimizes circuit and optimization method, array substrate, display device, can show The residual charge in capacitor is eliminated before device booting, improves the phenomenon that flashing drift in display picture.
In order to achieve the above objectives, the present invention adopts the following technical scheme:
First aspect present invention provides a kind of flashing drift optimization circuit, a work of the flashing drift optimization circuit It is divided into charge as the period and eliminates period and display control period；The flashing drift optimization circuit includes trigger module, electric charge stream Control module, first switch tube and second switch out；Wherein, the control terminal of the first switch tube and the trigger module Output end be connected, the input terminal of the first switch tube is connected with driving signal input, the first switch tube it is defeated Outlet is connected with charge outflow control module；The first switch tube is used for: the period is eliminated in the charge, in the touching It sends out and is connected under the control of module, under the action of the driving signal that driving signal input is inputted, make the charge Control module work is flowed out, the residual charge in the capacitor of each sub-pixel is flowed out；In the display control period, in the touching It sends out and is turned off under the control of module, the charge outflow control module is made not work；The control terminal of the second switch with it is described The output end of trigger module is connected, and the input terminal of the second switch is connected with driving signal input；Described Two switching tubes are used for: in the display control period, being connected under the control of the trigger module, inputted in the driving signal Under the action of the driving signal that terminal is inputted, so that the output end of the second switch is exported control signal, control each sub- picture Element display；The period is eliminated in the charge, is turned off under the control of the trigger module, is controlled each sub-pixel and do not show.
It is drifted about using flashing provided by the present invention and optimizes circuit, based between each section in flashing drift optimization circuit Connection relationship, charge eliminate the period, trigger module control first switch tube conducting, second switch shutdown, display control Period processed, trigger module control first switch tube shutdown, second switch conducting.In this way, being switched in liquid crystal display shows picture Before face, charge outflow control module first controls the remaining charge outflow of institute in the capacitor of sub-pixel, eliminates the residual in capacitor Charge.In this way, the remaining charge of institute that can avoid in the capacitor of sub-pixel brings disturbance to public electrode voltages, common electrical is avoided Pole tension deviates standard value, and then largely improves the phenomenon that flashing drift in display picture.
Second aspect of the present invention provides a kind of flashing drift optimization method, is applied to flashing drift optimization circuit In, flashing drift is optimized；The flashing drift optimization circuit includes trigger module, charge outflow control module, first Switching tube and second switch；One duty cycle of the flashing drift optimization circuit is divided into charge and eliminates period and display Control time；The flashing drift optimization method includes: to eliminate period, the trigger module control described second in the charge Switching tube shutdown, controls each sub-pixel and does not show；The trigger module controls the first switch tube conducting, believes in the driving Under the action of the driving signal that number input terminal is inputted, the charge outflow control module work makes the capacitor of each sub-pixel The outflow of institute's residual charge；In the display control period, the trigger module controls the second switch conducting, in the drive Under the action of the driving signal that dynamic signal input terminal is inputted, the output end output control signal of second switch, control is respectively Sub-pixel is shown；The trigger module controls the first switch tube shutdown, and the charge outflow control module is made not work.
It is dodged provided by the beneficial effect and the first aspect of the present invention of flashing drift optimization method provided by the present invention The beneficial effect of bright drift optimization circuit is identical, and details are not described herein again.
Third aspect present invention provides a kind of array substrate, and the array substrate includes such as the first aspect of the present invention institute The flashing drift optimization circuit stated.
The beneficial effect of array substrate provided by the present invention and flashing drift provided by the first aspect of the present invention are excellent The beneficial effect for changing circuit is identical, and details are not described herein again.
Fourth aspect present invention provides a kind of display device, and the display device includes such as the third aspect of the present invention institute The array substrate stated.
The beneficial effect of display device provided by the present invention and flashing drift provided by the first aspect of the present invention are excellent The beneficial effect for changing circuit is identical, and details are not described herein again.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with Other attached drawings are obtained according to these attached drawings.
Fig. 1 is the structural schematic diagram one of flashing drift optimization circuit provided by the embodiment of the present invention one；
Fig. 2 is the structural schematic diagram two of flashing drift optimization circuit provided by the embodiment of the present invention one；
Fig. 3 is the timing of each signal intensity in the flashing drift optimization circuit course of work provided by the embodiment of the present invention one Figure.
Description of symbols:
1- trigger module；2- charge flows out control module；
3- capacitor；11- delay cell；
K1First switch tube； K2Second switch；
VGHDriving signal input；VDD- trigger signal input terminal；
XOR- XOR gate；The output end of VDD_D- delay cell；
INV1- the first phase inverter； INV2- the second phase inverter；
CLK1The positive control terminal of _ P- first switch tube； CLK1The Reverse Turning Control end of _ N- first switch tube；
CLK2The positive control terminal of _ P- second switch； CLK2The Reverse Turning Control end of _ N- second switch；
CLCiLiquid crystal capacitance； CSCiStorage capacitance；
R33rd resistor； VcomCommon voltage terminal；
GND- ground terminal； M11~M1NThe first transistor；
R1First resistor； VGHThe output end of _ 1- first switch tube；
R2Second resistance； CoomParasitic capacitance；
M2iSecond transistor； VGHThe output end of _ 2- second switch.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, implement below in conjunction with the present invention Attached drawing in example, technical scheme in the embodiment of the invention is clearly and completely described.Obviously, described embodiment Only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, the common skill in this field Art personnel all other embodiment obtained without creative labor belongs to the model that the present invention protects It encloses.
Embodiment one
As shown in Figure 1, a kind of flashing drift optimization circuit is present embodiments provided, one of flashing drift optimization circuit Duty cycle is divided into charge and eliminates period and display control period.
It specifically may include trigger module 1, charge outflow control module 2, first switch tube in flashing drift optimization circuit K1And second switch K2。
Wherein, first switch tube K1Control terminal be connected with the output end of trigger module 1, first switch tube K1Input terminal With the sub- V of driving signal inputGHIt is connected, first switch tube K1Output end and charge outflow control module 2 be connected.
First switch tube K1For: the period is eliminated in charge, is connected under the control of trigger module 1, it is defeated in driving signal Enter terminal VGHUnder the action of the driving signal inputted, charge outflow control module 2 is set to work, and then make capacitor in each sub-pixel The remaining charge outflow of 3 institutes；It in the display control period, is turned off under the control of trigger module 1, charge is made to flow out control module 2 It does not work.
Second switch K2Control terminal be connected with the output end of trigger module 1, second switch K2Input terminal and driving Signal input terminal VGHIt is connected.
Second switch K2For: in the display control period, be connected under the control of trigger module 1, it is defeated in driving signal Enter terminal VGHUnder the action of the driving signal inputted, make second switch K2Output end output control signal, to sub-pixel In capacitor 3 charge, control each sub-pixel and show；The period is eliminated in charge, turns off, controls under the control of trigger module 1 Each sub-pixel is made not show.
Using provided by the present embodiment flashing drift optimization circuit, based on the flashing drift optimization circuit in each section it Between connection relationship, charge eliminate the period, trigger module 1 control first switch tube K1Conducting, second switch K2Shutdown, Display control period, trigger module 1 control first switch tube K1Shutdown, second switch K2Conducting.In this way, in liquid crystal display Before booting display picture, charge outflow control module 2 first controls the remaining charge outflow of institute in the capacitor 3 of sub-pixel, eliminates Residual charge in capacitor 3.So, it can avoid the remaining charge of institute in the capacitor 3 of sub-pixel to public electrode voltages Disturbance is brought, public electrode voltages is avoided to deviate standard value, and then largely improves in display picture and flashes drift The phenomenon that.
As shown in Fig. 2, trigger module 1 specifically may include trigger signal input terminal VDD, delay cell 11 and XOR gate XOR。
Wherein, the input terminal of delay cell 11 is connected with trigger signal input terminal VDD, the first input of XOR gate XOR End is connected with trigger signal input terminal VDD, and the second input terminal of XOR gate XOR is connected with the output end VDD_D of delay cell, The output end and first switch tube K of XOR gate XOR1Control terminal and second switch K2Control terminal be connected.
Below by taking the trigger signal of trigger signal input terminal VDD output high level as an example, to delay cell 11 and exclusive or The working principle of door XOR is illustrated:
When trigger signal input terminal VDD has just exported the trigger signal of high level, the first input end of XOR gate XOR is connect The signal of high level is received, and since delay cell 11 has the function of exporting signal delay, thus current time, delay are single The signal that the output end VDD_D of member is exported is low level, and the second input terminal of XOR gate XOR receives low level signal. Based on the working principle of XOR gate XOR, the signal of the output end output of moment XOR gate XOR is high level.
When trigger signal input terminal VDD persistently exports the trigger signal of high level for a period of time, and the trigger signal Have been subjected to delay cell 11 delay exported after, the first input end of XOR gate XOR and the second input terminal receive height The signal of level, the signal of moment XOR gate XOR output are low level.
Optionally, delay cell 11 may include 2M the first phase inverter INV1, wherein M is the integer more than or equal to 1. Using 2M the first phase inverter INV1Constitute delay cell 11, the trigger signal that trigger signal input terminal VDD is inputted need through By multiple first phase inverter INV1It is transmitted and is converted, this could be exported after allowing for signal delay for a period of time, another party Face, using 2M the first phase inverter INV1, moreover it is possible to guarantee the state and triggering of the delayed trigger signal that delay cell 11 is exported The state of signal is identical.
It should be noted that the first switch tube K in the present embodiment1With second switch K2It can be low level conducting, It can be high level conducting, with specific reference to first switch tube K1With second switch K2Type determine.
Preferably, first switch tube K1With second switch K2It can be transmission gate switch, at this point, the present embodiment provides Flashing drift optimization circuit further include the second phase inverter INV2.The output end of XOR gate XOR respectively with first switch tube just To control terminal CLK1The Reverse Turning Control end CLK of _ P, second switch2_ N and the second phase inverter INV2Input terminal be connected；Second Phase inverter INV2Output end respectively with the Reverse Turning Control end CLK of first switch tube1The positive control terminal of _ N and second switch CLK2_ P is connected.Given this connection relationship, when the signal of the output end of XOR gate XOR output high level, first switch tube Positive control terminal CLK1_ P receives the exported high level signal of XOR gate XOR, the Reverse Turning Control end CLK of first switch tube1_ N is received By the second phase inverter INV2Low level signal after reverse phase, so that first switch tube K1Conducting.At the same time, second switch Positive control terminal CLK2_ P is received by the second phase inverter INV2Low level signal after reverse phase, the Reverse Turning Control end of second switch CLK2_ N receives the exported high level signal of XOR gate XOR, so that second switch K2Shutdown.
In contrast, when the output end of XOR gate XOR exports low level signal, the positive control of first switch tube Hold CLK1_ P receives the exported low level signal of XOR gate XOR, the Reverse Turning Control end CLK of first switch tube1_ N receives anti-by second Phase device INV2High level signal after reverse phase, so that first switch tube K1Shutdown.At the same time, the positive control of second switch Hold CLK2_ P is received by the second phase inverter INV2High level signal after reverse phase, the Reverse Turning Control end CLK of second switch2_ N connects The exported low level signal of XOR gate XOR is received, so that second switch K2Conducting.
It is found that the specific structure of the flashing drift optimization circuit according to provided by the present embodiment, it is only necessary to pass through XOR gate XOR A signal being exported of output end, so that it may so that first switch tube K1With second switch K2Two at synchronization The different state of kind.
Further, the charge outflow control module 2 in flashing drift optimization circuit specifically may include multiple and sub-pixel In the one-to-one the first transistor M of capacitor11~M1N, the first transistor M11~M1NGrid pass through first resistor R1With The output end V of first switch tubeGH_ 1 is connected, the first transistor M11~M1NDrain electrode pass through second resistance R2With ground terminal GND It is connected, the first transistor M11~M1NSource electrode be connected with capacitor.
As the first transistor M11~M1NGrid receive the output end V of first switch tubeGH_ 1 high level letter exported Number when, the first transistor M11~M1NConducting, liquid crystal capacitance CLCiWith storage capacitance CSCiThe middle remaining charge of institute can pass through second Resistance R2Flow into ground terminal GND.
It should be noted that the capacitor of each sub-pixel specifically includes the liquid crystal capacitance CLC being connected in seriesiAnd storage capacitance CSCi.Liquid crystal capacitance CLCiWith storage capacitance CSCiPass through 3rd resistor R respectively3It is connected with ground terminal GND, and storage capacitance CSCi It is connected with the source electrode of the first transistor corresponding to the sub-pixel of place.According to liquid crystal capacitance CLCiWith storage capacitance CSCiConnection Relationship, as the first transistor M11~M1NWhen conducting, liquid crystal capacitance CLCiWith storage capacitance CSCiIn remaining charge not only can be with Via second resistance R2Ground terminal GND is flowed to, it can also be via 3rd resistor R3Ground terminal GND is flowed to, which adds residuals The outflow pathway of charge, and then can guarantee that residual charge all flows out.
In addition, each sub-pixel should also include second transistor M2i, wherein i is the mark of the column of second transistor Number.Second transistor M2iGrid and second switch output end VGH_ 2 are connected, second transistor M2iDrain electrode with it is corresponding Liquid crystal capacitance CLCiIt is connected, second transistor M2iSource electrode and the source electrode of corresponding the first transistor be connected, while also and source electrode Line is connected.
As second switch K2When conducting, in the sub- V of driving signal inputGHUnder the action of the driving signal inputted, the Two-transistor M2iConducting, source electrode line export display drive signals to corresponding sub-pixel, corresponding sub-pixel are driven to be shown.
It is understood that Fig. 2 be illustrate give the structure of a line sub-pixel in array substrate, wherein CLC1、 CSC1And M21Respectively correspond liquid crystal capacitance, storage capacitance and the second transistor in a line in first row sub-pixel, CLC2、CSC2 And M22Liquid crystal capacitance, storage capacitance and the second transistor in a line in secondary series sub-pixel are respectively corresponded, and so on, CLCN、CSCNAnd M2NRespectively correspond liquid crystal capacitance, storage capacitance and the second transistor in a line in Nth column sub-pixel.As above I=1~the N.
In addition, liquid crystal capacitance CLCi, storage capacitance CSCiAlso with parasitic capacitance CoomThe first pole plate be connected, parasitic capacitance CoomThe second pole plate be connected with ground terminal GND.In addition, liquid crystal capacitance CLCi, storage capacitance CSCiAnd parasitic capacitance Coom? One pole plate is also connected with common voltage terminal Vcom。
Parasitic capacitance CoomWith common voltage terminal VcomIdentical as function in the prior art, this will not be repeated here.
In order to which how relatively sharp description flashing drift optimization circuit provided in this embodiment works, below with reference to Fig. 2 Shown in flashing drift optimization circuit specific structure and signal intensity shown in Fig. 3 timing diagram, the present embodiment is provided Flashing drift optimization circuit the course of work be described in detail.Wherein, Fig. 3 be liquid crystal display from the last time down under The timing diagram of the signal intensity of period between primary booting display picture.
First period, after liquid crystal display shutdown, trigger signal and driving letter that trigger signal input terminal VDD is exported Number input terminal VGHThe driving signal exported is low level, the delay triggering that the output end VDD_D of delay cell is exported Signal is also low level.
Therefore, the positive control terminal CLK of first switch tube1_ P received signal is low level, Reverse Turning Control end CLK1_ N connects The signal of receipts is high level, first switch tube K1Shutdown.First switch tube output end VGH_ 1 output signal be low level, first Transistor M11~M1NIt can not be connected, liquid crystal capacitance CLCiWith storage capacitance CSCiIn residual charge can not flow out.
At the same time, the positive control terminal CLK of second switch2_ P received signal is high level, Reverse Turning Control end CLK2_ N received signal is low level, second switch K2Conducting.But due to the sub- V of driving signal inputGHThe drive exported Signal is moved as low level, thus the output end V of second switchGHThe signal of _ 2 outputs is also low level, so that second transistor M2iIt can not be connected, each sub-pixel is enabled to be in non-display state.
Second period, the trigger signal that trigger signal input terminal VDD is exported starts as high level, and driving signal is defeated Enter terminal VGHThe driving signal exported is low level, due to the delayed-action by delay cell 11, at this point, delay cell The delayed trigger signal that output end VDD_D is exported still is low level, and the signal that the output end of XOR gate XOR is exported is high electricity It is flat.
Therefore, the positive control terminal CLK of first switch tube1_ P received signal is high level, Reverse Turning Control end CLK1_ N connects The signal of receipts is low level, first switch tube K1Conducting.But due to the sub- V of driving signal inputGHThe driving signal exported is Low level, thus first switch tube output end VGHThe signal of _ 1 output is also low level, the first transistor M11~M1NIt can not lead It is logical, liquid crystal capacitance CLCiWith storage capacitance CSCiIn residual charge can not flow out.
At the same time, second switch K2Positive control terminal CLK2_ P received signal is low level, Reverse Turning Control end CLK2_ N received signal is high level, second switch K2Shutdown, second switch K2Output end VGHThe signal of _ 2 outputs is low Level, second transistor M21~M2NIt can not be connected, each sub-pixel is enabled to be in non-display state.
The third period, the trigger signal that trigger signal input terminal VDD is exported keeps high level, and driving signal inputs Terminal VGHThe driving signal exported is also high level.
Within the third period, the signal that the output end VDD_D of delay cell is exported still is low level, therefore, XOR gate The signal of the output end output of XOR is high level.At this moment, the positive control terminal CLK of first switch tube1_ P received signal is height Level, Reverse Turning Control end CLK1_ N received signal is low level, first switch tube K1Conducting.Due to driving signal input VGHThe driving signal exported is high level, thus first switch tube output end VGHThe signal of _ 1 output is also high level, first Transistor M11~M1NConducting, liquid crystal capacitance CLCiWith storage capacitance CSCiIn residual charge can be via second resistance R2And third Resistance R3Flow to ground terminal.
At the same time, the positive control terminal CLK of second switch2_ P received signal is low level, Reverse Turning Control end CLK2_ N received signal is high level, second switch K2Shutdown, second switch K2Output end VGHThe signal of _ 2 outputs is low Level, second transistor M2iIt can not be connected, each sub-pixel is enabled to be in non-display state.
It should be noted that working as liquid crystal capacitance CLCiWith storage capacitance CSCiIn residual charge all reserve after, it is corresponding Residual voltage V discharges into zero potential.
It is understood that the charge in the third period corresponding flashing drift optimization circuit duty cycle eliminates the period.
4th period, trigger signal input terminal VDD persistently export high level trigger signal for a period of time, and this when The sub- V of section driving signal inputGHThe driving signal exported is still high level.
Within the 4th period, the delayed trigger signal that the output end VDD_D of delay cell is exported is high level, therefore, The signal of the output end output of XOR gate XOR is low level.At this moment, the positive control terminal CLK of first switch tube1The received letter of _ P Number be low level, Reverse Turning Control end CLK1_ N received signal is high level, first switch tube K1Shutdown, first switch tube output Hold VGHThe signal of _ 1 output is low level, the first transistor M11~M1NIt can not be connected, liquid crystal capacitance CLCiWith storage capacitance CSCi In residual charge can not flow out.
At the same time, the positive control terminal CLK of second switch2_ P received signal is high level, Reverse Turning Control end CLK2_ N received signal is low level, second switch K2Conducting.Due to the sub- V of driving signal inputGHThe driving exported Signal is high level, thus the output end V of second switchGH_ 2 signals exported are high level, second transistor M2iIt leads Logical, the display drive signals of source electrode line output drive corresponding sub-pixel to show, that is, enter the normal display of picture.
It is understood that the display control period in the 4th period corresponding flashing drift optimization circuit duty cycle.
The situation of change list of the state of each signal corresponding to one different periods of table
It is defeated with VDD reference trigger signal input terminal VDD institute in table one to keep the content in table more clear succinct Trigger signal out, the delayed trigger signal exported with the output end VDD_D that VDD_D refers to delay cell, uses VGHIt refers to and drives Dynamic signal input terminal VGHThe driving signal exported, uses CLK1_ P and CLK1_ N respectively refers to the forward direction control for first switch tube Hold CLK1_ P and Reverse Turning Control end CLK1_ N received signal, uses VGH_ 1 and VGH_ 2 respectively refer to for first switch tube output end VGH_1 With second switch output end VGHThe signal of _ 2 outputs, and use CLK2_ P and CLK2_ N respectively refers to the forward direction for second switch Control terminal CLK2_ P and Reverse Turning Control end CLK2_ N received signal.Label shown in Fig. 3 timing diagram is similarly.
It should be noted that according to the actual situation, the trigger signal for the high level that trigger signal input terminal VDD is exported It can be 3.3V, the sub- V of driving signal inputGHThe driving signal of the high level exported can be 22V.
Embodiment two
A kind of flashing drift optimization method is present embodiments provided, which drifts about optimization method applied to one institute of embodiment In the flashing drift optimization circuit of offer, flashing drift can be optimized using flashing drift optimization method.
As described above, referring to Fig. 2, flashing drift optimization circuit may include trigger module 1, charge outflow control module 2, first switch tube K1And second switch K2；One duty cycle of flashing drift optimization circuit is divided into charge and eliminates the period With the display control period.
Correspondingly, flashing drift optimization method specifically includes:
The period is eliminated in charge, trigger module 1 controls second switch K2Shutdown, controls each sub-pixel and does not show；Triggering Module 1 controls first switch tube K1Conducting, in the sub- V of driving signal inputGHUnder the action of the driving signal inputted, electric charge stream Control module 2 works out, flows out capacitor institute's residual charge of each sub-pixel.
In the display control period, trigger module 1 controls second switch K2Conducting, in the sub- V of driving signal inputGHInstitute is defeated Under the action of the driving signal entered, second switch K2Output end output control signal, control each sub-pixel and show；Trigger mode Block 1 controls first switch tube K1Shutdown makes charge outflow control module 2 not work.
Compared with prior art, the beneficial effect and above-described embodiment one of flashing drift optimization method provided in this embodiment The beneficial effect of the flashing drift optimization circuit of offer is identical, and this will not be repeated here.
First switch tube K in flashing drift optimization circuit1With second switch K2It is transmission gate switch, and flashes It include the second phase inverter INV in drift optimization circuit2When, corresponding, flashing drift optimization method further include:
Period, the positive control terminal CLK of the output end of XOR gate XOR to first switch tube are eliminated in charge1_ P output is high The signal of level, the second phase inverter INV2The signal progress reverse phase for the high level that the output end of XOR gate XOR is exported, second Phase inverter INV2Reverse Turning Control end CLK from output end to first switch tube1_ N exports low level signal, first switch tube K1 Conducting.
Reverse Turning Control end CLK of the output end of XOR gate XOR to second switch2The signal of _ N output high level, second Phase inverter INV2Positive control terminal CLK from output end to second switch2_ P exports low level signal, second switch K2 Shutdown.
In the display control period, the positive control terminal CLK of the output end of XOR gate XOR to first switch tube1_ P output is low The signal of level, the second phase inverter INV2The low level signal progress reverse phase that the output end of XOR gate XOR is exported, second Phase inverter INV2Reverse Turning Control end CLK from output end to first switch tube1_ N exports the signal of high level, first switch tube K1 Shutdown.
Reverse Turning Control end CLK of the output end of XOR gate XOR to second switch2The low level signal of _ N output, second Phase inverter INV2Positive control terminal CLK from output end to second switch2_ P exports the signal of high level, second switch K2 Conducting.
Embodiment three
A kind of array substrate is present embodiments provided, which includes that the flashing drift as provided by embodiment one is excellent Change circuit.
Using array substrate provided by the present embodiment, as including flashing drift optimization electricity provided by embodiment one Road, thus, before liquid crystal display is switched on display picture, the remaining charge outflow of institute in capacitor can be first controlled, eliminates capacitor In residual charge.In this way, the remaining charge of institute that can avoid in capacitor brings disturbance to public electrode voltages, common electrical is avoided Pole tension deviates standard value, and then largely improves the phenomenon that flashing drift in display picture.
Example IV
A kind of display device is present embodiments provided, which includes the array substrate as described in embodiment three.
Using display device provided by the present embodiment, as including array substrate provided by embodiment three, thus, Before the display device boots up display picture, the remaining charge of institute has been eliminated in the capacitor of sub-pixel, and then very The phenomenon that flashing drift in display picture is improved in big degree.
The foregoing is merely a specific embodiment of the invention, but scope of protection of the present invention is not limited thereto, any In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by those familiar with the art, all answers It is included within the scope of the present invention.Therefore, protection scope of the present invention should be with the scope of protection of the claims It is quasi-.

Claims (10)

1. a kind of flashing drift optimization circuit, which is characterized in that a duty cycle of the flashing drift optimization circuit is divided into Charge eliminates period and display control period；Flashing drift optimization circuit include trigger module, charge outflow control module, First switch tube and second switch；Wherein,
The control terminal of the first switch tube is connected with the output end of the trigger module, the input terminal of the first switch tube with Driving signal input is connected, and the output end of the first switch tube is connected with charge outflow control module；Described One switching tube is used for: being eliminated the period in the charge, is connected under the control of the trigger module, inputs in the driving signal Under the action of the driving signal that terminal is inputted, the charge outflow control module is set to work, in the capacitor for making each sub-pixel Residual charge outflow；It in the display control period, is turned off under the control of the trigger module, makes the charge outflow control Module does not work；
The control terminal of the second switch is connected with the output end of the trigger module, the input terminal of the second switch with Driving signal input is connected；The second switch is used for: in the display control period, in the trigger module Control under be connected, under the action of the driving signal that driving signal input is inputted, make the second switch Output end output control signal, control each sub-pixel and show；The period is eliminated in the charge, in the control of the trigger module Lower shutdown controls each sub-pixel and does not show.
2. flashing drift optimization circuit according to claim 1, which is characterized in that the trigger module includes trigger signal Input terminal, delay cell and XOR gate；Wherein,
The input terminal of the delay cell is connected with the trigger signal input terminal；The first input end of the XOR gate and institute It states trigger signal input terminal to be connected, the second input terminal of the XOR gate is connected with the output end of the delay cell, described The output end of XOR gate is connected with the control terminal of the control terminal of the first switch tube and the second switch.
3. flashing drift optimization circuit according to claim 2, which is characterized in that the delay cell includes 2M first Phase inverter, wherein M is the integer more than or equal to 1.
4. flashing drift optimization circuit according to claim 2, which is characterized in that the first switch tube and described second Switching tube is transmission gate switch；The flashing drift optimization circuit further includes the second phase inverter；The output end of the XOR gate Respectively with the positive control terminal of the first switch tube, the Reverse Turning Control end of the second switch and second phase inverter Input terminal be connected, the output end of second phase inverter respectively with the Reverse Turning Control end of the first switch tube and described second The positive control terminal of switching tube is connected.
5. flashing drift optimization circuit according to claim 1, which is characterized in that the charge flows out control module and includes It is multiple with each sub-pixel in the one-to-one the first transistors of capacitor, the grid of the first transistor by first resistor with The output end of the first switch tube is connected, and the drain electrode of the first transistor is connected by second resistance with ground terminal, described The source electrode of the first transistor is connected with the capacitor in corresponding sub-pixel.
6. flashing drift optimization circuit according to claim 5, which is characterized in that the capacitor of each sub-pixel includes liquid crystal Capacitor and storage capacitance, the liquid crystal capacitance and storage capacitance pass through 3rd resistor respectively and are connected with the ground terminal；Described One end of three resistance is connected with the first pole plate of parasitic capacitance, and the second of the other end of the 3rd resistor and the parasitic capacitance Pole plate is connected.
The optimization method 7. a kind of flashing is drifted about, which is characterized in that be applied to flashing described in claim 1 drift optimization circuit In, flashing drift is optimized；The flashing drift optimization circuit includes trigger module, charge outflow control module, first Switching tube and second switch；One duty cycle of the flashing drift optimization circuit is divided into charge and eliminates period and display Control time；Flashing drift optimization method includes:
The period is eliminated in the charge, the trigger module controls the second switch shutdown, controls each sub-pixel and do not show； The trigger module controls the first switch tube conducting, in the work for the driving signal that driving signal input is inputted Under, the charge outflow control module work flows out capacitor institute's residual charge of each sub-pixel；
In the display control period, the trigger module controls the second switch conducting, inputs in the driving signal Under the action of the driving signal that terminal is inputted, the output end output control signal of second switch controls each sub-pixel and shows； The trigger module controls the first switch tube shutdown, and the charge outflow control module is made not work.
The optimization method 8. flashing according to claim 7 is drifted about, which is characterized in that the flashing drift optimization circuit also wraps The second phase inverter is included, the first switch tube and the second switch are transmission gate switch；The trigger module includes different Or door；The flashing drift optimization method further include:
The period is eliminated in the charge, the output end of the XOR gate exports high electricity to the positive control terminal of the first switch tube Flat signal, the signal for the high level that second phase inverter is exported the output end of the XOR gate carries out reverse phase, described The output end of second phase inverter exports low level signal, the first switch tube to the Reverse Turning Control end of the first switch tube Conducting；
For the output end of the XOR gate to the signal of the Reverse Turning Control end of second switch output high level, described second is anti- The output end of phase device exports low level signal, the second switch shutdown to the positive control terminal of the second switch；
In the display control period, the output end of the XOR gate exports low electricity to the positive control terminal of the first switch tube Flat signal, the low level signal that second phase inverter is exported the output end of the XOR gate carries out reverse phase, described Signal of the output end of second phase inverter to the Reverse Turning Control end of first switch tube output high level, the first switch tube Shutdown；
The output end of the XOR gate exports low level signal to the Reverse Turning Control end of the second switch, and described second is anti- Signal of the output end of phase device to the positive control terminal of second switch output high level, the second switch conducting.
9. a kind of array substrate, which is characterized in that drift about including flashing as described in any one of claims 1 to 6 and optimize circuit.
10. a kind of display device, which is characterized in that including array substrate as claimed in claim 9.
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CN108269544B (en) * 2018-01-31 2020-08-25 京东方科技集团股份有限公司 Flicker drift optimization circuit, display panel and display device
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1959482A (en) * 2006-10-25 2007-05-09 友达光电股份有限公司 Liquid crystal display capable of eliminating ghost, and method
CN104297969A (en) * 2014-10-28 2015-01-21 京东方科技集团股份有限公司 Liquid crystal display panel, discharging method thereof and display device
CN104616615A (en) * 2015-02-10 2015-05-13 昆山龙腾光电有限公司 Screen clearing circuit and display device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9135881B2 (en) * 2012-12-20 2015-09-15 Shenzhen China Star Optoelectronics Technology Co., Ltd LCD panel driver circuit, driving method and LCD device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1959482A (en) * 2006-10-25 2007-05-09 友达光电股份有限公司 Liquid crystal display capable of eliminating ghost, and method
CN104297969A (en) * 2014-10-28 2015-01-21 京东方科技集团股份有限公司 Liquid crystal display panel, discharging method thereof and display device
CN104616615A (en) * 2015-02-10 2015-05-13 昆山龙腾光电有限公司 Screen clearing circuit and display device

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