CN106708237A - Power-off protection method, device and computer - Google Patents
Power-off protection method, device and computer Download PDFInfo
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- CN106708237A CN106708237A CN201710043719.7A CN201710043719A CN106708237A CN 106708237 A CN106708237 A CN 106708237A CN 201710043719 A CN201710043719 A CN 201710043719A CN 106708237 A CN106708237 A CN 106708237A
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- computer
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- reset
- power supply
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
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- General Engineering & Computer Science (AREA)
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Abstract
The invention discloses a power-off protection method, a device and a computer. The method includes the steps: detecting whether the computer exists abnormal power-off conditions or not; resetting a CMOS (complementary metal oxide semiconductor), and enabling reset signals to be from an external circuit comprising a power supply chip. According to the power-off protection method, when the computer exists abnormal power-off conditions, the reset CMOS on a computer motherboard transmitted by the external circuit is received, and signals of the CMOS are reset, and the external circuit comprises the power supply chip, so that risks of failure transmitting the reset CMOS signals caused by sudden power off are avoided when an EC (electronic computer) detects abnormal power-off conditions.
Description
Technical field
The present invention relates to power-off protection technical field, more particularly to a kind of power-off protection method, device and computer.
Background technology
During the use of computer, sometimes there is the situation of abnormal power-down：For example, notebook computer is in start mould
Under formula, while removing power supply adaptor and battery.In this case, often cause system cannot normal boot-strap failure.
In the prior art, when there is this failure, can be by resetting complementary metal oxide semiconductors (CMOS)
(Complementary Metal Oxide Semiconductor, CMOS) eliminates failure.But, before and after CMOS is reset
During, it is necessary to disassembly and assembly computer.Because the part of computer is very accurate and complexity, in an assembling process, hold very much
Easily there is the situation for losing part or assembly defect etc..
The content of the invention
In view of this, the purpose of the embodiment of the present invention is to provide a kind of failure caused due to power-off in reparation computer
When, it is not necessary to dismantling computer can just repair power-off protection method, device and the computer of failure.
To achieve these goals, a kind of power-off protection method is the embodiment of the invention provides, including：
Detection computer whether there is abnormal power-down；
If in the presence of, CMOS is reset, and reset signal comes from the outer circuits for including power supply chip.
Preferably, CMOS is reset, including：
Receive and wake up the reset signal that south bridge hangs up logic；
Receive the control signal for starting south bridge stand-by power supply.
Preferably, receive that the reset signal that south bridge hangs up logic is waken up, including：
The reset signal is set to the first predetermined level；
After first predetermined level continues Preset Time, the reset signal is set to the second predetermined level；It is described
Second predetermined level is higher than first predetermined level.
Preferably, the control signal for starting south bridge stand-by power supply is received, including：
After the reset signal is set into the second predetermined level, the control letter of the stand-by power supply for starting the south bridge is received
Number.
The embodiment of the present invention also provides a kind of power-off protection apparatus, including：
Detection module, is configured to detection computer and whether there is abnormal power-down；
Receiver module, is configured to be reset when the computer has abnormal power-down the signal of CMOS, and reset signal comes
From in the outer circuits including power supply chip.
Preferably, the receiver module, including：
First receiving submodule, is configured to receive the reset signal for waking up south bridge hang-up logic；
Second receiving submodule, is configured to receive the control signal for starting south bridge stand-by power supply.
Preferably, first receiving submodule, including：
First sets submodule, is configured to for the reset signal to be set to the first predetermined level；
Second sets submodule, after being configured to the lasting Preset Time of first predetermined level, the reset signal is set
It is set to the second predetermined level；Second predetermined level is higher than first predetermined level.
Preferably, second receiving submodule, including：
3rd receiving submodule, after being configured to for the reset signal to be set to the second predetermined level, receives described in starting
The control signal of the stand-by power supply of south bridge.
The embodiment of the present invention also provides a kind of computer, and the computer includes device as described above, the computer
Mainboard on include outer circuits, the outer circuits are configured to send the control letter for resetting the CMOS on the computer motherboard
Number.
Preferably, the outer circuits include the first FET, the second FET, first resistor and the second electricity
Resistance；The grid of first FET receives MPWRG signals, and the source electrode of first FET connects the first resistor
First end, the second end connection power supply of the first resistor, the source electrode of first FET is also connected with described second
The grid of effect pipe, the grounded drain of first FET, the grounded drain of second FET, described second
The source electrode of effect pipe connects the first end of the second resistance, the second end output RSMRST signals of the second resistance.
Compared with prior art, the embodiment of the present invention has the advantages that：The technical scheme of the embodiment of the present invention is worked as
When detection computer has abnormal power-down, then the letter of the CMOS on the replacement computer motherboard that outer circuits send is received
Number, to reset the CMOS, the outer circuits include power supply chip, when can so avoid EC from detecting abnormal power-down, suddenly
Power-off, causes to send the risk for resetting cmos signal failure.
Brief description of the drawings
RSMRST# signals power supply signal VCCPRIM signals corresponding with its when Fig. 1 is for abnormal power-down situation in the prior art
Figure；
Fig. 2 is the flow chart of the embodiment one of power-off protection method of the invention；
Fig. 3 is the flow chart of the embodiment two of power-off protection method of the invention；
Fig. 4 is the flow chart of the embodiment one of power-off protection apparatus of the invention；
Fig. 5 is the flow chart of the embodiment two of power-off protection apparatus of the invention；
Fig. 6 is the schematic diagram of the outer circuits of embodiment one of computer of the invention；
Fig. 7 is the RSMRST# signals and VCCPRIM signal schematic representations of the embodiment one of computer of the invention.
Specific embodiment
With reference to the accompanying drawings and examples, specific embodiment of the invention is described in further detail.Hereinafter implement
Example is not limited to the scope of the present invention for illustrating the present invention.
During the use of computer, sometimes there is situations below：Under power on mode, while removing power adaptation
Device and battery.In this case, to prevent from causing clock (Real-Time Clock, RTC) to damage, it is necessary to be supplied by power supply
Before each device voltage of electricity exceeds default normal range of operation, the RSMRST# signals of each device are cut off.Also imply that,
The supply voltage of south bridge cuts off the RSMRST# signals of south bridge less than before preset value.Fig. 1 is abnormal when occurring in the prior art
During power-off, RSMRST# signals power supply signal VCCPRIM schematic diagrames corresponding with its.
Wherein, RSMRST# signals are that south bridge returns to the reset signal for hanging up circuit.RSMRST# signals are for notifying south
The normal signal of bridge 5VSB and 3VSB standby voltage, if low, then south bridge receives error information to this signal, it is believed that corresponding
Standby voltage does not make a mistake, so the upper electronic work of next step will not be carried out.
VCCPRIM signals are power rail (power rail) signal of south bridge stand-by power supply (standby power), mainly
Rich sharp technology for supporting Intel.
As seen from Figure 1, RSMRST# signals decline earlier than VCCPRIM signals, but because RSMRST# signals decline
Duration is long, and this will cause, and has begun to have dropped in VCCPRIM signals, but RSMRST# signals have not been completed,
I.e. south bridge does not enter into hang-up logic.
By taking Intel chip as an example, the operating voltage of RSMRST# signals is -0.5V to 0.99V, that is to say, that to prevent
Have begun to have dropped in VCCPRIM signals, south bridge have not been entered into hang up logic this case that generation, it is necessary to
Before VCCPRIM signals decline, the voltage of RSMRST# signals is set to be not less than 0.99V.
Other method can also be used, prevents RTC from damaging the computer glitch for causing.Due to the configuration information of computer motherboard
Storage is in the CMOS of mainboard, it is therefore possible to use software mode, removes CMOS.When the situation that there is abnormal power-down, if embedded
Formula controller (Embed Controller, EC) still can be with normal work, and EC then sends reduction RTCRST# and SRTCRST# letters
The control instruction of number level, so that system recovers normal.But the information of CMOS in this way, is removed, computer will be made
In date also remove, user also needs to reset the time.
Analysis based on more than, it is as follows that the present invention provides embodiment：
Fig. 2 is the flow chart of the embodiment one of power-off protection method of the invention, as shown in Fig. 2 the power-off of the present embodiment
Guard method, specifically may include steps of：
S201, detection computer whether there is abnormal power-down；If in the presence of, step S202 is performed, otherwise, then perform step
S203。
S202, resets CMOS, and reset signal comes from the outer circuits for including power supply chip.
Specifically, it is also possible to reset CMOS by EC, but when abnormal power-down, it is possible to which EC is not sending replacement also
During instruction, just not enough power supply cannot send the instruction for resetting CMOS.And the present embodiment resets computer by outer circuits
CMOS on mainboard, power supply chip is provided with outer circuits, it is ensured that can send the instruction for resetting CMOS.
S203, starts computer.
Specifically, it is normal to start computer if not there is abnormal power-down situation.
Involved computer includes notebook computer, desktop computer and equipment etc. server in this implementation.
The technical scheme of the embodiment of the present invention receives what outer circuits sent when detecting that computer has abnormal power-down, then
The signal of the CMOS on computer motherboard is reset, to reset CMOS, outer circuits include power supply chip, can so avoid EC from examining
When surveying abnormal power-down, power-off suddenly causes to send the risk for resetting cmos signal failure.
Fig. 3 is the flow chart of the embodiment two of power-off protection method of the invention, and the power-off protection method of the present embodiment exists
On the basis of above-described embodiment one, technical scheme is further introduced in further detail.As shown in figure 3, the present embodiment
Power-off protection method, specifically may include steps of：
S301, detection computer whether there is abnormal power-down；If in the presence of, step S302 is performed, otherwise, perform step
S304。
S302, receives and wakes up the reset signal that south bridge hangs up logic.
Specifically, five conditions of south bridge need of work：(1)+3V standby voltages；(2) reset signal RSMRST# is recovered, should
When signal is low level effectively, the signal is used for the sleep awakening logic of south bridge of resetting, when RSMRST# signals are if low electricity
Flat, then south bridge ACPI controller cannot go up electricity in reset state all the time；(3) RTC, real-time clock；(4) RTCRST, uses reflex
Logic circuit inside the south bridge of position；(5)CLK(32.768KHZ).It can be seen that, the reset signal that south bridge hangs up logic is waken up, i.e., southwards
Bridge sends RSMRST# signals.
Specifically, step S302, including：A, the first predetermined level is set to by reset signal；B, the first predetermined level is held
After continuous Preset Time, reset signal is set to the second predetermined level；Second predetermined level is higher than the first predetermined level.Namely
Say that the level of RSMRST# signals is first reduced draws high again.In the specific implementation, the first predetermined level, is 0.5V, the second default electricity
It is 0.99V to put down.
S303, receives the control signal for starting south bridge stand-by power supply.
Specifically, S303 includes：C, after reset signal is set into the second predetermined level, receives the standby electricity for starting south bridge
The control signal in source.
The control signal for starting south bridge stand-by power supply is VCCPRIM signals.
S304, starts computer.
Specifically, it is normal to start computer if not there is abnormal power-down situation.
Involved computer includes notebook computer, desktop computer and equipment etc. server in this implementation.
The technical scheme of the embodiment of the present invention receives what outer circuits sent when detecting that computer has abnormal power-down, then
The signal of the CMOS on computer motherboard is reset, to reset CMOS, outer circuits include power supply chip, can so avoid EC from examining
When surveying abnormal power-down, power-off suddenly causes to send the risk for resetting cmos signal failure.
Fig. 4 is the schematic diagram of the embodiment one of power-off protection apparatus of the invention, as shown in figure 4, the power-off of the present embodiment
Protection device, can specifically include detection module 41 and receiver module 43.
Detection module 41, is configured to detection computer and whether there is abnormal power-down.
Receiver module 42, is configured to, when computer has abnormal power-down, receive the replacement computer that outer circuits send
The signal of the CMOS on mainboard, to reset CMOS；Outer circuits include power supply chip.
The power-off protection apparatus of the present embodiment, by the realization mechanism for carrying out power-off protection to computer using above-mentioned module
Realization mechanism with the power-off protection method of above-mentioned embodiment illustrated in fig. 2 is identical, and above-mentioned embodiment illustrated in fig. 2 is may be referred in detail
Record, will not be repeated here.
Fig. 5 is the schematic diagram of the embodiment two of power-off protection apparatus of the invention, and the power-off protection apparatus of the present embodiment exist
On the basis of embodiment one as shown in Figure 4, technical scheme is further introduced in further detail.As shown in figure 5, this
The power-off protection apparatus of embodiment, can further include：
Receiver module 42, including：
First receiving submodule 421, is configured to receive the reset signal for waking up south bridge hang-up logic；
Second receiving submodule 422, is configured to receive the control signal for starting south bridge stand-by power supply.
Further, the first receiving submodule 421, including：
First sets submodule, is configured to for reset signal to be set to the first predetermined level；
Second sets submodule, after being configured to the lasting Preset Time of the first predetermined level, reset signal is set into second
Predetermined level；Second predetermined level is higher than the first predetermined level.
Further, the second receiving submodule 422, including：
3rd receiving submodule, after being configured to for reset signal to be set to the second predetermined level, receives and starts the standby of south bridge
With the control signal of power supply.
The power-off protection apparatus of the present embodiment, machine is realized by using above-mentioned module to carry out power-off protection to computer
System is identical with the realization mechanism of the power-off protection method of above-mentioned embodiment illustrated in fig. 3, may be referred to implement shown in above-mentioned Fig. 3 in detail
The record of example, will not be repeated here.
The present invention also provides a kind of computer, and the computer includes the device as shown in Fig. 4 to 5, the mainboard of the computer
Upper to include outer circuits, the outer circuits are configured to send the control signal for resetting the CMOS on computer motherboard.
As shown in fig. 6, outer circuits include the first FET Q1, the second FET Q2, first resistor R1With the second electricity
Resistance R2；First FET Q1Grid receive MPWRG signals, the first FET Q1Source electrode connection first resistor R1
One end, first resistor R1The second end connection power supply VCC, the first FET Q1Source electrode be also connected with the second FET Q2's
Grid, the first FET Q1Grounded drain, the second FET Q2Grounded drain, the second FET Q2Source electrode connect
Meet second resistance R2First end, second resistance R2The second end output RSMRST# signals.
Wherein, MPWRG signals are sent to the power supply signal of south bridge for power supervisor, to notify south bridge voltage normal.When
MPWRG signals are high level, then the first FET Q1Grid receive high level signal, its source electrode and drain electrode turn on, power supply
By first resistor R1With the first FET Q1Start electric discharge, the second FET Q2Grid be low level, therefore,
RSMRST# signals remain high level signal；When there is abnormal power-down, MPWRG signals will be changed into low level, the first field-effect
Pipe Q1Source electrode and drain electrode be not turned on, the second FET Q2Grid receive high level signal, its source electrode and drain electrode turn on, this
When, RSMRST# signals are changed into low level signal.
As shown in fig. 7, after by above-mentioned outer circuits control RSMRST# signals, when notebook abnormal power-down,
RSMRST# signal voltages decline, but can be quickly raised to more than 0.99V before the decline of VCCPRIM signals, and south bridge exists
RSMRST# signals will enter when having fluctuation hangs up logic, and will not so remove the information stored in CMOS.
Above example is only exemplary embodiment of the invention, is not used in the limitation present invention, protection scope of the present invention
It is defined by the claims.Those skilled in the art can make respectively in essence of the invention and protection domain to the present invention
Modification or equivalent are planted, this modification or equivalent also should be regarded as being within the scope of the present invention.
Claims (10)
1. a kind of power-off protection method, it is characterised in that including：
Detection computer whether there is abnormal power-down；
If in the presence of, CMOS is reset, and reset signal comes from the outer circuits for including power supply chip.
2. method according to claim 1, it is characterised in that then reset CMOS, including：
Receive and wake up the reset signal that south bridge hangs up logic；
Receive the control signal for starting south bridge stand-by power supply.
3. method according to claim 2, it is characterised in that receive and wake up the reset signal that south bridge hangs up logic, including：
The reset signal is set to the first predetermined level；
After first predetermined level continues Preset Time, the reset signal is set to the second predetermined level；Described second
Predetermined level is higher than first predetermined level.
4. method according to claim 3, it is characterised in that receive the control signal for starting south bridge stand-by power supply, including：
After the reset signal is set into the second predetermined level, the control signal of the stand-by power supply for starting the south bridge is received.
5. a kind of power-off protection apparatus, it is characterised in that including：
Detection module, is configured to detection computer and whether there is abnormal power-down；
Receiver module, is configured to be reset when the computer has abnormal power-down the signal of CMOS, and reset signal comes from
The one outer circuits for including power supply chip.
6. device according to claim 5, it is characterised in that the receiver module, including：
First receiving submodule, is configured to receive the reset signal for waking up south bridge hang-up logic；
Second receiving submodule, is configured to receive the control signal for starting south bridge stand-by power supply.
7. device according to claim 6, it is characterised in that first receiving submodule, including：
First sets submodule, is configured to for the reset signal to be set to the first predetermined level；
Second sets submodule, after being configured to the lasting Preset Time of first predetermined level, the reset signal is set to
Second predetermined level；Second predetermined level is higher than first predetermined level.
8. device according to claim 7, it is characterised in that second receiving submodule, including：
3rd receiving submodule, after being configured to for the reset signal to be set to the second predetermined level, receives and starts the south bridge
Stand-by power supply control signal.
9. a kind of computer, it is characterised in that the computer includes the device as any one of claim 5 to 8, institute
Stating includes outer circuits on the mainboard of computer, the outer circuits are configured to send the CMOS reset on the computer motherboard
Control signal.
10. computer according to claim 9, it is characterised in that the outer circuits include the first FET, second
FET, first resistor and second resistance；The grid of first FET receives MPWRG signals, first effect
Should the source electrode of pipe connect the first end of the first resistor, the second end connection power supply of the first resistor, first effect
Should the source electrode of pipe be also connected with the grid of second FET, the grounded drain of first FET, described second
The grounded drain of effect pipe, the source electrode of second FET connects the first end of the second resistance, the second resistance
The second end output RSMRST signals.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710043719.7A CN106708237B (en) | 2017-01-19 | 2017-01-19 | Power-off protection method, device and computer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710043719.7A CN106708237B (en) | 2017-01-19 | 2017-01-19 | Power-off protection method, device and computer |
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| CN106708237A true CN106708237A (en) | 2017-05-24 |
| CN106708237B CN106708237B (en) | 2019-11-12 |
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| CN101038563A (en) * | 2006-03-17 | 2007-09-19 | 联想(北京)有限公司 | Method and device remotely automatic recovering CMOS date with network |
| CN201503569U (en) * | 2009-09-02 | 2010-06-09 | 鸿富锦精密工业（深圳）有限公司 | South bridge chip power supply circuit |
| CN102981585A (en) * | 2011-09-06 | 2013-03-20 | 鸿富锦精密工业（深圳）有限公司 | Complementary metal-oxide-semiconductor (CMOS) chip information clear circuit |
| CN103064486A (en) * | 2011-10-18 | 2013-04-24 | 纬创资通股份有限公司 | Computer device and method for resetting real-time clock signal thereof |
| CN105759663A (en) * | 2014-12-16 | 2016-07-13 | 研祥智能科技股份有限公司 | Industrial equipment monitoring processing method and system thereof |
-
2017
- 2017-01-19 CN CN201710043719.7A patent/CN106708237B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101038563A (en) * | 2006-03-17 | 2007-09-19 | 联想(北京)有限公司 | Method and device remotely automatic recovering CMOS date with network |
| CN201503569U (en) * | 2009-09-02 | 2010-06-09 | 鸿富锦精密工业（深圳）有限公司 | South bridge chip power supply circuit |
| CN102981585A (en) * | 2011-09-06 | 2013-03-20 | 鸿富锦精密工业（深圳）有限公司 | Complementary metal-oxide-semiconductor (CMOS) chip information clear circuit |
| CN103064486A (en) * | 2011-10-18 | 2013-04-24 | 纬创资通股份有限公司 | Computer device and method for resetting real-time clock signal thereof |
| CN105759663A (en) * | 2014-12-16 | 2016-07-13 | 研祥智能科技股份有限公司 | Industrial equipment monitoring processing method and system thereof |
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