CN106684219A - LED chip structure and processing method thereof - Google Patents
LED chip structure and processing method thereof Download PDFInfo
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- CN106684219A CN106684219A CN201710053641.7A CN201710053641A CN106684219A CN 106684219 A CN106684219 A CN 106684219A CN 201710053641 A CN201710053641 A CN 201710053641A CN 106684219 A CN106684219 A CN 106684219A
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- 238000003672 processing method Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 84
- 230000004888 barrier function Effects 0.000 claims description 52
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 45
- 239000010931 gold Substances 0.000 claims description 45
- 229910052737 gold Inorganic materials 0.000 claims description 45
- 238000009413 insulation Methods 0.000 claims description 29
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 19
- 238000009792 diffusion process Methods 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000007480 spreading Effects 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910017083 AlN Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052593 corundum Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000004062 sedimentation Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000011514 reflex Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
- H01L33/60—Reflective elements
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention discloses an LED chip structure and a processing method thereof. The LED chip structure comprises a first semiconductor layer, a second semiconductor layer and a multiple quantum well layer, wherein the multiple quantum well is arranged between the first semiconductor layer and the second semiconductor layer, a transparent conductive layer, a reflection insulating layer and a first current expansion reflection layer are arranged on the first semiconductor layer in a layer-by-layer manner, a plurality of first through holes are distributed in the reflection insulating layer, the first current expansion reflection layer is provided with first conductive columns extending into the first through holes, and the first conductive columns are in conductive contact with the transparent conductive layer. The LED chip structure is good in current diffusion effect.
Description
Technical field
The present invention relates to technical field of semiconductor device, more particularly, it relates to a kind of LED chip structure and its processing side
Method.
Background technology
LED chip is also referred to as LED luminescence chips, and its major function is that electric energy is converted into luminous energy, and its core is quasiconductor
Chip, the semiconductor wafer is made up of P, N the two poles of the earth, and wherein P extremely P-type semiconductor, its inner cavity are occupied an leading position, N extremely N
Type quasiconductor, its internal electron are occupied an leading position.When electric current acts on this semiconductor wafer by conductor, N extremely in
Electronics will be pushed to P poles, after electronics is with hole-recombination, energy then will be sent in the form of photon.
In prior art, the current spread at P, N the two poles of the earth of LED chip is all to extend bar diffusion, this kind of structure by metal
In current spread, electrons to metal extension bar is concentrated around, and diffusion effect is poor.
Therefore, how to solve the problems, such as that current spreading effect is poor in LED chip in prior art, become art technology
Personnel's important technological problems to be solved.
The content of the invention
In view of this, it is an object of the invention to provide a kind of LED chip structure, its current spreading effect is preferable.This
Bright purpose is also resided in and provides a kind of processing method of LED chip.
A kind of LED chip structure that the present invention is provided, including the first semiconductor layer, the second semiconductor layer and positioned at described
Multiple quantum well layer between first semiconductor layer and second semiconductor layer, is successively provided with transparent on first semiconductor layer
Conductive layer, reflective isolating layer and the first current expansion reflecting layer, are distributed with multiple first through hole on the reflective isolating layer, described
There is the first conductive pillar structure and the transparency conducting layer that stretch in the first through hole to lead in the first current expansion reflecting layer
Electrical contact.
Preferably, also include the reflective isolating layer, the transparency conducting layer, first semiconductor layer and described many
Multiple second through holes that quantum well layer runs through, and the second current expansion reflecting layer on reflective isolating layer upper strata is arranged on, it is described
Second current expansion reflecting layer have be inserted into the second conductive pillar structure in second through hole, with second quasiconductor
Layer conductive contact, and the reflective isolating layer extended between the hole wall of second conductive pillar structure and second through hole.
Preferably, the transparency conducting layer is internally provided with for preventing the electric current flowed into by the first through hole from vertically noting
Enter the insulation barrier structure in first semiconductor layer.
Preferably, the insulation barrier structure is multiple and aligns setting one by one with the first through hole.
Preferably, cross section of the cross section of the insulation barrier structure more than the first through hole.
Preferably, the reflective isolating layer is by the transparency conducting layer, first semiconductor layer, the multiple quantum well layer
And the side of second semiconductor layer seals.
Preferably, the transparency conducting layer, first semiconductor layer, the multiple quantum well layer and described the second half lead
The side of body layer is provided with ledge structure, and the reflective isolating layer is enclosed on the ledge structure.
Preferably, also include being located at the substrate layer of the second semiconductor layer bottom.
Preferably, also include being located at the first current expansion reflecting layer and the second current expansion reflecting layer upper strata
Insulating barrier and the first altogether layer gold and the second layer gold altogether positioned at the insulating barrier upper strata, the described first layer gold and described the altogether
Two common layer gold are respectively by the be arranged on the insulating barrier first common gold through hole and the second common gold through hole and first electric current
Spread reflection layer and the second current expansion reflecting layer electrically connect.
Present invention also offers a kind of processing method of LED chip, including step：
Multiple steps are processed on the epitaxial wafer with the first semiconductor layer, multiple quantum well layer and the second semiconductor layer,
The step runs through first semiconductor layer and the multiple quantum well layer, to expose second semiconductor layer；
Multiple insulation barrier structures are formed on first semiconductor layer；
Transparency conducting layer is formed on the upper strata of first semiconductor layer, the transparency conducting layer ties the insulation barrier
Structure is coated on inside it, and the through hole corresponding with the step is processed on the transparency conducting layer；
Reflective isolating layer is formed on the upper strata of the transparency conducting layer, and make that reflective isolating layer injection is described transparent to be led
In the through hole of electric layer, process on the reflective isolating layer first through hole corresponding with the insulation barrier locations of structures,
And second through hole corresponding with the stepped locations；
The first current expansion reflecting layer and the second current expansion reflecting layer are formed on the upper strata of the reflective isolating layer, it is described
There is gap between first current expansion reflecting layer and the second current expansion reflecting layer, and first current expansion reflects
Layer is contacted by first through hole with the transparency conducting layer, and the second current expansion reflecting layer is by second through hole and institute
State the second semiconductor layer to contact.
Preferably, before the upper strata of the transparency conducting layer forms reflective isolating layer, also including step：In the extension
Ledge structure is processed on the side of piece；When the upper strata of the transparency conducting layer forms reflective isolating layer, make the reflection exhausted
Edge layer is surrounded on the ledge structure.
Preferably, also including step：
Insulating barrier, and the insulating barrier are formed on the upper strata in the first current expansion reflecting layer and the second current expansion reflecting layer
The side in the first current expansion reflecting layer and the second current expansion reflecting layer is surrounded；
The common gold through hole of first for being run through, the second common gold through hole are processed on the insulating barrier and positioned at described exhausted
The first of edge layer upper strata altogether layer gold and the second layer gold altogether, described first altogether layer gold and described second altogether layer gold respectively by described the
Altogether golden through hole and the second common gold through hole are electrically connected with the first current expansion reflecting layer and the second current expansion reflecting layer
Connect.
In the technical scheme that the present invention is provided, transparency conducting layer, reflection are successively provided with absolutely on the upper strata of the first semiconductor layer
Edge layer and the first current expansion reflecting layer, it should be noted that " upper strata " " lower floor " that be referred to herein refers to the second quasiconductor
Layer is located at bottom, multiple quantum well layer and is located at when the second semiconductor layer, the first semiconductor layer are located on multiple quantum well layer
Indication on the basis of state.Transparency conducting layer is located at the upper strata of the first semiconductor layer, reflective isolating layer and is located at transparency conducting layer
Upper strata, the first current expansion reflecting layer are located at the upper strata of reflective isolating layer.Wherein, reflective isolating layer has and is capable of reflecting light, absolutely
The characteristic of edge, transparency conducting layer has transparent, conductive characteristic, and current expansion reflecting layer has the conductive, characteristic of reflected light.Instead
Penetrate on insulating barrier and multiple first through hole be distributed with, the first current expansion reflecting layer have stretch to it is first conductive in first through hole
Rod structure and transparency conducting layer conductive contact.It is arranged such, is spread by the first current expansion reflecting layer first when electric current injects
To the whole surface of chip, reflective isolating layer can prevent electric current from being directly injected into transparency conducting layer, but by reflective isolating
The multiple first through hole being distributed on layer are uniformly injected into transparency conducting layer, it is to avoid current convergence is in injection phase, and electric current is uniform
After being injected into transparency conducting layer, further spread in the transparent conductive layer, and then electric current can be made uniformly to be diffused into
In semi-conductor layer.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the entirety sectional view of LED chip structure in the embodiment of the present invention；
Fig. 2 is the structural representation formed after LED chip S1 procedure of processing in the embodiment of the present invention；
Fig. 3 is the schematic diagram that the N-GaN layers exposed in the embodiment of the present invention are uniformly arranged；
Fig. 4 is the front arrangement schematic diagram of insulation barrier structure in the embodiment of the present invention；
Fig. 5 is the structural representation formed after S3 steps in the embodiment of the present invention；
Fig. 6 is the structural representation formed after S4 steps in the embodiment of the present invention；
Fig. 7 is the distribution schematic diagram of first through hole and the second through hole in the embodiment of the present invention；
Fig. 8 is the final finished surface schematic diagram of LED chip in the embodiment of the present invention；
Fig. 9 is LED chip structure schematic diagram in present invention another kind embodiment；
In Fig. 1-Fig. 9：
First semiconductor layer -11, the second semiconductor layer -12, multiple quantum well layer -13, transparency conducting layer -14, reflection
Insulating barrier -15, the first current expansion reflecting layer -16, first through hole -17, the second through hole -18, the reflection of the second current expansion
Layer -19, insulation barrier structure -20, ledge structure -21, substrate layer -22, insulating barrier -23, first altogether layer gold -24, the
Two common layer gold -25, ohmic contact layer -26, the first common gold through hole -27, the second common gold through hole -28.
Specific embodiment
The purpose of this specific embodiment is to provide a kind of LED chip structure, and its current spreading effect is preferable.This is concrete
The purpose of embodiment is also resided in and provides a kind of processing method of LED chip.
Hereinafter, embodiment is illustrated referring to the drawings.Additionally, embodiments illustrated below is not to described in claim
The content of the invention rise any restriction effect.In addition, the full content of the composition represented by example below is not limited to as right
Necessary to requiring the solution of described invention.
Refer to Fig. 1, a kind of LED chip structure that the present embodiment is provided, including the first semiconductor layer 11, the second quasiconductor
Layer 12 and the multiple quantum well layer 13 between the first semiconductor layer 11 and second semiconductor layer 12.
In the present embodiment, the first semiconductor layer 11 is P-GaN layers, and the second semiconductor layer 12 is N-GaN layers.Certainly, at it
In its embodiment, the first semiconductor layer 11 is alternatively N-GaN layers, and the second semiconductor layer 12 is P-GaN layers.
For the ease of description, the second semiconductor layer 12 is set to be located at bottom as shown in Figure 1, multiple quantum well layer 13 is located at the second half
The upper strata of conductor layer 12, the first semiconductor layer 11 is located at the upper strata of multiple quantum well layer 13, hereinafter will be entered on the basis of this state
Row description, it should be noted that " upper strata ", the description of " lower floor " herein, does not constitute the concrete restriction to this programme, when
When LED chip is in other placement states, each layer " on " D score position can also occur respective change.
In the present embodiment, transparency conducting layer 14, reflective isolating layer 15 and first are successively provided with the first semiconductor layer 11 electric
Stream spread reflection layer 16, i.e. transparency conducting layer 14 are located at the upper strata of the first semiconductor layer 11, and reflective isolating layer 15 is located at transparent leading
The upper strata of electric layer 14, the first current expansion reflecting layer 16 is located at the upper strata of reflective isolating layer 15.Wherein, reflective isolating layer 15 has
The characteristic for be capable of reflecting light, insulating, transparency conducting layer 14 has transparent, conductive characteristic, and the first current expansion reflecting layer 16 has
There are conduction, the characteristic of reflected light.
It is distributed with multiple first through hole 17 on reflective isolating layer 15, the first current expansion reflecting layer 16 has and stretches to first
The first conductive pillar structure and the conductive contact of transparency conducting layer 14 in through hole 17, specifically, the first current expansion reflecting layer 16 can
By sedimentation, to be formed in the surface of reflective isolating layer 15, can the above-mentioned first conductive pole knot of self-assembling formation in deposition process
Structure.The distribution form of first through hole 17 can specifically set according to practical situation, specifically not limited herein.
It is arranged such, first the whole surface of chip is diffused into by the first current expansion reflecting layer 16 when electric current injects,
Reflective isolating layer 15 can prevent electric current from being directly injected into transparency conducting layer 14, but many by what is be distributed on reflective isolating layer 15
Individual first through hole 17 is uniformly injected into transparency conducting layer 14, it is to avoid current convergence is uniformly injected in injection phase, electric current
After bright conductive layer 14, further spread in transparency conducting layer 14, and then electric current can be made uniformly to be diffused into the first half
In conductor layer 11.
In addition, the current expansion reflecting layer 16 of reflective isolating layer 15 and first together form complete reflecting surface, formed compared with
Good omnidirectional reflection effect.
The LED chip structure that the present embodiment is provided, can also be included reflective isolating layer 15, transparency conducting layer 14, first
Multiple second through holes 18 that semiconductor layer 11 and multiple quantum well layer 13 run through, and be arranged on the upper strata of reflective isolating layer 15 second
Current expansion reflecting layer 19.
Wherein, the distribution form and distribution density of multiple second through holes 18 can specifically set according to practical situation.
And, the second current expansion reflecting layer 19 have be inserted in the second through hole 18 the second conductive pillar structure, with
The conductive contact of second semiconductor layer 12.Equally, the second current expansion reflecting layer 19 has conductive, light-reflecting property.Second electric current expands
Extensor reflex layer 19 also can be formed in the surface of reflective isolating layer 15 by sedimentation, and above-mentioned second can be simultaneously formed in deposition process
Conductive pillar structure.
In order to realize good conductive contact, above-mentioned second conductive pillar structure can be by ohmic contact layer 26 and the second half
Conductor layer 12 realizes conductive contact, certainly, ensure that it is good that the second conductive pillar structure and the second semiconductor layer 12 have
On the basis of conductive contact, the second conductive pillar structure can also be contacted with the direct conduction of the second semiconductor layer 12, as shown in Figure 9.
Additionally, being provided with reflective insulating material between the inwall of the second conductive pillar structure and the second through hole 18, can avoid
There is conduction between second conductive pillar structure and multiple quantum well layer 13, the first semiconductor layer 11, transparency conducting layer 14, while ensureing
The reflecting effect of the position.
It is arranged such, electric current is injected after the second semiconductor layer 12, by the second conductive pillar structure in multiple second through holes 18
Derive to the second current expansion reflecting layer 19, CURRENT DISTRIBUTION has preferable uniformity.Therefore, the technical side that the present embodiment is provided
In case, the current spread of the first semiconductor layer 11 and the second semiconductor layer 12 all has good uniformity.
Further, in the present embodiment, transparency conducting layer 14 is internally provided with for preventing what is flowed into by first through hole 17
Insulation barrier structure 20 in the first semiconductor layer of electric current vertical injection 11.Above-mentioned " vertical injection " is referred to and led perpendicular to the first half
The direction in body surface face, insulation barrier structure 20 has insulation characterisitic, can play barrier effect to electric current, and then makes electric current to flat
Row spreads in the direction of the first semiconductor layer 11, improves diffusion effect.
Above-mentioned insulation barrier structure 20 can be multiple and align setting one by one with first through hole 17.It is arranged such, by every
The electric current of the injection of individual first through hole 17 can all be subject to the vertical barrier effect of insulation barrier structure 20, force electric current to parallel to the
The direction diffusion of semi-conductor layer 11.Further, in order to improve diffusion effect, the cross section of insulation barrier structure 20 is more than the
The cross section of one through hole 17, so, insulation barrier structure 20 can play more preferable insulation barrier effect, improve current spread effect
Really.
Reflective isolating layer 15 has insulation characterisitic, and in order to avoid the electric leakage in side direction of LED chip, in the present embodiment, reflection is exhausted
Edge layer 15 is close by the side of transparency conducting layer 14, the first semiconductor layer 11, the semiconductor layer 12 of multiple quantum well layer 13 and second
Envelope.It is possible to further in above-mentioned transparency conducting layer 14, the first semiconductor layer 11, the quasiconductor of multiple quantum well layer 13 and second
The side of layer 12 is provided with ledge structure 21, and reflective isolating layer 15 is enclosed on ledge structure 21.Specifically, etching can be passed through
Method forms above-mentioned ledge structure 21, and forms above-mentioned reflective isolating layer 15 by sedimentation.It is arranged such, structure can be formed tight
Gather, the LED chip structure that rationally distributed, reflecting effect is good, anti-electric leakage effect is good.
In addition, the LED chip structure that the present embodiment is provided also includes being located at the substrate layer 22 of the bottom of the second semiconductor layer 12,
The substrate layer 22 is specifically as follows Sapphire Substrate.
And, the LED chip structure can also include being located at the first current expansion reflecting layer 16 and the second current expansion is anti-
Penetrate the insulating barrier 23 on the upper strata of layer 19 and be total to the layer gold 25 altogether of layer gold 24 and second positioned at the first of the upper strata of insulating barrier 23, first is total to
Layer gold 24 is electrically connected by the be arranged on insulating barrier 23 first common gold through hole 27 with the first current expansion reflecting layer 16, and second is total to
Also by second be arranged on insulating barrier 23, altogether gold through hole 28 is electrically connected layer gold 25 with the second current expansion reflecting layer 19.
Altogether layer gold 25 is conductively connected respectively first common layer gold 24 and second with the both positive and negative polarity of extraneous power supply, and so, first is total to
Altogether layer gold 25 can realize conductive company to layer gold 24 and second with the first current expansion reflecting layer 16 and the second spread reflection layer respectively
Connect, and electric current can realize preferably diffusion.
The present embodiment additionally provides a kind of processing method for processing above-mentioned LED chip structure, including step：
S1, on the epitaxial wafer for growing effective epitaxial structure, carves on the first semiconductor layer 11 and multiple quantum well layer 13
Lose step, expose the second semiconductor layer 12 of the lower section of the first semiconductor layer 11, in the present embodiment, the first semiconductor layer 11 can
Think P-GaN layers, the second semiconductor layer 12 can be N-GaN layers；The N-GaN layers for exposing are evenly spaced in whole chip surface
It is uniformly injected into increasing electric current, its distribution form can be as shown in figure 3, wherein above-mentioned step size, quantity, position of arranging
The practical situation that putting can make technique according to epitaxial structure and chip is adjusted to reach optimal current spreading effect.In core
The periphery of piece forms ledge structure 21 using sapphire substrate surface is etched into.Structure as shown in Figure 2 is formed after this step.
S2, multiple insulation barrier structures 20 are formed on the epitaxial wafer of said structure by way of being deposited with and etching,
The insulation barrier structure 20 is specifically as follows the bulge-structure of P-GaN layer upper surfaces, and its position is with follow-up for the injection of P electric currents
The position of first through hole 17 correspondence and cross section be slightly larger than first through hole 17, to reduce the vertical injection of electric current.The insulation barrier
The material of structure 20 is insulant, usually SiO2, Al2O3, TiO2, AlN, Si3N4Deng.The front of the insulation barrier structure 20
Arrangement can be using as shown in Figure 4.The wherein size of insulation barrier structure 20, quantity, arrangement position can be according to epitaxial structure and core
Piece makes the practical situation of technique and is adjusted to reach optimal current spreading effect.
S3, forms saturating by way of being deposited with and etching in P-GaN layer surfaces and the top of insulation barrier structure 20
Bright conductive layer 14, the transparency conducting layer 14 is, in order to further increase the horizontal proliferation of electric current, to reduce the vertical injection of electric current.Should
The material of transparency conducting layer 14 is usually ITO, ZnO, AZO, TiN etc..In the platform of N-GaN layers by way of being deposited with and peeling off
Rank bottom surface forms ohmic contact layer 26, and certainly, in other embodiments, the ohmic contact layer 26 also can be omitted.After the step
Structure it is as shown in Figure 5.
S4, is deposited with reflective isolating layer 15 on said structure, and the reflective isolating layer 15 is by SiO2, Al2O3, TiO2, AlN,
Si3N4It is alternately stacked to be formed Deng two or more in material.Recycle etching technics to get in the reflective isolating layer 15 and supply P
The through hole 18 of first through hole 17 and second injected with the electric current of N.Recycle evaporation and method formation the first electric current expansion peeled off
The current expansion reflecting layer 19 of extensor reflex layer 16 and second.First current expansion reflecting layer 16 and the second current expansion reflecting layer 19
The bottom is by the higher metal material of reflectance, such as Ag, Al composition, to reach preferable reflecting effect.Formed such as after the step
Structure shown in Fig. 6.The distribution schematic diagram of the through hole 18 of first through hole 17 and second formed in the step can be as shown in Figure 7.
S5, is deposited with again insulating barrier 23 in the structure of above-mentioned formation, and the material of the insulating barrier 23 is usually SiO2, Al2O3,
TiO2, AlN, Si3N4In one or more, recycle etch process that the first altogether gold He of through hole 27 is got in the insulating barrier 23
Second common golden through hole 28, altogether golden through hole 28 is respectively used to the common layer gold of P, N to the first current expansion to the first common gold through hole 27 and second
The electric current injection in the current expansion reflecting layer 19 of reflecting layer 16 and second.Finally form P, N using evaporation and the method peeled off common
Layer gold, forms the final structure of the present embodiment LED chip structure, as shown in Figure 8.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
Various modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, the present invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope for causing.
Claims (12)
1. a kind of LED chip structure, including the first semiconductor layer, the second semiconductor layer and positioned at first semiconductor layer and
Multiple quantum well layer between second semiconductor layer, it is characterised in that be successively provided with transparent leading on first semiconductor layer
Electric layer, reflective isolating layer and the first current expansion reflecting layer, are distributed with multiple first through hole on the reflective isolating layer, and described
One current expansion reflecting layer is with the first conductive pillar structure stretched in the first through hole, to lead with the transparency conducting layer
Electrical contact.
2. LED chip structure as claimed in claim 1, it is characterised in that also include the reflective isolating layer, described transparent
Multiple second through holes that conductive layer, first semiconductor layer and the multiple quantum well layer run through, and it is arranged on reflective isolating
The second current expansion reflecting layer on layer upper strata, the second current expansion reflecting layer has the be inserted in second through hole
Two conductive pillar structures, with the second semiconductor layer conductive contact, and the reflective isolating layer to extend to described second conductive
Between the hole wall of rod structure and second through hole.
3. LED chip structure as claimed in claim 1, it is characterised in that the transparency conducting layer is internally provided with for hindering
Insulation barrier structure in first semiconductor layer described in the electric current vertical injection for only being flowed into by the first through hole.
4. LED chip structure as claimed in claim 3, it is characterised in that the insulation barrier structure for it is multiple and with it is described
First through hole aligns one by one setting.
5. LED chip structure as claimed in claim 4, it is characterised in that the cross section of the insulation barrier structure is more than institute
State the cross section of first through hole.
6. the LED chip structure as described in any one of claim 1-6, it is characterised in that the reflective isolating layer will be described
The side of bright conductive layer, first semiconductor layer, the multiple quantum well layer and second semiconductor layer seals.
7. LED chip structure as claimed in claim 6, it is characterised in that the transparency conducting layer, first quasiconductor
The side of layer, the multiple quantum well layer and second semiconductor layer is provided with ledge structure, and the reflective isolating layer is enclosed in
On the ledge structure.
8. LED chip structure as claimed in claim 1, it is characterised in that also include being located at the second semiconductor layer bottom
Substrate layer.
9. LED chip structure as claimed in claim 2, it is characterised in that also include being reflected positioned at first current expansion
The insulating barrier on layer and the second current expansion reflecting layer upper strata and the first altogether layer gold and the positioned at the insulating barrier upper strata
Two common layer gold, the described first common layer gold and the second common layer gold are led to respectively by the be arranged on the insulating barrier first common gold
Hole and the second common gold through hole are electrically connected with the first current expansion reflecting layer and the second current expansion reflecting layer.
10. a kind of processing method of LED chip, it is characterised in that including step：
Multiple steps are processed on the epitaxial wafer with the first semiconductor layer, multiple quantum well layer and the second semiconductor layer, it is described
Step runs through first semiconductor layer and the multiple quantum well layer, to expose second semiconductor layer；
Multiple insulation barrier structures are formed on first semiconductor layer；
Transparency conducting layer is formed on the upper strata of first semiconductor layer, the transparency conducting layer is by the insulation barrier structure bag
It is overlying on inside it, and the through hole corresponding with the step is processed on the transparency conducting layer；
Reflective isolating layer is formed on the upper strata of the transparency conducting layer, and makes the reflective isolating layer inject the transparency conducting layer
Through hole in, process on the reflective isolating layer first through hole corresponding with the insulation barrier locations of structures and with
The second corresponding through hole of the stepped locations；
The first current expansion reflecting layer and the second current expansion reflecting layer are formed on the upper strata of the reflective isolating layer, described first
There is gap between current expansion reflecting layer and the second current expansion reflecting layer, and the first current expansion reflecting layer is logical
Cross first through hole to contact with the transparency conducting layer, the second current expansion reflecting layer is by second through hole and described the
Two semiconductor layers contact.
The processing method of 11. LED chips as claimed in claim 10, it is characterised in that on the upper strata of the transparency conducting layer
Before forming reflective isolating layer, also including step：Ledge structure is processed on the side of the epitaxial wafer；Transparent lead described
When the upper strata of electric layer forms reflective isolating layer, the reflective isolating layer is set to be surrounded on the ledge structure.
The processing method of 12. LED chips as claimed in claim 10, it is characterised in that also including step：
On the upper strata in the first current expansion reflecting layer and the second current expansion reflecting layer insulating barrier, and the insulating barrier are formed by institute
The side for stating the first current expansion reflecting layer and the second current expansion reflecting layer surrounds；
The common gold through hole of first for being run through, the second common gold through hole are processed on the insulating barrier and on the insulating barrier
The first of layer altogether layer gold and the second layer gold altogether, described first altogether layer gold and described second altogether layer gold respectively by the described first gold altogether
Through hole and the second common gold through hole are electrically connected with the first current expansion reflecting layer and the second current expansion reflecting layer.
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