CN106684091A - Display panel, array substrate and manufacturing method of array substrate - Google Patents
Display panel, array substrate and manufacturing method of array substrate Download PDFInfo
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- CN106684091A CN106684091A CN201610289121.1A CN201610289121A CN106684091A CN 106684091 A CN106684091 A CN 106684091A CN 201610289121 A CN201610289121 A CN 201610289121A CN 106684091 A CN106684091 A CN 106684091A
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- 239000000758 substrate Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 58
- 229920005591 polysilicon Polymers 0.000 claims abstract description 56
- 239000010409 thin film Substances 0.000 claims abstract description 48
- 239000013078 crystal Substances 0.000 claims abstract description 31
- 239000012528 membrane Substances 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 24
- 238000005224 laser annealing Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 claims description 4
- 208000034699 Vitreous floaters Diseases 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 12
- 230000008859 change Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000805 composite resin Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a display panel, an array substrate and a manufacturing method of the array substrate. The array substrate comprises a substrate, a polysilicon thin film located on the substrate and a plurality of thin film transistors, wherein the polysilicon thin film comprises crystal lattices which are arranged along a first direction and a second direction; the boundaries of the crystal lattices form crystal boundaries which extend along the first direction and the second direction; each thin film transistor comprises a broken line-shaped channel formed in the polysilicon thin film; each broken line-shaped channel comprises a plurality of connected channel parts; and the extension direction of each channel part and the first direction form a first included angle which is greater than 0 and smaller than 90 degrees. According to the display panel, the array substrate and the manufacturing method of the array substrate, the uniformity of single channel current can be improved through improving the directions of the corresponding channel and the crystal boundaries.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of display floater, array base palte and its manufacture
Method.
Background technology
In recent years, OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) technology
Quickly grow, have become most possible replacement LCD (Liquid Crystal Display, liquid crystal display)
Prospect technology.
Existing display floater is using thin film transistor (TFT) (TFT) element come to such as OLED, LCD
Luminescence unit is lighted and is controlled.However, in display floater TFT elements preparation need on substrate shape
Into polysilicon membrane, the polysilicon membrane as TFT elements active layer causing TFT elements to have
The effect of on-off control.At present, the mainstream technology that prepared by polysilicon membrane is excimer laser annealing technology
(ELA).Quasi-molecule laser annealing technology amorphous silicon layer is scanned using laser beam so that amorphous
Crystallizing silicon layer becomes polysilicon membrane.However, when adopting quasi-molecule laser annealing technology, amorphous silicon layer knot
Brilliant feature has a directivity, and crystal boundary (Grain boundary) size has differences in different directions.
Illustrate referring specifically to Fig. 1 and Fig. 2, Fig. 1 and scanned along Y-direction using quasi-molecule laser annealing technology
130 schematic diagram of polysilicon membrane for being formed, polysilicon membrane 130 are included in X direction and along Y-direction
Multiple lattices 131 of arrangement.The border of lattice 131 forms crystal boundary 132.In other words, crystal boundary 132 is along X
Direction and Y-direction extend.Due to the anisotropy of polycrystalline silicon growth, the crystal boundary 132 that can be resulted in exists
Different directions have different quantity, and polysilicon membrane 130 has different roughness in different directions.
For example, in the embodiment shown in fig. 1, quasi-molecule laser annealing technology is scanned along Y-direction, is formed
Polysilicon membrane 130 along Y-direction roughness more than roughness in X direction.If excimer laser
Annealing technology is scanned in X direction, and the polysilicon membrane 130 for being formed roughness in X direction is more than edge
The roughness of Y-direction.Further, since the anisotropy of polycrystalline silicon growth, in X direction by the polycrystalline
The electric current of silicon thin film has obvious with Y-direction by the number of grain boundaries passed through by the electric current of the polysilicon membrane
Difference, and then affect light-emitting component display effect.Fig. 2 is illustrated using quasi-molecule laser annealing technology
Formed polysilicon membrane schematic diagram is scanned in X direction, and which can equally cause difference in X direction and Y
Current difference of the direction by the polysilicon membrane.
When prior art prepares TFT elements, its raceway groove is generally arranged along above-mentioned X-direction and/or Y-direction,
When electric current passes through raceway groove, can be because passing through crystal boundary number on the path of X-direction and Y-direction, size and many
The notable difference of the roughness of polycrystal silicon film in turn results in current difference, and easily after light-emitting component is lighted
Form horizontally or vertically linear moire (Mura).
The content of the invention
Defect in order to overcome above-mentioned prior art presence of the invention, there is provided a kind of display floater, array base
Plate and its manufacture method, which can improve single channel current by the direction of improvement raceway groove and crystal boundary
Homogeneity.
The present invention provides a kind of array base palte, including：Substrate；Polysilicon membrane, on the substrate,
The polysilicon membrane includes lattice in the first direction with second direction arrangement, the border shape of the lattice
Into the crystal boundary extended along the first direction and the second direction；And multiple thin film transistor (TFT)s, each
The fold-line-shaped raceway groove that the thin film transistor (TFT) is formed in being included in the polysilicon membrane, the fold-line-shaped ditch
Road includes multiple grooves for connecting, and the bearing of trend of each groove is formed with the first direction and is more than
0 degree of first angle less than 90 degree.
Preferably, the bearing of trend of two grooves adjacent in each described fold-line-shaped raceway groove is orthogonal.
Preferably, in each described fold-line-shaped raceway groove, the bearing of trend of each groove and described
First angle that one direction is formed is identical.
Preferably, the thin film transistor (TFT) also include grid, source electrode and drain electrode, the grid, source electrode and
The bearing of trend of the pattern of drain electrode is respectively perpendicular or arranges parallel to the first direction.
Preferably, the thin film transistor (TFT) also include grid, source electrode and drain electrode, the grid, source electrode and
The bearing of trend of the pattern of drain electrode is respectively parallel to a line of the fold-line-shaped raceway groove and arranges.
Preferably, the scope of first angle is 5 degree to 85 degree.
Preferably, the fold-line-shaped raceway groove is " S " type raceway groove, " V " type raceway groove, " N " type raceway groove
And the one kind in " W " type raceway groove.
Preferably, the thin film transistor (TFT) is top gate type thin film transistor or bottom gate thin film transistor.
Preferably, the substrate is rectangle, and a line of the substrate is parallel with the first direction.
Preferably, the first direction is vertical with the second direction.
According to a further aspect of the invention, a kind of display floater is also provided, including：Above-mentioned array base
Plate；And multiple display elements, on the array base palte.
According to another aspect of the present invention, a kind of manufacture method of array base palte is also provided, including：
Amorphous silicon layer is formed on substrate；Using quasi-molecule laser annealing technique, the amorphous is scanned in a second direction
Silicon layer so that the amorphous silicon layer forms polysilicon membrane, the polysilicon membrane is included in the first direction
With the lattice of second direction arrangement, the border of the lattice is formed along the first direction and the second party
To the multiple crystal boundaries for extending, the second direction is perpendicular to the first direction；And form multiple thin film
Transistor, wherein, the fold-line-shaped raceway groove of the thin film transistor (TFT), institute are formed using the polysilicon membrane
Stating fold-line-shaped raceway groove includes multiple grooves for connecting, the bearing of trend of each groove and the first party
To the first angle formed more than 0 degree less than 90 degree.
Preferably, the fold-line-shaped raceway groove for forming multiple thin film transistor (TFT)s using the polysilicon membrane includes：
The polysilicon membrane is performed etching using the light shield with multiple fold-line-shaped openings, form the folding
Linear raceway groove, the fold-line-shaped opening have multiple peristomes for connecting, multiple peristomes with it is multiple
The groove is corresponding.
Preferably, the polysilicon membrane is performed etching using the light shield with multiple fold-line-shaped openings,
Include to form the fold-line-shaped raceway groove：The light shield is placed, each opening of the fold-line-shaped opening is made
The bearing of trend in portion forms first angle with the first direction.
Preferably, the light shield be rectangle, the extension side of the two neighboring peristome of the fold-line-shaped opening
To orthogonal, multiple peristomes of the fold-line-shaped opening are parallel with two sides of the light shield respectively.
Preferably, the polysilicon membrane is performed etching using the light shield with multiple fold-line-shaped openings,
Include to form the fold-line-shaped raceway groove：Place the light shield, make two sides of the light shield respectively with institute
State first direction parallel with the second direction；And relatively described first direction, with one described first
The angle of angle rotates the light shield.
Preferably, the scope of first angle is 5 degree to 85 degree.
Preferably, the substrate is rectangle, two sides of the substrate respectively with the first direction and institute
State second direction parallel.
Compared with prior art, the present invention passes through using the thin film transistor (TFT) with fold-line-shaped raceway groove, and makes
The bearing of trend of multiple grooves of fold-line-shaped raceway groove has angle with crystal boundary bearing of trend, and then improves single
The homogeneity of individual thin film transistor channel electric current.On the other hand, the present invention is thin to make also by mask set
Film transistor is with the fold-line-shaped raceway groove different with crystal boundary bearing of trend.By the present invention provide structure and
Method, can effectively reduce the difference of single thin film transistor channel electric current, improve the property of thin film transistor (TFT)
Can, and then improve display floater due to the horizontally or vertically linear moire produced by current difference.
Description of the drawings
Its example embodiment is described in detail by referring to accompanying drawing, above and other feature of the present invention and excellent
Point will be apparent from.
Fig. 1 to show and scan formed polysilicon membrane along Y-direction using quasi-molecule laser annealing technology
Schematic diagram.
Fig. 2 to show and scan formed polysilicon membrane in X direction using quasi-molecule laser annealing technology
Schematic diagram.
Fig. 3 A show the array base palte schematic diagram according to an embodiment of the present invention.
Fig. 3 B show the array base palte schematic diagram according to another kind embodiment of the invention.
Fig. 4 shows " S " type raceway groove schematic diagram according to embodiments of the present invention.
Fig. 5 shows " V " type raceway groove schematic diagram according to embodiments of the present invention.
Fig. 6 shows the sectional view of display floater according to embodiments of the present invention.
Fig. 7 shows the schematic diagram of light shield according to an embodiment of the invention.
Fig. 8 shows the schematic diagram of light shield according to another embodiment of the present invention.
Specific embodiment
Example embodiment is described more fully with referring now to accompanying drawing.However, example embodiment can
Implement in a variety of forms, and be not understood as limited to embodiment set forth herein；On the contrary, there is provided this
A little embodiments cause the present invention fully and completely, and the design of example embodiment comprehensively will be passed on
To those skilled in the art.In figure, identical reference represents same or similar structure, thus
Repetition thereof will be omitted.
Described feature, structure or characteristic can in any suitable manner with reference in one or more realities
Apply in mode.In the following description, there is provided many details so as to be given to the present invention embodiment party
Formula fully understands.However, one of ordinary skill in the art would recognize that, in no specific detail or
It is more, or using other methods, constituent element, material etc., it is also possible to put into practice technical scheme.
In some cases, it is not shown in detail or describes known features, material or operation to avoid obscuring this
It is bright.
The accompanying drawing of the present invention is only used for illustrating relative position relation, and in accompanying drawing, the size of element does not represent reality
The proportionate relationship of border size.
In order to improve the problem of single thin film transistor channel current difference in prior art, the present invention is provided
A kind of display floater with fold-line-shaped thin film transistor (TFT) and its manufacture method.With reference to Fig. 3 A to Fig. 8
The display floater and its manufacture method provided to the present invention is described.
First embodiment
Referring first to Fig. 3 A, Fig. 3 A show the array base palte schematic diagram according to an embodiment of the present invention.
Array base palte includes substrate 110, the polysilicon membrane on substrate 110 and multiple thin film transistor (TFT)s 120.
Substrate 110 can be the substrate that glass substrate or resin composite materials are constituted.In Fig. 3 A illustrated embodiments
In, 110 preferably rectangular substrate of substrate.Two sides of substrate 110 respectively with X-direction and Y-direction
It is parallel.
Polysilicon membrane is formed on substrate 110, and including along X side using quasi-molecule laser annealing technology
To the multiple lattices arranged with Y-direction.The border of lattice forms the crystalline substance for extending with Y-direction in X direction
Boundary 132.Wherein, X-direction is vertical with Y-direction.In Fig. 3 A illustrated embodiments, using quasi-molecule
Laser annealing techniques scan along Y-direction to be formed polysilicon membrane (crystal boundary 132 can with as shown in figure 1,
Omit in this figure).In such embodiments, the roughness along Y-direction of polysilicon membrane is more than edge
The roughness of X-direction, and along Y-direction 132 number of crystal boundary for passing through and the crystal boundary for passing through in X direction
132 numbers have notable difference.In some change case, it would however also be possible to employ quasi-molecule laser annealing technology
Scanning in X direction forms polysilicon membrane, and which can equally cause the crystal boundary difference on different directions.
Thin film transistor (TFT) 120 can be top gate type thin film transistor, or bottom gate thin film transistor.
Thin film transistor (TFT) 120 shown in Fig. 3 A is bottom gate thin film transistor.Specifically, thin film transistor (TFT)
120 include grid 124, source electrode 123, drain electrode 122 and the fold-line-shaped formed in polysilicon membrane 130
Raceway groove 121.In the present embodiment, the bearing of trend of the pattern of grid 124, source electrode 123 and drain electrode 122
It is respectively parallel to Y-direction setting.In further embodiments, grid 124, source electrode 123 and drain electrode 122
Pattern bearing of trend can also be respectively parallel to X-direction setting.Specifically, in embodiment with
Rectangle illustrates the pattern of grid 124, source electrode 123 and drain electrode 122, grid 124, source electrode 123 and drain electrode
122 bearing of trend can refer to the long axis direction of rectangular gate 124, source electrode 123 and drain electrode 122.
When drain electrode 122 and grid 124 on apply high level, the electricity between grid 124 and source electrode 123
When pressure Vgs is more than or equal to threshold voltage vt h, near 124 surface of grid in fold-line-shaped raceway groove 121
Migration electronics drain electrode 122 and source electrode 123 between conducting form channel current 125.Channel current 125
Direction it is consistent with the bearing of trend of fold-line-shaped raceway groove 121.
As the channel current 125 in each fold-line-shaped raceway groove 121 is needed across crystal boundary 132, and crystal boundary 132
There is significant difference in the x-direction and the z-direction, in order to improve the raceway groove of single thin film transistor (TFT) 120
The homogeneity of channel current 125 in 121, multiple grooves of the fold-line-shaped raceway groove 121 that the present invention is provided
Bearing of trend and X-direction between formed
Between also formed more than 0 degree less than 90 degree of included angle B), and then so that in single fold-line-shaped raceway groove 121
Each groove in electric current 125 across the number of crystal boundary 132, size and polysilicon membrane it is thick
Rugosity obvious difference reduces, and then improves the electric current 125 between each groove of single fold-line-shaped raceway groove 121
Between homogeneity.
Specifically, fold-line-shaped raceway groove provided by the present invention 121 includes multiple grooves for connecting.Often
The bearing of trend of individual groove is consistent with 125 direction of channel current in the groove.The part of groove
Border can be identical with the bearing of trend of groove, i.e., formed with X-direction and be less than more than 0 degree 90 degree
Angle, and the segment boundary of groove can also be parallel to each other.However, raceway groove provided by the present invention
The border not limited to this in portion, which can also in X direction or Y-direction is arranged, as long as ensureing that groove prolongs
Stretch direction and the angle more than 0 degree less than 90 degree is formed with X-direction.In the present embodiment, fold-line-shaped ditch
Road 121 is " S " type raceway groove, and which includes groove 1211,1212,1213,1214 and 1215.It is right
In each fold-line-shaped raceway groove 121, the bearing of trend of adjacent groove is orthogonal.Such as groove 1211
The bearing of trend of groove 1212 that is adjacent of bearing of trend it is orthogonal；Groove 1212 prolongs
The bearing of trend for stretching the groove 1213 that direction is adjacent is orthogonal.The extension of two neighboring groove
The included angle A formed between direction and X-direction is mutually remaining.Such as bearing of trend of groove 1211 and X side
The angle formed between the angle formed between and the bearing of trend and X-direction of groove 1212 is mutually remaining.
The included angle A formed between the bearing of trend and X-direction of each groove can be between 5 degree to 85 degree.
Preferably, in order to further reduce the electric current 125 between each groove of single fold-line-shaped raceway groove 121
Across crystal boundary 132 number, size and polysilicon membrane roughness difference, each groove prolongs
Stretch between the bearing of trend of included angle A and each groove formed between direction and X-direction and Y-direction
The included angle B of formation is identical.In other words, included angle A is preferably 45 degree.In some change case, folding
In linear raceway groove 121, the bearing of trend of two adjacent grooves is not orthogonal, therefore, fold-line-shaped
The included angle A formed between the bearing of trend and X-direction of each groove of raceway groove 121 can with it is different,
Part is identical or all identical.When the bearing of trend and X-direction of each groove of fold-line-shaped raceway groove 121
Between the included angle A that formed it is identical when, can preferably reduce each raceway groove of single fold-line-shaped raceway groove 121
Electric current 125 between portion across crystal boundary 132 number, size and polysilicon membrane roughness difference.
Second embodiment
Referring to Fig. 3 B, Fig. 3 B show the array base palte schematic diagram according to another kind embodiment of the invention.
Array base palte shown in Fig. 3 B is similar with the array base-plate structure shown in Fig. 3 A.Array shown in Fig. 3 B
Substrate is that the thin film transistor (TFT) 120 ' in Fig. 3 B is top with the array base palte difference shown in Fig. 3 A
Grid 124 ', source electrode 123 ' and drain electrode 122 ' in gate type thin film transistor, and thin film transistor (TFT) 120 '
Arrange parallel to the bearing of trend of a groove of fold-line-shaped raceway groove 121.
3rd embodiment
Referring specifically to Fig. 4, Fig. 4 illustrates a kind of fold-line-shaped raceway groove 121 '.Fold-line-shaped raceway groove 121 ' and Fig. 3 A
And 121 structure of fold-line-shaped raceway groove shown in Fig. 3 B is similar to, and is also " S " type raceway groove.With Fig. 3 A and
Fold-line-shaped raceway groove 121 ' and broken line unlike fold-line-shaped raceway groove 121 shown in Fig. 3 B, shown in Fig. 4
121 specular of shape raceway groove.In other words, either just " S " type raceway groove, anti-" S types " raceway groove, fall
" S " type raceway groove is belonged in the range of " S types " raceway groove.
Due to the fold-line-shaped raceway groove 121 ' shown in Fig. 4 and 121 specular of fold-line-shaped raceway groove, therefore raceway groove
Electric current 125 ' also with 125 specular of channel current shown in Fig. 3 A and Fig. 3 B.
Fourth embodiment
Referring specifically to Fig. 5, Fig. 5 illustrates another kind of fold-line-shaped raceway groove 121 ".Fold-line-shaped raceway groove 121 " is
" V " type raceway groove, including two grooves 1211 " and 1212 ".The flow direction of channel current 125 " and folding
The bearing of trend of linear raceway groove 121 " is consistent, is also " V " type.In other words, channel current 125 " with
The bearing of trend of two grooves 1211 " and 1212 " is consistent.Therefore with channel current 125 " flow direction with
Angle between X-direction is describing two grooves 1211 " and 1212 " bearing of trend and X-direction it
Between angle.Specifically, in the present embodiment, two extension sides of " V " type channel current 125 "
It is equal to the included angle A 1 and A2 between X-direction.Included angle A 1 and A2 can be 5 degree to 85 degree
Between it is arbitrarily angled.Preferably, included angle A 1 and A2 are 45 degree.Some in the present embodiment change
In example, included angle A 1 and A2 can be with unequal, for example, " V " type channel current 125 " two prolong
Stretch direction orthogonal, also, included angle A 1 and A2 are not equal to 45 degree.
3rd embodiment and the schematic fold-line-shaped raceway groove that present invention offer must be provided of fourth embodiment, this
Art personnel can realize further types of broken line type raceway groove with design of the invention.Such as " N "
The variation pattern of type raceway groove, " W " type raceway groove or these raceway grooves is all within the scope of the present invention.
The manufacture process of manufacturing array substrate of the present invention and display floater is described below in conjunction with Fig. 6.Specifically
Comprise the steps：
Substrate 210 is provided.Preferably, substrate 210 be rectangular substrate, two sides of such as rectangular substrate
It is parallel with above-mentioned X-direction and Y-direction respectively.
Grid 220 is formed over the substrate 210.
Gate insulation layer 230 is formed on grid 220.
Amorphous silicon layer is formed on gate insulation layer 230.
Being formed using quasi-molecule laser annealing technology scanning amorphous silicon layer includes arranging with Y-direction in X direction
Multiple lattices polysilicon membrane.The border of lattice is formed in X direction and along the multiple of Y-direction extension
Crystal boundary.The roughness of the number, size and polysilicon membrane of the crystal boundary for passing through in X direction with along Y-direction
Through the roughness of number, size and polysilicon membrane of crystal boundary there is notable difference.
240 (the raceway groove 240 of fold-line-shaped raceway groove that lithographic process forms thin film transistor (TFT) is carried out to polysilicon membrane
Overlook as fold-line-shaped).Fold-line-shaped raceway groove 240 includes multiple grooves for connecting, fold-line-shaped raceway groove 240
Each groove bearing of trend and X-direction between formed more than 0 degree be less than 90 degree angle (such as
Shown in Fig. 3 A to Fig. 5).The lithographic process of polysilicon membrane is entered one with reference to Fig. 7 and Fig. 8 below
Step explanation.
Referring to Fig. 7, Fig. 7 illustrates a kind of embodiment of light shield 300 of present invention offer.Light shield 300 has
There are multiple fold-line-shaped openings 310, for forming S type raceway grooves." S " type opening 310 is shown as in Fig. 7.
The bearing of trend in the wherein adjacent apertures portion of " S " type opening 310 is orthogonal.For example, peristome 311
Bearing of trend and peristome 312 bearing of trend it is orthogonal.Light shield 300 is rectangle light shield.“S”
The bearing of trend of each peristome of type opening 310 is parallel with two sides of rectangular devices 300 respectively.When
Entered using the light shield 300 shown in Fig. 7 when lithographic process is carried out to polysilicon membrane, make light shield 300 first
Side it is parallel with X-direction and Y-direction respectively.In other words, that is, make each of " S " type opening 310
The bearing of trend of individual peristome is parallel with X-direction and Y-direction respectively.Then by 300 relative X of light shield
(shown in dotted line, wherein A is the one of groove of required fold-line-shaped raceway groove to direction anglec of rotation A
Angle between bearing of trend and X-direction), to perform etching to polysilicon membrane, and then obtain as schemed
121 ' fold-line-shaped raceway grooves shown in 4.It will be appreciated by those skilled in the art that light shield 300 can be in existing skill
The light shield performed etching to polysilicon membrane in art, the present invention only need existing light shield rotates to an angle
The fold-line-shaped channel structure required for the present invention is can be achieved with, the system of photomask materials and light shield is saved with this
Journey.
Referring to Fig. 8, Fig. 8 illustrates a kind of embodiment of light shield 400 of present invention offer.Light shield 400
With multiple " S " type fold-line-shaped openings 410.From unlike the light shield 300 shown in Fig. 7, work as light shield
400 side respectively with X-direction and parallel Y-direction when, each peristome of " S " type opening 310
Bearing of trend forms the angle more than 0 degree less than 90 degree with X-direction, and then obtains such as Fig. 4 after etching
121 ' shown fold-line-shaped raceway grooves.
Above-mentioned Fig. 7 and Fig. 8 only symbolically illustrate two embodiments of light shield provided by the present invention.Remove
Light shield shown in Fig. 7 and Fig. 8, using with " V " type opening, " N " type opening, " W " type
The step of light shield of opening is performed etching to polysilicon membrane is also within the scope of the present invention.
After performing etching to polysilicon membrane and to form fold-line-shaped raceway groove 240, on fold-line-shaped raceway groove 240
Form source electrode 250 and drain electrode 260.
Planarization layer 270 is formed on source electrode 250 and drain electrode 260.
The negative electrode 281 that an opening is formed on planarization layer 270 for display element 280 is connected with drain electrode 260
Connect.
Display element 280 is formed, the negative electrode 281 of display element 280 is by above-mentioned opening and drain electrode 260
Contact.
Pixel defining layer 290 is formed between display element 280.
Specifically, the present embodiment schematically depict the display surface with bottom grating structure thin film transistor (TFT)
The fabrication steps of plate.Those skilled in the art can be according to different display elements and the thin film of different structure
Transistor realizes the change case of more processing procedures, and can for example omit or take on demand increases some fabrication steps,
Will not be described here.
Compared with prior art, the present invention passes through using the thin film transistor (TFT) with fold-line-shaped raceway groove, and makes
Multiple groove bearing of trends of fold-line-shaped raceway groove have angle with crystal boundary bearing of trend, and then improve single
The homogeneity of thin film transistor channel electric current.On the other hand, the present invention makes thin film also by mask set
Transistor is with the fold-line-shaped raceway groove different with crystal boundary bearing of trend.The structure provided by the present invention and side
Method, can effectively reduce the difference of single thin film transistor channel electric current, improve the performance of thin film transistor (TFT),
And then improve display floater due to the horizontally or vertically linear moire produced by current difference.
The illustrative embodiments of the present invention are particularly shown and described more than.It should be understood that of the invention
Disclosed embodiment is not limited to, on the contrary, it is intended to cover be included in scope
Interior various modifications and equivalent replacement.
Claims (18)
1. a kind of array base palte, it is characterised in that include：
Substrate；
Polysilicon membrane, on the substrate, the polysilicon membrane includes in the first direction with the second
The lattice of direction arrangement, the border of the lattice are formed and are extended along the first direction and the second direction
Crystal boundary；And
Multiple thin film transistor (TFT)s, what each described thin film transistor (TFT) was formed in being included in the polysilicon membrane
Fold-line-shaped raceway groove, the fold-line-shaped raceway groove include multiple grooves for connecting, the extension side of each groove
To the first angle formed with the first direction more than 0 degree less than 90 degree.
2. array base palte as claimed in claim 1, it is characterised in that in each described fold-line-shaped raceway groove
The bearing of trend of two adjacent grooves is orthogonal.
3. array base palte as claimed in claim 1, it is characterised in that in each described fold-line-shaped raceway groove,
The bearing of trend of each groove is identical with first angle that the first direction is formed.
4. the array base palte as described in any one of claims 1 to 3, it is characterised in that the thin film is brilliant
Body pipe also includes grid, source electrode and drain electrode, the bearing of trend point of the pattern of the grid, source electrode and drain electrode
Do not arrange perpendicular or parallel to the first direction.
5. the array base palte as described in any one of claims 1 to 3, it is characterised in that the thin film is brilliant
Body pipe also includes grid, source electrode and drain electrode, the bearing of trend point of the pattern of the grid, source electrode and drain electrode
Do not arrange parallel to a line of the fold-line-shaped raceway groove.
6. the array base palte as described in any one of claims 1 to 3, it is characterised in that first folder
The scope at angle is 5 degree to 85 degree.
7. the array base palte as described in any one of claims 1 to 3, it is characterised in that the fold-line-shaped
Raceway groove is the one kind in " S " type raceway groove, " V " type raceway groove, " N " type raceway groove and " W " type raceway groove.
8. the array base palte as described in any one of claims 1 to 3, it is characterised in that the thin film is brilliant
Body pipe is top gate type thin film transistor or bottom gate thin film transistor.
9. the array base palte as described in any one of claims 1 to 3, it is characterised in that the substrate is
Rectangle, a line of the substrate are parallel with the first direction.
10. the array base palte as described in any one of claims 1 to 3, it is characterised in that described first
Direction and the second direction are orthogonal.
11. a kind of display floaters, it is characterised in that include：
Array base palte as described in any one of claim 1 to 10；And
Multiple display elements, on the array base palte.
12. a kind of manufacture methods of array base palte, it is characterised in that include：
Amorphous silicon layer is formed on substrate；
Using quasi-molecule laser annealing technique, the amorphous silicon layer is scanned in a second direction so that described non-
Crystal silicon layer forms polysilicon membrane, and the polysilicon membrane includes arranging with the second direction in the first direction
The lattice of row, the border of the lattice formed along the first direction and the second direction extend it is multiple
Crystal boundary, the second direction is perpendicular to the first direction；And
Multiple thin film transistor (TFT)s are formed, wherein, the thin film transistor (TFT) is formed using the polysilicon membrane
Fold-line-shaped raceway groove, the fold-line-shaped raceway groove includes multiple grooves for connecting, the extension of each groove
Direction forms the first angle more than 0 degree less than 90 degree with the first direction.
13. manufacture methods as claimed in claim 12, it is characterised in that using the polysilicon membrane
The fold-line-shaped raceway groove for forming multiple thin film transistor (TFT)s includes：
The polysilicon membrane is performed etching using the light shield with multiple fold-line-shaped openings, form institute
State fold-line-shaped raceway groove, the fold-line-shaped opening has multiple peristomes for connecting, multiple peristomes with
Multiple grooves are corresponding.
14. manufacture methods as claimed in claim 13, it is characterised in that using with multiple fold-line-shapeds
The light shield of opening is performed etching to the polysilicon membrane, and forming the fold-line-shaped raceway groove includes：
The light shield is placed, the bearing of trend and described first of each peristome of the fold-line-shaped opening is made
Direction forms first angle.
15. manufacture methods as claimed in claim 13, it is characterised in that the light shield be rectangle, institute
The bearing of trend for stating the two neighboring peristome of fold-line-shaped opening is orthogonal, the fold-line-shaped opening it is many
Individual peristome is parallel with two sides of the light shield respectively.
16. manufacture methods as claimed in claim 15, it is characterised in that using with multiple fold-line-shapeds
The light shield of opening is performed etching to the polysilicon membrane, and forming the fold-line-shaped raceway groove includes：
Place the light shield, make two sides of the light shield respectively with the first direction and the second party
To parallel；And
With respect to the first direction, the light shield is rotated with the angle of first angle.
17. manufacture methods as described in claim 14 or 16, it is characterised in that first angle
Scope be 5 degree to 85 degree.
18. manufacture methods as described in any one of claim 14 to 16, it is characterised in that the base
Plate is rectangle, and two sides of the substrate are parallel with the first direction and the second direction respectively.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510755051 | 2015-11-09 | ||
| CN201510755051X | 2015-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106684091A true CN106684091A (en) | 2017-05-17 |
Family
ID=58839406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610289121.1A Pending CN106684091A (en) | 2015-11-09 | 2016-05-03 | Display panel, array substrate and manufacturing method of array substrate |
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| Country | Link |
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| CN (1) | CN106684091A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111640765A (en) * | 2020-06-10 | 2020-09-08 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1299073A (en) * | 1999-12-08 | 2001-06-13 | 三菱电机株式会社 | Liquid crystal display device and TFT panel |
| US6479837B1 (en) * | 1998-07-06 | 2002-11-12 | Matsushita Electric Industrial Co., Ltd. | Thin film transistor and liquid crystal display unit |
| US20100270557A1 (en) * | 2007-09-25 | 2010-10-28 | The Trustees Of Columbia University In The City Of New York | Methods of producing high uniformity in thin film transistor devices fabricated on laterally crystallized thin films |
| CN104022157A (en) * | 2014-05-26 | 2014-09-03 | 京东方科技集团股份有限公司 | Thin-film transistor, array substrate and display device |
| CN104538402A (en) * | 2014-12-30 | 2015-04-22 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
-
2016
- 2016-05-03 CN CN201610289121.1A patent/CN106684091A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6479837B1 (en) * | 1998-07-06 | 2002-11-12 | Matsushita Electric Industrial Co., Ltd. | Thin film transistor and liquid crystal display unit |
| CN1299073A (en) * | 1999-12-08 | 2001-06-13 | 三菱电机株式会社 | Liquid crystal display device and TFT panel |
| US20100270557A1 (en) * | 2007-09-25 | 2010-10-28 | The Trustees Of Columbia University In The City Of New York | Methods of producing high uniformity in thin film transistor devices fabricated on laterally crystallized thin films |
| CN104022157A (en) * | 2014-05-26 | 2014-09-03 | 京东方科技集团股份有限公司 | Thin-film transistor, array substrate and display device |
| CN104538402A (en) * | 2014-12-30 | 2015-04-22 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111640765A (en) * | 2020-06-10 | 2020-09-08 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN111640765B (en) * | 2020-06-10 | 2023-03-24 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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Application publication date: 20170517 |