CN106653680A - Method for forming contact hole - Google Patents

Method for forming contact hole Download PDF

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Publication number
CN106653680A
CN106653680A CN201510741788.6A CN201510741788A CN106653680A CN 106653680 A CN106653680 A CN 106653680A CN 201510741788 A CN201510741788 A CN 201510741788A CN 106653680 A CN106653680 A CN 106653680A
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CN
China
Prior art keywords
hole
layer
forming method
dielectric layer
side wall
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Pending
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CN201510741788.6A
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Chinese (zh)
Inventor
刘继全
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201510741788.6A priority Critical patent/CN106653680A/en
Publication of CN106653680A publication Critical patent/CN106653680A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas

Abstract

A method for forming a contact hole comprises the following steps: providing a substrate, and forming a dielectric layer on the substrate; forming a through hole inwardly in a direction perpendicular to the surface of the dielectric layer, wherein an overhang structure protruding from the sidewall of the through hole is formed on the sidewall; physically bombarding the sidewall of the through hole; and filling the bombarded through hole with a conductive material to form a contact hole. According to the embodiment of the invention, after the through hole is formed by etching, the sidewall of the through hole is processed by means of physical bombardment to remove a possible overhang formed on the sidewall of the through hole, so that continuous growth of a barrier layer and a seed layer and uniform filling of the conductive material in the subsequent process are ensured. Therefore, slits and cavities in the contact hole are avoided, the continuity of the contact hole is ensured, and the electrical property and mechanical strength of the contact hole are improved.

Description

The forming method of contact hole
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of forming method of contact hole.
Background technology
In integrated circuit technology, the interconnection between levels is generally realized using contact hole.Concrete technology bag Include：First carry out the deposition of dielectric layer；Then through hole is formed using photoetching and etching technics；Recycle physics Vapour deposition (Physical Vapor Deposition, PVD) technique sequentially forms barrier layer and Seed Layer； Again through hole is filled with the mode of electroless plating (Electro chemical plating, ECP)；Using The mode of cmp (Chemical Mechanical Polishing, CMP) is to the through hole after filling Top is planarized.
The continuity of contact hole has important to its electric property and mechanical strength, such as electric migration performance Affect, it is therefore desirable to a kind of forming method for ensureing successional contact hole.
The content of the invention
Present invention solves the technical problem that being during contact hole is formed, it is to avoid through-hole side wall produces narrow Seam cavity, to ensure the continuity of contact hole.
To solve above-mentioned technical problem, the embodiment of the present invention provides a kind of forming method of contact hole, including：
Substrate is provided, dielectric layer is formed over the substrate；Perpendicular to the dielectric layer surface internally shape Into through hole, the through-hole side wall is formed with overhang structure and projects the side wall；Physics is carried out to through-hole side wall Bombardment；Filling conductive material in through hole after bombardment, forms contact hole.
Alternatively, the physical bombardment method is included using the plasma of argon gas, helium or nitrogen, edge Physical bombardment is carried out to through-hole side wall perpendicular to via bottoms, parallel to the direction of through-hole side wall.
Alternatively, during the plasma bombardment, the flow of gas is 5sccm to 20sccm, is added in work The radio-frequency power on radio-frequency coil in skill chamber be 500W to 2000W, the AC bias being added on wafer Power is 100W to 800W, and bombardment time is 1s to 10s.
Alternatively, the through-hole side wall is carried out filling conductive in the through hole after physical bombardment, after bombardment Before material, also include cleaning the through hole.
Alternatively, carrying out cleaning to the through hole includes：Using hydrofluoric acid, hydrochloric acid, ammoniacal liquor, hydrogen peroxide, And a kind of aqueous solution in sulfuric acid or the wherein arbitrarily combination of several aqueous solution are used as cleaning agent.
Alternatively, the dielectric layer includes the dielectric layer with different etching speed.
Alternatively, the dielectric layer with different etching speed includes：Sequentially form over the substrate Carbonitride of silicium layer, black diamond layer, octamethylcy-clotetrasiloxane hard mask layer, tetraethyl orthosilicate hard mask layer And titanium nitride hard mask layer.
Alternatively, the thickness of the carbonitride of silicium layer isExtremely
Alternatively, the thickness of the black diamond layer isExtremely
Alternatively, the thickness of the octamethylcy-clotetrasiloxane hard mask layer isExtremely
Alternatively, the thickness of the tetraethyl orthosilicate hard mask layer isExtremely
Alternatively, the thickness of the titanium nitride hard mask layer isExtremely
Alternatively, forming the through hole includes adopting CF4、CClF3、C2F6、O2And O3In one kind Or its any combination performs etching to be formed as etching agent.
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantages that：
The embodiment of the present invention is entered using the method for physical bombardment after etching forms through hole to through-hole side wall Row is processed, and with overhanging of removing that through-hole side wall is likely to form the company of subsequent barrier and Seed Layer is ensured Continuous growth and the uniform filling of conductive material, so as to efficiently avoid slit cavity in contact hole Produce, it is ensured that the continuity of contact hole, improve the electric property and mechanical strength of contact hole.
Alternatively, in one particular embodiment of the present invention, by using argon gas, helium or nitrogen etc. Gas ions, along perpendicular to the direction of via bottoms, to through-hole side wall physical bombardment are carried out, and eliminate through hole Overhanging for side wall, efficiently avoid the generation in slit cavity in contact hole.
Description of the drawings
Fig. 1 to Fig. 3 is a kind of generalized section of the intermediate structure of the forming method of contact hole；
Fig. 4 is the schematic flow sheet of the forming method of the contact hole of one embodiment of the invention；
Fig. 5 to Fig. 9 is the section of the intermediate structure of the forming method of the contact hole of one embodiment of the invention Schematic diagram.
Specific embodiment
From background technology, a kind of forming method for ensureing successional contact hole is needed.Fig. 1 to Fig. 3 It is a kind of generalized section of the intermediate structure of the forming method of contact hole.
With reference to Fig. 1, there is provided substrate 11, dielectric layer 12 is formed on the substrate 11.
The dielectric layer 12 includes：The first medium layer 121 being formed on the substrate 11, is formed at institute State the second dielectric layer 122 on first medium layer 121, the 3rd be formed in the second dielectric layer 122 Dielectric layer 123.Through hole 13 is internally formed perpendicular to the surface of the dielectric layer 12.
With reference to Fig. 2, before filling conductive material 16 in through hole 13, need to be initially formed in through hole 13 Barrier layer 14 and Seed Layer 15.
With reference to Fig. 3, the top of through hole 13 after filling is put down using cmp (CMP) method Smoothization, to form contact hole 18.The cmp stops at the table of the first medium layer 121 Face.
Find during detecting to the contact hole 18 formed using said method, in through hole 13 The conductive material 16 of filling is susceptible to ELECTROMIGRATION PHENOMENON.Referring to figs. 1 to Fig. 3, after further research It was found that, the ELECTROMIGRATION PHENOMENON causes mainly due to the cavity 17 in contact hole 18, cavity 17 Presence can cause local current excessive, and local electronic is that the electron collision near cavity 17 strengthens, and then is made Cavity 17 gradually expands, and ultimately results in circuit malfunction.Find after further study again, the product in cavity 17 Life is because the overhang structure 122a that the side wall of through hole 13 is formed have impact on barrier layer 14 and Seed Layer 15 Continuous growth, at overhang structure 122a dead angles formed below so that barrier layer 14 and Seed Layer 15 are deposited Less than, and, when subsequently through hole 13 is filled using electroless plating (ECP) method, conductive material 16 Fill uneven in overhang structure 122a vicinity, so as to produce slit cavity 17, cause electromigration.And Overhang structure 122a at the second dielectric layer 122 of the side wall of through hole 13 is then due to etching shape Into during through hole 13, have differences between the etch rate of different medium layer caused.
The embodiment of the present invention provides a kind of forming method of contact hole, below in conjunction with the accompanying drawings in addition specifically It is bright.
Fig. 4 is the schematic flow sheet of the forming method of the contact hole of one embodiment of the invention.
Fig. 5 to Fig. 9 is the section of the intermediate structure of the forming method of the contact hole of one embodiment of the invention Schematic diagram.
With reference to step S10 in Fig. 4 and Fig. 5, there is provided substrate 21.The substrate 21 can for monocrystalline silicon or Polysilicon；The substrate 21 can also be selected from GaAs, carborundum or silicon Germanium compound；The substrate 21 It is also selected from epitaxial layer or epitaxial layer silicon-on；The substrate 21 can also be other semiconductors Material；Device architecture can also be formed with the substrate 21.Substrate 21 described in the present embodiment is single Crystal silicon.
With reference to step S12 in Fig. 4 and Fig. 5, dielectric layer 22 is formed on the substrate 21.The medium Layer 22 includes：
First medium layer 221, is formed at the surface of the substrate 21, for the diffusion of barrier metal atoms. The first medium layer 221 can be silica, silicon nitride or carbonitride of silicium.Described in the present embodiment First medium layer 221 is carbonitride of silicium (SiCN), and dielectric constant is between 2.0 to 3.0.The carbon Silicon nitride (SiCN) layer adopts chemical vapor deposition (Chemical vapor deposition, CVD) technique Formed.The specific process parameter that the carbonitride of silicium (SiCN) layer is formed in the present embodiment is：Using four Methyl-monosilane (C4H12) and NH Si3Used as reactant, the wherein flow of tetramethylsilane is 400sccm To 1000sccm, NH3Flow be 500sccm to 4000sccm, reaction temperature be 200 DEG C to 500 DEG C, Reactant is dissociated using the high-frequency ac voltage of 13.56MHz, power is 800W to 2000W. The thickness for forming the first medium layer 221 isExtremely
Second dielectric layer 222, is formed at the surface of first medium layer 221, for isolating interlayer and same layer Metal.The material of the second dielectric layer 222 is low-K dielectric material, such as porous media material.Specifically Ground, in the present embodiment, the second dielectric layer 222 is black diamond (BDII), and dielectric constant is arrived 2.0 3.0 in the range of.Black diamond (BDII) layer is formed using chemical vapor deposition (CVD) technique.This reality Apply and the specific process parameter of the black diamond (BDII) layer is formed in example be：Using methyldiethoxysilane (DEMS) (chemical formula：C5H14O2Si), α-terpinene (ATRP) (chemical formula：C10H16) and O2 Used as reactant, the wherein flow of methyldiethoxysilane (DEMS) is 0.2g/min to 4g/min, The flow of α-terpinene (ATRP) is 0.5g/min to 5g/min, O2Flow be 50sccm extremely 500sccm, reaction temperature is 100 DEG C to 400 DEG C, using the high-frequency ac voltage of 13.56MHz to reaction Thing is dissociated, and power is 500W to 2000W.The thickness for forming the second dielectric layer 222 is ExtremelyMetal pedestal layer (not shown) is formed with the second dielectric layer 222.
3rd dielectric layer 223, is formed at the surface of the second dielectric layer 222, for stopping that oxygen is diffused into In the second dielectric layer 222.The material of the 3rd dielectric layer 223 can be higher Jie of consistency Material, such as epoxy dielectric material.In embodiment, the 3rd dielectric layer 223 is prestox ring four The hard mask of siloxanes (OMCTS HM) (chemical formula：SiOxCyHz).The octamethylcy-clotetrasiloxane Hard mask (OMCTS HM) layer is formed using chemical vapor deposition (CVD) technique.In the present embodiment The specific process parameter for forming the hard mask of the octamethylcy-clotetrasiloxane (OMCTS HM) layer is：Adopt With octamethylcy-clotetrasiloxane (OMCTS) as reactant, its flow is 0.5g/min to 10g/min, Reaction temperature is 200 DEG C to 500 DEG C, and reactant is solved using the high-frequency ac voltage of 13.56MHz From power is 500W to 2000W.The thickness for forming the 3rd dielectric layer 223 isExtremely
4th dielectric layer 224, is formed at the surface of the 3rd dielectric layer 223, for covering as etching Film layer.The material of the 4th dielectric layer 224 can be silicon, oxygen or nitrogen compound, such as silica. In the present embodiment, the 4th dielectric layer 224 is tetraethyl orthosilicate hard mask (TEOS HM) layer.Institute State tetraethyl orthosilicate hard mask (TEOS HM) layer to be formed using chemical vapor deposition (CVD) technique. The specific process parameter that the tetraethyl orthosilicate hard mask (TEOS HM) layer is formed in the present embodiment is： Using tetraethyl orthosilicate (TEOS) and O2As reactant, the wherein stream of tetraethyl orthosilicate (TEOS) Measure as 0.5g/min to 10g/min, O2Flow be 50sccm to 500sccm, reaction temperature be 100 DEG C To 400 DEG C, reactant is dissociated using the high-frequency ac voltage of 13.56MHz, power be 500W extremely 2000W.The thickness for forming the 4th dielectric layer 224 isExtremely
5th dielectric layer 225, is formed at the surface of the 4th dielectric layer 224, for as the anti-of photoetching Reflecting layer and the mask layer of etching.The material of the 5th dielectric layer 225 can be metallic compound, than Such as titanium or the compound of tantalum.In the present embodiment, the 5th dielectric layer 225 is titanium nitride hard mask (TiN HM) layer.Titanium nitride hard mask (TiN HM) layer is formed using physical vapour deposition (PVD) (PVD) technique, Specific process parameter is：The dc power being added on target is 3KW to 15KW, and the flow of argon gas is 4sccm to 20sccm, the flow of nitrogen is 10sccm to 200sccm.Form the 5th dielectric layer 225 Thickness beExtremely
With reference to step S14 in Fig. 4 and Fig. 6, perpendicular to the surface of the dielectric layer 22 through hole is internally formed 23.The through hole 23 sequentially passes through the 5th dielectric layer 225, the 4th dielectric layer 224, described 3rd dielectric layer 223, until exposing the metal pedestal layer (not shown) inside the second dielectric layer 222 Till.The A/F of the through hole 23 in the range of 30nm to 100nm, the depth of the through hole 23 Degree is in the range of 100nm to 300nm.The formation process of the through hole 23 is included using dry etching shape Into etching agent can be CF4、CClF3、C2F6、O2And O3In one kind or its any combination.
It should be noted that in due to the forming process of through hole 23, between the etch rate of different medium layer Have differences, in the interface of two media layer, easily produce and overhang.Specifically, in the present embodiment, Due to the laterally etched speed of the octamethylcy-clotetrasiloxane of the 3rd dielectric layer 223 hard mask (OMCTS HM) layer The laterally etched speed of rate dielectric layer more several than other is all slow.Therefore after the completion of etching, in the side of through hole 23 Wall, the octamethylcy-clotetrasiloxane of the 3rd dielectric layer 223 holds at hard mask (OMCTS HM) layer position It is also easy to produce overhang structure 223a.
With reference to step S16 in Fig. 4 and Fig. 7, physical bombardment is carried out to the side wall of the through hole 23, to go Except the overhang structure 223a.The direction of the physical bombardment is perpendicular to the bottom of through hole 23, parallel to logical The side wall of hole 23.The physical bombardment method is included using the plasma of argon gas, helium or nitrogen to institute State through hole 23 to be bombarded.In the present embodiment, during using argon ion bombardment, the flow of argon gas be 5sccm extremely 20sccm, is equipped with radio frequency (RF) coil, using the radio-frequency power pair of 500W to 2000W in process cavity Argon gas is dissociated, and the AC bias power being added on wafer is 100W to 800W, with Accelerated argon-ions, Bombardment time is 1s to 10s.
With reference to step S18 in Fig. 4 and Fig. 7, in the overhang structure 223a for removing the side wall of through hole 23 Afterwards, the through hole 23 is cleaned, to remove dry etching through hole 23 and argon ion bombardment is formed The accessory substance in through hole 23, such as carbonitride of silicium (SiCN), carbon copper nitride are resulted from during through hole 23 (CuCN) etc., prevent the follow-up filling on through hole 23 and contact from producing impact.In certain embodiments A kind of aqueous solution or several water-soluble in hydrofluoric acid, hydrochloric acid, ammoniacal liquor, hydrogen peroxide, sulfuric acid can be adopted Any combination of liquid is cleaned as cleaning agent to the through hole 23.Specifically, in the present embodiment, Using hydrofluoric acid as cleaning agent, HF and H in the hydrofluoric acid solution2The volume ratio of O is 1:1000.
With reference to step S20 in Fig. 4 and Fig. 8, in the through hole 23 barrier layer 24, seed is sequentially formed Layer 25 and the through hole 23 is filled using chemical plating method.
First, barrier layer 24 is formed in the through hole 23.The effect on the barrier layer 24 be prevent after The metallic atom for continuing the conductive material of filling in the through hole 23 is diffused into the dielectric layer 22 and described In substrate 21.The thickness range on the barrier layer 24 isExtremelySpecifically, the stop Layer 24 includes the first barrier layer 241 and the second barrier layer 242.In the present embodiment, first barrier layer 241 material is tantalum nitride, and the material on second barrier layer 242 is tantalum；First barrier layer 241 And the thickness range on second barrier layer 242 isExtremely
In the present embodiment, first barrier layer 241 is formed using physical vapour deposition (PVD) (PVD) method With second barrier layer 242.When depositing first barrier layer 241, nitrogen flow be 18sccm extremely 30sccm, argon flow amount is 2sccm to 10sccm, and the dc power of physical bombardment is 10KW to 30KW； When depositing second barrier layer 242, argon flow amount be 2sccm to 10sccm, the direct current of physical bombardment Power is 10KW to 30KW.
Then, Seed Layer 25 is formed in the through hole 23.The effect of the Seed Layer 25 be in order to Current lead-through is realized during follow-up filling conductive material.The material of the Seed Layer 25 and the follow-up conduction filled Material is relevant.Specifically, in the present embodiment, wire is done using copper, Seed Layer 25 can be done using copper. Forming the concrete technology of copper seed layer 25 includes：Institute is formed using the method for physical vapour deposition (PVD) (PVD) Seed Layer 25 is stated, during deposition, the dc power 10KW to 50KW being added on target, the seed of deposition Layer 25 thickness beExtremely
Then, conductive material 26 is filled into the through hole 23.The conductive material 26 can selected from tungsten, One or more in aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper.In the present embodiment, The conductive material 26 is copper.Specifically, using electroless plating (Electro chemical plating, ECP) Method in the through hole 23 filling conductive material 26.
Then, step S22 and Fig. 9 in Fig. 4 are refer to, the top of through hole 23 after the filling is carried out Planarization process.Specifically, in the present embodiment, using cmp (Chemical Mechanical Polishing, CMP) method the top of the through hole 23 after the filling is planarized, with formed Contact hole 27.The cmp stops at the surface of the second dielectric layer 222.
To sum up, after the embodiment of the present invention in etching by forming through hole, using physical bombardment mode to institute The side wall for stating through hole is processed, follow-up to ensure to remove the overhang structure that through-hole side wall is likely to form The continuous growth of barrier layer and Seed Layer and the uniform filling of conductive material, so as to efficiently avoid The generation in slit cavity in contact hole, it is ensured that the continuity of contact hole, improves the electrical property of contact hole Energy and mechanical strength.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore the guarantor of the present invention Shield scope should be defined by claim limited range.

Claims (13)

1. a kind of forming method of contact hole, it is characterised in that include：
Substrate is provided, dielectric layer is formed over the substrate；
Through hole is internally formed perpendicular to the dielectric layer surface, the through-hole side wall is formed with overhang structure and dashes forward Go out the side wall；
Physical bombardment is carried out to through-hole side wall；
Filling conductive material in through hole after bombardment, forms contact hole.
2. forming method as claimed in claim 1, it is characterised in that the physical bombardment method includes adopting The plasma of argon gas, helium or nitrogen, along perpendicular to via bottoms, parallel to the side of through-hole side wall Physical bombardment is carried out to through-hole side wall.
3. forming method as claimed in claim 2, it is characterised in that during the plasma bombardment, gas Flow be 5sccm to 20sccm, it is 500W to be added in radio-frequency power on the radio-frequency coil in process cavity To 2000W, the AC bias power being added on wafer is 100W to 800W, and bombardment time is 1s To 10s.
4. forming method as claimed in claim 1, it is characterised in that the through-hole side wall is carried out physics Hong After hitting, in through hole after bombardment before filling conductive material, also include cleaning the through hole.
5. forming method as claimed in claim 4, it is characterised in that carrying out cleaning to the through hole includes： A kind of aqueous solution or wherein any in using hydrofluoric acid, hydrochloric acid, ammoniacal liquor, hydrogen peroxide and sulfuric acid The combination of several aqueous solution is used as cleaning agent.
6. forming method as claimed in claim 1, it is characterised in that the dielectric layer includes thering is different quarters The dielectric layer of erosion speed.
7. forming method as claimed in claim 6, it is characterised in that Jie with different etching speed Matter layer includes：Carbonitride of silicium layer, black diamond layer, the silicon of prestox ring four are sequentially formed over the substrate Oxygen alkane hard mask layer, tetraethyl orthosilicate hard mask layer and titanium nitride hard mask layer.
8. forming method as claimed in claim 7, it is characterised in that the thickness of the carbonitride of silicium layer is Extremely
9. forming method as claimed in claim 7, it is characterised in that the thickness of the black diamond layer is Extremely
10. forming method as claimed in claim 7, it is characterised in that the octamethylcy-clotetrasiloxane is covered firmly The thickness of film layer isExtremely
11. forming methods as claimed in claim 7, it is characterised in that the tetraethyl orthosilicate hard mask layer Thickness isExtremely
12. forming methods as claimed in claim 7, it is characterised in that the thickness of the titanium nitride hard mask layer ForExtremely
13. forming methods as claimed in claim 1, it is characterised in that forming the through hole includes adopting CF4、 CClF3、C2F6、O2And O3In one kind or its any combination perform etching shape as etching agent Into.
CN201510741788.6A 2015-11-04 2015-11-04 Method for forming contact hole Pending CN106653680A (en)

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CN111724742B (en) * 2020-06-11 2022-02-22 武汉华星光电半导体显示技术有限公司 Display panel, preparation method thereof and display device
WO2022110383A1 (en) * 2020-11-26 2022-06-02 武汉新芯集成电路制造有限公司 Backside illuminated image sensor substrate and method for manufacturing backside illuminated image sensor

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