CN106652930B - Display panel and its data drive circuit and display device - Google Patents
Display panel and its data drive circuit and display device Download PDFInfo
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- CN106652930B CN106652930B CN201610910235.3A CN201610910235A CN106652930B CN 106652930 B CN106652930 B CN 106652930B CN 201610910235 A CN201610910235 A CN 201610910235A CN 106652930 B CN106652930 B CN 106652930B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- Crystallography & Structural Chemistry (AREA)
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract
The embodiment of the invention discloses a kind of display panel and its data drive circuit and display device, which includes: at least one switching circuit；Switching circuit includes two switch, and first switch will be from the received data signal transmission of data lead to data line；Second switch will be from the received data signal transmission of data lead to data line；When data-signal is positive data mode, first control line traffic control, first switch is opened second switch of line traffic control of Article 2 control simultaneously and is opened, when data-signal is negative sense data mode, first control line traffic control, first switch is opened second switch of line traffic control of Article 2 control simultaneously and is closed.In the embodiment of the present invention, data drive circuit guarantees that the positive frame charging ability of display panel is not lost by the driving of large scale switching circuit；And the negative frame charging ability for guaranteeing display panel is driven by small size switching circuit, achieve the effect that reduce display panel power consumption.
Description
Technical field
The present embodiments relate to display technology more particularly to a kind of display panels and its data drive circuit, Yi Jixian
Showing device.
Background technique
Liquid crystal display is the main product of present field of liquid crystal display, the brightness of liquid crystal display, contrast, color and
The display effects such as visible angle are mainly determined that 80% cost of liquid crystal display is also concentrated mainly on liquid crystal by liquid crystal display panel
In display panel, therefore liquid crystal display panel is the principal element for determining liquid crystal display quality and cost.Liquid crystal display panel
The cost that data drive circuit reduction driving chip can be used achievees the purpose that reduce panel cost, data drive circuit control one
Root data lead drives at least two data lines, and the polarity of the data-signal of data lead transmission can be alternately flipped,
To realize display driving.
The schematic diagram of the data drive circuit of the display panel provided as shown in Figure 1A for the prior art, data-driven electricity
Road 10 be 2:6CMOS multiplexer circuit, the data drive circuit 10 respectively with six timing control line CKHR1, CKHG1,
CKHB1, XCKHR1, XCKHG1 and XCKHB1, two data lead S1 and S2 and multiple data lines (only show herein D1~
D6 it) is electrically connected, which includes that multiple switchings switch (demux switch) 11.Optional display panel is column herein
Inverted pattern, then Figure 1B is the driver' s timing figure of Figure 1A, after the scan line (not shown) of line n is opened in m frame, six
Timing control line drives multiple demux switches 11, and first backward data line D1~D6 transmits data-signal, wherein S1 pairs of data lead
Corresponding pixel progress is positive charged, and data lead S2 is negatively charged to the progress of corresponding pixel, after the (n+1)th row is opened, repeats
Same action.Data drive circuit 10 repeats same action in m+1 frame, but data lead S1 fills corresponding pixel
Negative electricity, data lead S2 carry out corresponding pixel positive charged.It follows that every data in the refresh process for completing a frame
The corresponding demux switch 11 of lead has switched 1920 times (by taking FHD product as an example).
Charge and discharge when AC power dissipation derives from panel refresh in known display panel to intrinsic capacitor and parasitic capacitance,
Therefore data drive circuit can account for the 70% of entire display panel power consumption, and the power consumption of data drive circuit is opened by demux
The size and charge and discharge number of pass determine.With the promotion of display panel resolution ratio and the increase of panel refresh frequency and right
The insufficient worry of pixel charging capability, the size and charge and discharge number of data drive circuit all increase therewith, lead to display panel
Power consumption it is increasing.
Summary of the invention
The embodiment of the present invention provides a kind of display panel and its data drive circuit and display device, to reduce display
The power consumption of panel.
In a first aspect, the embodiment of the invention provides a kind of data drive circuit of display panel, the data drive circuit
It include: at least one switching circuit；
The switching circuit includes two switch, wherein
The output end of first switch is electrically connected with a data line, input terminal is electrically connected with a data lead, with
And control terminal is electrically connected with first control line, under the control of first control line, first switch is opened
Or it closes, and will be from the received data signal transmission of the data lead to the data line when opening；
The output end of second switch is electrically connected with the data line, input terminal is electrically connected with the data lead, with
And control terminal is electrically connected with Article 2 control line, under the control of the Article 2 control line, second switch is opened
Or it closes, and will be from the received data signal transmission of the data lead to the data line when opening；
The data-signal has forward data state and negative sense data mode, when the data-signal is forward data shape
When state, first switch described in the first control line traffic control is opened second described in the Article 2 control line traffic control simultaneously
A switch is opened, and when the data-signal is negative sense data mode, is cut for first described in the first control line traffic control
Parallel operation is opened second switch described in the Article 2 control line traffic control simultaneously and is closed.
Second aspect, the embodiment of the invention also provides a kind of display panel, which includes driving chip and such as
The upper data drive circuit.
The third aspect, the embodiment of the invention also provides a kind of display device, which includes as described above aobvious
Show panel.
First switching in the embodiment of the present invention, when data-signal is positive data mode, in each switching circuit
Device and second switch open simultaneously, and ensure that large-sized switching circuit is driven；When data-signal is negative sense data
When state, first switch in each switching circuit is opened second switch simultaneously and is closed, and switches electricity using small size
Road is driven.Obviously the present invention guarantees that the positive frame charging ability of display panel is not damaged by the driving of large scale switching circuit
Consumption drives the negative frame charging ability for guaranteeing display panel to also reduce the ruler of switching circuit simultaneously by small size switching circuit
It is very little, achieve the effect that the power consumption for reducing data drive circuit and then reduces display panel power consumption.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to do one simply to introduce, it should be apparent that, the accompanying drawings in the following description is this hair
Bright some embodiments for those of ordinary skill in the art without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Figure 1A is the schematic diagram of the data drive circuit for the display panel that the prior art provides；
Figure 1B is the driver' s timing figure of Figure 1A；
Fig. 2A is the schematic diagram of the data drive circuit of display panel provided by one embodiment of the present invention；
Fig. 2 B is the driver' s timing figure of Fig. 2A；
Fig. 3 A is the schematic diagram of the data drive circuit for the display panel that another embodiment of the present invention provides；
Fig. 3 B is the driver' s timing figure of Fig. 3 A；
Fig. 4 A is the schematic diagram of the data drive circuit for the display panel that further embodiment of the present invention provides；
Fig. 4 B is the driver' s timing figure of Fig. 4 A；
Fig. 5 A is the schematic diagram of the data drive circuit for the display panel that another embodiment of the invention provides；
Fig. 5 B is the driver' s timing figure of Fig. 5 A；
Fig. 6 is the schematic diagram of display panel provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, hereinafter with reference to attached in the embodiment of the present invention
Figure, clearly and completely describes technical solution of the present invention by embodiment, it is clear that described embodiment is the present invention one
Section Example, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
The power consumption of given data driving circuit is determined by the demux size switched and charge and discharge number, it is clear that reduces demux
The size and charge and discharge number of switch can achieve the purpose for reducing power consumption.However reduce demux switch size will lead to it is aobvious
Show that panel charging ability is insufficient.Specifically, it is as shown in the table, when the signal of data lead is the data-signal of -5V, demux
The size of switch reduces the negative frame charging ability for not influencing data drive circuit；When the signal of data lead is the data letter of+5V
Number when, demux switch size reduce influence data drive circuit positive frame charging ability.However, the gate source voltage Vgs of NMOS
(voltage i.e. between grid G and source S) is smaller, causes data drive circuit poor in positive frame charging ability, it is clear that restricts data
The factor of driving circuit size reduction is the positive frame charging ability of data drive circuit.
The present invention provides a kind of data drive circuit of display panel, the data drive circuit of the display panel include: to
A few switching circuit；Switching circuit includes two switch, wherein the output end and a data line electricity of first switch
Connection, input terminal is electrically connected with a data lead and control terminal is electrically connected with first control line, in first control line
Control under, first switch opens or closes, and open when will be from the received data signal transmission of data lead to number
According to line；The output end of second switch is electrically connected with data line, input terminal is electrically connected with data lead and control terminal and the
The electrical connection of two control lines, under the control of Article 2 control line, second switch is opened or closed, and will be from when opening
The received data signal transmission of data lead is to data line；Data-signal has forward data state and negative sense data mode, when
When data-signal is positive data mode, first control line traffic control, first switch opens Article 2 simultaneously and controls line traffic control
Second switch is opened, and when data-signal is negative sense data mode, first control line traffic control, first switch is opened
Second switch of line traffic control of Article 2 control simultaneously is closed.
Showing for data drive circuit of the present invention is carried out for the data drive circuit of the display panel shown in Fig. 2A herein
Example description, it will be recognized to those skilled in the art that data drive circuit of the invention includes but is not limited to Fig. 2A institute registration
According to driving circuit.As shown in Figure 2 A, which includes at least one switching circuit 111 (herein only to be labeled with 111
A switching circuit for be described), which is electrically connected with data lead S1 and data line D1 respectively.?
Each switch that first control line is electrically connected in the present invention is first switch, and the electrical connection of Article 2 control line is respectively cut
Parallel operation is second switch, and first control line for corresponding to switching circuit 111 in fig. 2 accordingly is CKH1, Article 2
Control line is CKH2, and first switch is T1, and second switch is T2.
Specifically, when the data-signal of data lead S1 output is positive data mode, in the switching circuit 111 with
First switch (T1) of first control line CKH1 electrical connection and be electrically connected with Article 2 control line CKH2 second cut
Parallel operation (T2) opens simultaneously, that is, ensure that large-sized switching circuit 111 is driven；When the data letter of data lead S1 output
When number being negative sense data mode, first switch being electrically connected with first control line CKH1 in the switching circuit 111
(T1) it opens second switch being electrically connected simultaneously with Article 2 control line CKH2 and closes (T2), i.e., using small size switching electricity
Road 111 is driven.Obviously the present invention by large scale switching circuit driving guarantee display panel positive frame charging ability not by
Loss drives the negative frame charging ability for guaranteeing display panel to also reduce the ruler of switching circuit simultaneously by small size switching circuit
It is very little, achieve the effect that the power consumption for reducing data drive circuit and then reduces display panel power consumption.
Display panel provided by the invention is illustrated by following multiple specific examples herein, those skilled in the art
It is appreciated that the data drive circuit of display panel includes but is not limited to following example, the data of any one display panel are driven
The structure of dynamic circuit each falls within protection scope of the present invention.Known NMOS causes data drive circuit poor in positive frame charging ability,
Therefore present invention is particularly suitable for cmos data driving circuit and NMOS data drive circuit, but those skilled in the art can be with
Understand, the present invention is obviously also applied for PMOS data drive circuit, in the following embodiments with cmos data driving circuit and
It is illustrated based on NMOS data drive circuit.
It is as shown in Figure 2 A the schematic diagram of the data drive circuit of display panel provided by one embodiment of the present invention.Such as figure
Shown, the data drive circuit of the display panel includes multiple switching circuit groups 110, each switching circuit group 110 includes extremely
Few six switching circuits 111；One switching circuit group 110 includes, respectively with the first data lead S1, the first timing control line CKH1
With the first data line D1 electrical connection the first switch T1, respectively with the first data lead S1, the second timing control line CKH2 and
Second switch T2, the first data lead S1 of the first data line D1 electrical connection is used for transmission the first data-signal；Respectively with
The third switch T3 of two data lead S2, third timing control line CKH3 and the second data line D2 electrical connection, respectively with second
The 4th switch T4 of data lead S2, the 4th timing control line CKH4 and the second data line D2 electrical connection, the second data lead
S2 is used for transmission the second data-signal；Respectively with the first data lead S1, the 5th timing control line CKH5 and third data line D3
5th switch T5 of electrical connection, it is electric with the first data lead S1, the 6th timing control line CKH6 and third data line D3 respectively
6th switch T6 of connection；It is electrically connected respectively with the second data lead S2, the first timing control line CKH1 and the 4th data line D4
The 7th switch T7 connect is electrically connected with the second data lead S2, the 7th timing control line CKH7 and the 4th data line D4 respectively
The 8th switch T8；It is electrically connected respectively with the first data lead S1, third timing control line CKH3 and the 5th data line D5
9th switch T9, be electrically connected respectively with the first data lead S1, the 8th timing control line CKH8 and the 5th data line D5
Ten switch T10；The tenth be electrically connected respectively with the second data lead S2, the 5th timing control line CKH5 and the 6th data line D6
One switch T11, the tenth be electrically connected respectively with the second data lead S2, the 9th timing control line CKH9 and the 6th data line D6
Two switch T12.
In the present embodiment optional first data line D1, the second data line D2, third data line D3, the 4th data line D4,
The sub-pixel of the corresponding driving of 5th data line D5 and the 6th data line D6 is tactic red, green, blue, red, green, blue dice picture
Element.It will be understood by those skilled in the art that the sub-pixel colors sequence arrangement of display panel can also be red, green, blue, white, red,
It is green, blue, white, do not limit the sub-pixel of display panel in the present invention.
A data lead drives three data lines, therefore this implementation in each switching circuit group 110 in the present embodiment
The data drive circuit that example provides is 2:6CMOS data drive circuit, it will be understood by those skilled in the art that in other embodiments
In also optional data drive circuit be 1:n cmos data driving circuit, details are not described herein.In the present embodiment optional first
Switch T1, third switch T3, the 5th switch T5, the 7th switch T7, the 9th switch T9 and the 11st switch T11
It is made of a NMOS transistor；Second switch T2, the 4th switch T4, the 6th switch T6, the 8th switch T8,
Ten switch T10 and the 12nd switch T12 are made of a PMOS transistor.It will be apparent that each in the present embodiment
First switch of switching circuit 111 is respectively T1, T3, T5, T7, T9 and T11, is respectively cut as shown in Figure 2 A in the present embodiment
Second switch for changing circuit 111 is respectively T2, T4, T6, T8, T10 and T12.It will be understood by those skilled in the art that first
The type of the switch T12 of switch T1~the 12nd includes but is not limited to above example, and in other embodiments also optional first
The switch T12 of switch T1~the 12nd is NMOS or is PMOS3, and details are not described herein.
The display panel optional in the present embodiment is column overturning drive mode, specifically, display panel shows former frame
When image, the first data-signal is positive data mode, and the second data-signal is negative sense data mode；Display panel shows latter
When frame image, the first data-signal is negative sense data mode, and the second data-signal is positive data mode.Those skilled in the art
It is appreciated that the drive mode of display panel includes but is not limited to arrange overturning, display panel provided by the invention is applied also for a little
The drive modes such as overturning, row overturning and frame overturning, details are not described herein.
The smaller data drive circuit that will lead to of Vgs based on NMOS is poor in positive frame charging ability, therefore the number of the present embodiment
Be according to the driving principle of driving circuit: display panel before display a frame image when, signal polarity is positive polar first data
Two switch of each switching circuit 111 corresponding to lead S1 open simultaneously, ensure that large-sized switching circuit 111 into
Row driving；And be negative first of each switching circuit 111 corresponding to polar second data lead S2 of signal polarity cuts
Parallel operation is opened, and is driven using small size switching circuit 111.
Display panel after the display a frame image when, signal polarity is negative every corresponding to polar first data lead S1
First switch of a switching circuit 111 is opened, and is driven using small size switching circuit 111；Signal polarity is anode
Two switch of each switching circuit 111 corresponding to the second data lead S2 of property open simultaneously, and ensure that large-sized
Switching circuit 111 is driven.Therefore in the present embodiment, data drive circuit is guaranteed by the driving of large scale switching circuit 111
The positive frame charging ability of display panel is not lost；And it is driven by small size switching circuit 111 and guarantees the negative of display panel
Frame charging ability also reduces the size of switching circuit simultaneously to reach the power consumption of reduction data drive circuit and then reduce display
The effect of panel power consumption.
It will be apparent that by taking m frame image and m+1 frame image are shown as an example, it is provided in this embodiment as shown in Figure 2 B
The driver' s timing of data drive circuit is: display m frame image, when the first data-signal is positive data mode and the second data
When signal is negative sense data mode, the first timing control line CKH1 controls the first switch T1 and opens, the second timing control line
CKH2 controls the second switch T2 and opens, so that the first data signal transmission to the first data line D1, i.e., switched by large scale
The driving of circuit 111 guarantees that the positive frame charging ability of display panel is not lost；Meanwhile first timing control line CKH1 control the 7th
Switch T7 is opened, and the 7th timing control line CKH7 controls the 8th switch T8 and closes, so that the second data signal transmission is to the
Four data line D4 are driven by small size switching circuit 111 to achieve the effect that reduce display panel power consumption.Known first cuts
Parallel operation T1 and the 7th switch T7 is NMOS, and the second switch T2 and the 8th switch T8 are PMOS, so the first timing
Control line CKH1 exports high level signal, and the second timing control line CKH2 exports low level signal, the 7th timing control line CKH7
Export high level signal.
Third timing control line CKH3 controls third switch T3 and opens, the 4th switching of the 4th timing control line CKH4 control
Device T4 is closed, so that the second data signal transmission to the second data line D2, i.e., driven by small size switching circuit 111 to reach
Reduce the effect of display panel power consumption；Meanwhile third timing control line CKH3 controls the 9th switch T9 and opens, the 8th timing control
Line CKH8 processed controls the tenth switch T10 and opens, so that the first data signal transmission passes through large scale to the 5th data line D5
The driving of switching circuit 111 guarantees that the positive frame charging ability of display panel is not lost.The switching of known third switch T3 and the 9th
Device T9 is NMOS, and the 4th switch T4 and the tenth switch T10 are PMOS, so third timing control line CKH3 output is high
Level signal, the 4th timing control line CKH4 export high level signal, and the 8th timing control line CKH8 exports low level signal.
5th timing control line CKH5 controls the 5th switch T5 and opens, the 6th switching of the 6th timing control line CKH6 control
Device T6 is opened, so that the first data signal transmission is guaranteed aobvious to third data line D3 by the driving of large scale switching circuit 111
Show that the positive frame charging ability of panel is not lost；Meanwhile the 5th timing control line CKH5 control the 11st switch T11 open,
9th timing control line CKH9 controls the 12nd switch T12 and closes, so that the second data signal transmission to the 6th data line D6,
It is driven by small size switching circuit 111 to achieve the effect that reduce display panel power consumption.Known 5th switch T5 and
11 switch T11 are NMOS, and the 6th switch T6 and the 12nd switch T12 are PMOS, so the 5th timing control
Line CKH5 exports high level signal, and the 6th timing control line CKH6 exports low level signal, the 9th timing control line CKH9 output
High level signal.
As shown in Figure 2 B, m+1 frame image is shown, when the first data-signal is negative sense data mode and the second data-signal
When for positive data mode, the first timing control line CKH1 controls the first switch T1 and opens, the second timing control line CKH2 control
The second switch T2 closing is made, so that the first data signal transmission to the first data line D1, that is, pass through small size switching circuit 111
Driving is to achieve the effect that reduce display panel power consumption；Meanwhile first timing control line CKH1 control the 7th switch T7 open,
7th timing control line CKH7 controls the 8th switch T8 and opens, so that the second data signal transmission to the 4th data line D4, i.e.,
It is driven by large scale switching circuit 111 and guarantees that the positive frame charging ability of display panel is not lost.Known first switch T1
It is NMOS with the 7th switch T7, the second switch T2 and the 8th switch T8 are PMOS, so the first timing control line
CKH1 exports high level signal, and the second timing control line CKH2 exports high level signal, and the 7th timing control line CKH7 output is low
Level signal.
Third timing control line CKH3 controls third switch T3 and opens, the 4th switching of the 4th timing control line CKH4 control
Device T4 is opened, so that the second data signal transmission to the second data line D2, i.e., guaranteed aobvious by the driving of large scale switching circuit 111
Show that the positive frame charging ability of panel is not lost；Meanwhile third timing control line CKH3 controls the 9th switch T9 and opens, the 8th
Timing control line CKH8 controls the tenth switch T10 and closes, so that the first data signal transmission passes through to the 5th data line D5
The driving of small size switching circuit 111 is to achieve the effect that reduce display panel power consumption.The switching of known third switch T3 and the 9th
Device T9 is NMOS, and the 4th switch T4 and the tenth switch T10 are PMOS, so third timing control line CKH3 output is high
Level signal, the 4th timing control line CKH4 export low level signal, and the 8th timing control line CKH8 exports high level signal.
5th timing control line CKH5 controls the 5th switch T5 and opens, the 6th switching of the 6th timing control line CKH6 control
Device T6 is closed, so that the first data signal transmission is driven to third data line D3 by small size switching circuit 111 to reach
Reduce the effect of display panel power consumption；Meanwhile the 5th timing control line CKH5 control the 11st switch T11 and open, when the 9th
Sequence control line CKH9 controls the 12nd switch T12 and opens, so that the second data signal transmission passes through to the 6th data line D6
The driving of large scale switching circuit 111 guarantees that the positive frame charging ability of display panel is not lost.Known 5th switch T5 and
11 switch T11 are NMOS, and the 6th switch T6 and the 12nd switch T12 are PMOS, so the 5th timing control
Line CKH5 exports high level signal, and the 6th timing control line CKH6 exports high level signal, the 9th timing control line CKH9 output
Low level signal.
The schematic diagram of the data drive circuit of the display panel provided as shown in Figure 3A for another embodiment of the present invention.With
The difference of data drive circuit shown in Fig. 2A is, in the data drive circuit of display panel provided in this embodiment, first is cut
Parallel operation T1, the second switch T2, third switch T3, the 4th switch T4, the 5th switch T5, the 6th switch T6, the 7th
Switch T7, the 8th switch T8, the 9th switch T9, the tenth switch T10, the switching of the 11st switch T11 and the 12nd
Device T12 is made of a NMOS transistor.It will be apparent that first switching of each switching circuit 111 in the present embodiment
Device is respectively T1, T3, T5, T7, T9 and T11, in the present embodiment second switch of each switching circuit 111 as shown in Figure 3A
Respectively T2, T4, T6, T8, T10 and T12.
The driver' s timing of the obvious data drive circuit is as shown in Figure 3B.M frame image is shown, when the first data-signal is
When forward data state and the second data-signal are negative sense data mode, the first timing control line CKH1 exports high level signal,
Second timing control line CKH2 exports high level signal, and the 7th timing control line CKH7 exports low level signal.Third timing control
Line CKH3 processed exports high level signal, and the 4th timing control line CKH4 exports low level signal, and the 8th timing control line CKH8 is defeated
High level signal out.5th timing control line CKH5 exports high level signal, and the 6th timing control line CKH6 exports high level letter
Number, the 9th timing control line CKH9 exports low level signal.It is driven from there through large scale switching circuit 111 and guarantees display panel
Positive frame charging ability be not lost, and driven by small size switching circuit 111 to reach and reduce display panel power consumption
Effect.
M+1 frame image is shown, when the first data-signal is negative sense data mode and the second data-signal is forward data
When state, the first timing control line CKH1 output high level signal, the second timing control line CKH2 output low level signal, the 7th
Timing control line CKH7 exports high level signal.Third timing control line CKH3 exports high level signal, the 4th timing control line
CKH4 exports high level signal, and the 8th timing control line CKH8 exports low level signal.5th timing control line CKH5 output is high
Level signal, the 6th timing control line CKH6 export low level signal, and the 9th timing control line CKH9 exports high level signal.By
This guarantees that the positive frame charging ability of display panel is not lost by the driving of large scale switching circuit 111, and passes through small size
The driving of switching circuit 111 is to achieve the effect that reduce display panel power consumption.
The schematic diagram of the data drive circuit of the display panel provided as shown in Figure 4 A for further embodiment of the present invention.Such as
Shown in figure, the data drive circuit of the display panel includes multiple switching circuit groups 110, each switching circuit group 110 includes
At least four switching circuits 111；One switching circuit group 110 includes, respectively with the first data lead S1, the first timing control line
CKH1 and the first data line D1 electrical connection the first switch T1, respectively with the first data lead S1, the second timing control line
Second switch T2, the first data lead S1 of CKH2 and the first data line D1 electrical connection is used for transmission the first data-signal；Point
The third switch T3 not being electrically connected with the second data lead S2, third timing control line CKH3 and the second data line D2, respectively
The 4th switch T4 being electrically connected with the second data lead S2, the 4th timing control line CKH4 and the second data line D2, the second number
The second data-signal is used for transmission according to lead S2；Respectively with the first data lead S1, third timing control line CKH3 and third number
According to line D3 be electrically connected the 5th switch T5, respectively with the first data lead S1, the 5th timing control line CKH5 and third data
6th switch T6 of line D3 electrical connection；Respectively with the second data lead S2, the first timing control line CKH1 and the 4th data line
D4 electrical connection the 7th switch T7, respectively with the second data lead S2, the 6th timing control line CKH6 and the 4th data line D4
8th switch T8 of electrical connection.
Optional first data line D1, the second data line D2, third data line D3 and the 4th data line D4 in the present embodiment
The sub-pixel of corresponding driving is tactic red, green, blue and white sub-pixels.It will be understood by those skilled in the art that display
The sub-pixel colors sequence arrangement of panel can also be red, green, blue, and red, green, blue does not limit display panel in the present invention
Sub-pixel.For example, also optional first data line, the second data line, third data line and the 4th in other embodiments of the present invention
The sub-pixel of the corresponding driving of data line is tactic red, green, blue and yellow sub-pixel.
A data lead drives two data lines, therefore this implementation in each switching circuit group 110 in the present embodiment
The data drive circuit that example provides is 2:4CMOS data drive circuit, it will be understood by those skilled in the art that in other embodiments
In also optional data drive circuit be 1:n cmos data driving circuit, details are not described herein.In the present embodiment optional first
Switch T1, third switch T3, the 5th switch T5 and the 7th switch T7 are made of a NMOS transistor；Second cuts
Parallel operation T2, the 4th switch T4, the 6th switch T6 and the 8th switch T8 are made of a PMOS transistor.Obviously
, first switch of each switching circuit 111 is respectively T1, T3, T5 and T7 in the present embodiment, in the present embodiment as schemed
Second switch of each switching circuit 111 shown in 4A is respectively T2, T4, T6 and T8.It will be understood by those skilled in the art that the
The type of the one switch T8 of switch T1~the 8th includes but is not limited to above example, also optional first is cut in other embodiments
The switch T8 of parallel operation T1~the 8th is NMOS or is PMOS3, and details are not described herein.
The display panel optional in the present embodiment is column overturning drive mode, specifically, display panel shows former frame
When image, the first data-signal is positive data mode, and the second data-signal is negative sense data mode；Display panel shows latter
When frame image, the first data-signal is negative sense data mode, and the second data-signal is positive data mode.Those skilled in the art
It is appreciated that the drive mode of display panel includes but is not limited to arrange overturning, display panel provided by the invention is applied also for a little
The drive modes such as overturning, row overturning and frame overturning, details are not described herein.
The smaller data drive circuit that will lead to of Vgs based on NMOS is poor in positive frame charging ability, therefore the number of the present embodiment
Be according to the driving principle of driving circuit: display panel before display a frame image when, signal polarity is positive polar first data
Two switch of each switching circuit 111 corresponding to lead S1 open simultaneously, ensure that large-sized switching circuit 111 into
Row driving；And be negative first of each switching circuit 111 corresponding to polar second data lead S2 of signal polarity cuts
Parallel operation is opened, and is driven using small size switching circuit 111.
Display panel after the display a frame image when, signal polarity is negative every corresponding to polar first data lead S1
First switch of a switching circuit 111 is opened, and is driven using small size switching circuit 111；Signal polarity is anode
Two switch of each switching circuit 111 corresponding to the second data lead S2 of property open simultaneously, and ensure that large-sized
Switching circuit 111 is driven.Therefore in the present embodiment, data drive circuit is guaranteed by the driving of large scale switching circuit 111
The positive frame charging ability of display panel is not lost；And it is driven by small size switching circuit 111 and guarantees the negative of display panel
Frame charging ability also reduces the size of switching circuit simultaneously to reach the power consumption of reduction data drive circuit and then reduce display
The effect of panel power consumption.
It will be apparent that by taking m frame image and m+1 frame image are shown as an example, it is provided in this embodiment as shown in Figure 4 B
The driver' s timing of data drive circuit is: display m frame image, when the first data-signal is positive data mode and the second data
When signal is negative sense data mode, the first timing control line CKH1 controls the first switch T1 and opens, the second timing control line
CKH2 controls the second switch T2 and opens, so that the first data signal transmission to the first data line D1, i.e., switched by large scale
The driving of circuit 111 guarantees that the positive frame charging ability of display panel is not lost；Meanwhile first timing control line CKH1 control the 7th
Switch T7 is opened, and the 6th timing control line CKH6 controls the 8th switch T8 and closes, so that the second data signal transmission is to the
Four data line D4 are driven by small size switching circuit 111 to achieve the effect that reduce display panel power consumption.Known first cuts
Parallel operation T1 and the 7th switch T7 is NMOS, and the second switch T2 and the 8th switch T8 are PMOS, so the first timing
Control line CKH1 exports high level signal, and the second timing control line CKH2 exports low level signal, the 6th timing control line CKH6
Export high level signal.
Third timing control line CKH3 controls third switch T3 and opens, the 4th switching of the 4th timing control line CKH4 control
Device T4 is closed, so that the second data signal transmission to the second data line D2, i.e., driven by small size switching circuit 111 to reach
Reduce the effect of display panel power consumption；Meanwhile third timing control line CKH3 controls the 5th switch T5 and opens, the 5th timing control
Line CKH5 processed controls the 6th switch T6 and opens, so that the first data signal transmission passes through large scale to third data line D3
The driving of switching circuit 111 guarantees that the positive frame charging ability of display panel is not lost.The switching of known third switch T3 and the 5th
Device T5 is NMOS, and the 4th switch T4 and the 6th switch T6 are PMOS, so third timing control line CKH3 output is high
Level signal, the 4th timing control line CKH4 export high level signal, and the 5th timing control line CKH5 exports low level signal.
As shown in Figure 4 B, m+1 frame image is shown, when the first data-signal is negative sense data mode and the second data-signal
When for positive data mode, the first timing control line CKH1 controls the first switch T1 and opens, the second timing control line CKH2 control
The second switch T2 closing is made, so that the first data signal transmission to the first data line D1, that is, pass through small size switching circuit 111
Driving is to achieve the effect that reduce display panel power consumption；Meanwhile first timing control line CKH1 control the 7th switch T7 open,
6th timing control line CKH6 controls the 8th switch T8 and opens, so that the second data signal transmission to the 4th data line D4, i.e.,
It is driven by large scale switching circuit 111 and guarantees that the positive frame charging ability of display panel is not lost.Known first switch T1
It is NMOS with the 7th switch T7, the second switch T2 and the 8th switch T8 are PMOS, so the first timing control line
CKH1 exports high level signal, and the second timing control line CKH2 exports high level signal, and the 6th timing control line CKH6 output is low
Level signal.
Third timing control line CKH3 controls third switch T3 and opens, the 4th switching of the 4th timing control line CKH4 control
Device T4 is opened, so that the second data signal transmission to the second data line D2, i.e., guaranteed aobvious by the driving of large scale switching circuit 111
Show that the positive frame charging ability of panel is not lost；Meanwhile third timing control line CKH3 controls the 5th switch T5 and opens, the 5th
Timing control line CKH5 controls the 6th switch T6 and closes, so that the first data signal transmission passes through to third data line D3
The driving of small size switching circuit 111 is to achieve the effect that reduce display panel power consumption.The switching of known third switch T3 and the 5th
Device T5 is NMOS, and the 4th switch T4 and the 6th switch T6 are PMOS, so third timing control line CKH3 output is high
Level signal, the 4th timing control line CKH4 export low level signal, and the 5th timing control line CKH5 exports high level signal.
The schematic diagram of the data drive circuit of the display panel provided as shown in Figure 5A for another embodiment of the invention.With
The difference of data drive circuit shown in Fig. 4 A is, in the data drive circuit of display panel provided in this embodiment, first is cut
Parallel operation T1, the second switch T2, third switch T3, the 4th switch T4, the 5th switch T5, the 6th switch T6, the 7th
Switch T7 and the 8th switch T8 are made of a NMOS transistor.It will be apparent that each switching is electric in the present embodiment
First switch on road 111 is respectively T1, T3, T5 and T7, in the present embodiment the of each switching circuit 111 as shown in Figure 2 A
Two switch are respectively T2, T4, T6 and T8.
The driver' s timing of the obvious data drive circuit is as shown in Figure 5 B.M frame image is shown, when the first data-signal is
When forward data state and the second data-signal are negative sense data mode, the first timing control line CKH1 exports high level signal,
Second timing control line CKH2 exports high level signal, and the 6th timing control line CKH6 exports low level signal.Third timing control
Line CKH3 processed exports high level signal, and the 4th timing control line CKH4 exports low level signal, and the 5th timing control line CKH5 is defeated
High level signal out.It is driven from there through large scale switching circuit 111 and guarantees that the positive frame charging ability of display panel is not lost,
And it is driven by small size switching circuit 111 to achieve the effect that reduce display panel power consumption.
M+1 frame image is shown, when the first data-signal is negative sense data mode and the second data-signal is forward data
When state, the first timing control line CKH1 output high level signal, the second timing control line CKH2 output low level signal, the 6th
Timing control line CKH6 exports high level signal.Third timing control line CKH3 exports high level signal, the 4th timing control line
CKH4 exports high level signal, and the 5th timing control line CKH5 exports low level signal.From there through large scale switching circuit 111
Driving guarantees that the positive frame charging ability of display panel is not lost, and is driven by small size switching circuit 111 to reach drop
The effect of low display panel power consumption.
On the basis of above-mentioned any embodiment, the embodiment of the present invention also provides a kind of display panel, the display panel packet
Include data drive circuit described in driving chip and any embodiment as above.The number of specific driving chip and data drive circuit
It is electrically connected according to lead, first control line and Article 2 control line, for applying data-signal to data lead, is controlled to first
Line processed applies the first timing control signal, and applies second of timing control signal to Article 2 control line, wherein data
Signal has forward data state and negative sense data mode.
When driving chip applies the data-signal of forward data state to data lead, driving chip is to first control line
Apply the timing control signal that first switch of control is opened while driving chip applies control second to Article 2 control line
The timing control signal that a switch is opened, first switch and second switch are simultaneously by received data signal transmission
To the data line of electrical connection；When driving chip applies the data-signal of negative sense data mode to data lead, driving chip is to the
One control line applies the timing control signal that first switch of control is opened, and first switch is by received data-signal
It is transmitted to the data line of electrical connection.
Carry out the attached drawing example of display panel, the display as shown in Figure 6 shown in Fig. 2A for data drive circuit herein
Panel includes driving chip 200 and data drive circuit 100 as shown in Figure 2 A.Specific driving chip 200 controls data and drives
The process of dynamic circuit 100 is described in detail in the above-described embodiments, and details are not described herein.
Display panel provided in this embodiment, in data drive circuit, when data-signal is positive data mode, each
First switch and second switch in switching circuit open simultaneously, and ensure that large-sized switching circuit is driven
It is dynamic；When data-signal is negative sense data mode, first switch in each switching circuit opens second switching simultaneously
Device is closed, and is driven using small size switching circuit.The obvious display panel is guaranteed aobvious by the driving of large scale switching circuit
Show that the positive frame charging ability of panel is not lost, the negative frame charging ability for guaranteeing display panel is driven by small size switching circuit
The size of switching circuit is also reduced simultaneously, it is clear that, compared with prior art, data drive circuit reduces at least
25% power consumption has achieved the effect that reduce display panel power consumption.
The embodiment of the present invention also provides a kind of display device, which includes display panel as described above.At this
The optional display device is that smart phone etc. shows equipment in embodiment.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (18)
1. a kind of data drive circuit of display panel, including at least one switching circuit, the switching circuit includes two and cuts
Parallel operation, wherein the output end of first switch is electrically connected with a data line, input terminal is electrically connected with a data lead,
And control terminal is electrically connected with first control line, under the control of first control line, first switch is beaten
On or off is closed, and will be from the received data signal transmission of the data lead to the data line when opening, second switching
The output end of device is electrically connected with the data line, input terminal is electrically connected with the data lead and control terminal and Article 2 control
Line electrical connection processed, under the control of the Article 2 control line, second switch is opened or closed, and will when opening
From the received data signal transmission of the data lead to the data line, which is characterized in that
The data-signal has forward data state and negative sense data mode, when the data-signal is positive data mode
When, first switch described in the first control line traffic control opens described in the Article 2 control line traffic control simultaneously second
Switch is opened, when the data-signal is negative sense data mode, first switching described in the first control line traffic control
Device is opened second switch described in the Article 2 control line traffic control simultaneously and is closed.
2. data drive circuit according to claim 1, which is characterized in that the data drive circuit includes multiple switchings
Circuit group, each described switching circuit group include at least six switching circuits；
The one switching circuit group includes,
The first switch being electrically connected respectively with the first data lead, the first timing control line and the first data line, respectively with institute
State the second switch of the first data lead, the second timing control line and first data line electrical connection, first data
Lead is used for transmission the first data-signal；
The third switch being electrically connected respectively with the second data lead, third timing control line and the second data line, respectively with institute
State the 4th switch of the second data lead, the 4th timing control line and second data line electrical connection, second data
Lead is used for transmission the second data-signal；
The 5th switch being electrically connected respectively with first data lead, the 5th timing control line and third data line, respectively
The 6th switch being electrically connected with first data lead, the 6th timing control line and the third data line；
The 7th switch being electrically connected respectively with second data lead, the first timing control line and the 4th data line,
The 8th switch being electrically connected respectively with second data lead, the 7th timing control line and the 4th data line；
The 9th switch being electrically connected respectively with first data lead, the third timing control line and the 5th data line,
The tenth switch being electrically connected respectively with first data lead, the 8th timing control line and the 5th data line；
The 11st switching being electrically connected respectively with second data lead, the 5th timing control line and the 6th data line
Device, the 12nd switch being electrically connected respectively with second data lead, the 9th timing control line and the 6th data line.
3. data drive circuit according to claim 2, which is characterized in that
When the display panel shows previous frame image, first data-signal is positive data mode, second data
Signal is negative sense data mode；
When the display panel shows a later frame image, first data-signal is negative sense data mode, second data
Signal is positive data mode.
4. data drive circuit according to claim 3, which is characterized in that first switch, third switching
Device, the 5th switch, the 7th switch, the 9th switch and the 11st switch are by a NMOS
Transistor composition；
Second switch, the 4th switch, the 6th switch, the 8th switch, the tenth switching
Device and the 12nd switch are made of a PMOS transistor.
5. data drive circuit according to claim 3, which is characterized in that first switch, second switching
Device, the third switch, the 4th switch, the 5th switch, the 6th switch, the 7th switching
Device, the 8th switch, the 9th switch, the tenth switch, the 11st switch and the described 12nd
Switch is made of a NMOS transistor.
6. data drive circuit according to claim 4 or 5, which is characterized in that when first data-signal is forward direction
When data mode and second data-signal are negative sense data mode,
First switch described in the first timing control line traffic control is opened, and second cuts described in the second timing control line traffic control
Parallel operation is opened, so that first data signal transmission is to first data line；Meanwhile the first timing control line traffic control
7th switch is opened, and the 8th switch described in the 7th timing control line traffic control is closed, so that second data
Signal is transmitted to the 4th data line；
Third switch described in the third timing control line traffic control is opened, and the 4th cuts described in the 4th timing control line traffic control
Parallel operation is closed, so that second data signal transmission is to second data line；Meanwhile the third timing control line traffic control
9th switch is opened, and the tenth switch described in the 8th timing control line traffic control is opened, so that first data
Signal is transmitted to the 5th data line；
5th switch described in the 5th timing control line traffic control is opened, and the 6th cuts described in the 6th timing control line traffic control
Parallel operation is opened, so that first data signal transmission is to the third data line；Meanwhile the 5th timing control line traffic control
11st switch is opened, and the 12nd switch described in the 9th timing control line traffic control is closed, so that described second
Data signal transmission is to the 6th data line.
7. data drive circuit according to claim 4 or 5, which is characterized in that when first data-signal is negative sense
When data mode and second data-signal are positive data mode,
First switch described in the first timing control line traffic control is opened, and second cuts described in the second timing control line traffic control
Parallel operation is closed, so that first data signal transmission is to first data line；Meanwhile the first timing control line traffic control
7th switch is opened, and the 8th switch described in the 7th timing control line traffic control is opened, so that second data
Signal is transmitted to the 4th data line；
Third switch described in the third timing control line traffic control is opened, and the 4th cuts described in the 4th timing control line traffic control
Parallel operation is opened, so that second data signal transmission is to second data line；Meanwhile the third timing control line traffic control
9th switch is opened, and the tenth switch described in the 8th timing control line traffic control is closed, so that first data
Signal is transmitted to the 5th data line；
5th switch described in the 5th timing control line traffic control is opened, and the 6th cuts described in the 6th timing control line traffic control
Parallel operation is closed, so that first data signal transmission is to the third data line；Meanwhile the 5th timing control line traffic control
11st switch is opened, and the 12nd switch described in the 9th timing control line traffic control is opened, so that described second
Data signal transmission is to the 6th data line.
8. data drive circuit according to claim 2, which is characterized in that first data line, second data
The sub- picture of the corresponding driving of line, the third data line, the 4th data line, the 5th data line and the 6th data line
Element is tactic red, green, blue, red, green, blue sub-pixels.
9. data drive circuit according to claim 1, which is characterized in that the data drive circuit includes multiple switchings
Circuit group, each described switching circuit group include at least four switching circuits；
The one switching circuit group includes,
The first switch being electrically connected respectively with the first data lead, the first timing control line and the first data line, respectively with institute
State the second switch of the first data lead, the second timing control line and first data line electrical connection, first data
Lead is used for transmission the first data-signal；
The third switch being electrically connected respectively with the second data lead, third timing control line and the second data line, respectively with institute
State the 4th switch of the second data lead, the 4th timing control line and second data line electrical connection, second data
Lead is used for transmission the second data-signal；
The 5th switch being electrically connected respectively with first data lead, the third timing control line and third data line,
The 6th switch being electrically connected respectively with first data lead, the 5th timing control line and the third data line；
The 7th switch being electrically connected respectively with second data lead, the first timing control line and the 4th data line,
The 8th switch being electrically connected respectively with second data lead, the 6th timing control line and the 4th data line.
10. data drive circuit according to claim 9, which is characterized in that
When the display panel shows previous frame image, first data-signal is positive data mode, second data
Signal is negative sense data mode；
When the display panel shows a later frame image, first data-signal is negative sense data mode, second data
Signal is positive data mode.
11. data drive circuit according to claim 10, which is characterized in that first switch, the third are cut
Parallel operation, the 5th switch and the 7th switch are made of a NMOS transistor；
Second switch, the 4th switch, the 6th switch and the 8th switch are by a PMOS
Transistor composition.
12. data drive circuit according to claim 10, which is characterized in that first switch, described second cut
Parallel operation, the third switch, the 4th switch, the 5th switch, the 6th switch, the 7th switching
Device and the 8th switch are made of a NMOS transistor.
13. data drive circuit according to claim 11 or 12, which is characterized in that when first data-signal is positive
When to data mode and second data-signal being negative sense data mode,
First switch described in the first timing control line traffic control is opened, and second cuts described in the second timing control line traffic control
Parallel operation is opened, so that first data signal transmission is to first data line；Meanwhile the first timing control line traffic control
7th switch is opened, and the 8th switch described in the 6th timing control line traffic control is closed, so that second data
Signal is transmitted to the 4th data line；
Third switch described in the third timing control line traffic control is opened, and the 4th cuts described in the 4th timing control line traffic control
Parallel operation is closed, so that second data signal transmission is to second data line；Meanwhile the third timing control line traffic control
5th switch is opened, and the 6th switch described in the 5th timing control line traffic control is opened, so that first data
Signal is transmitted to the third data line.
14. data drive circuit according to claim 11 or 12, which is characterized in that when first data-signal is negative
When to data mode and second data-signal being positive data mode,
First switch described in the first timing control line traffic control is opened, and second cuts described in the second timing control line traffic control
Parallel operation is closed, so that first data signal transmission is to first data line；Meanwhile the first timing control line traffic control
7th switch is opened, and the 8th switch described in the 6th timing control line traffic control is opened, so that second data
Signal is transmitted to the 4th data line；
Third switch described in the third timing control line traffic control is opened, and the 4th cuts described in the 4th timing control line traffic control
Parallel operation is opened, so that second data signal transmission is to second data line；Meanwhile the third timing control line traffic control
5th switch is opened, and the 6th switch described in the 5th timing control line traffic control is closed, so that first data
Signal is transmitted to the third data line.
15. data drive circuit according to claim 9, which is characterized in that first data line, second data
The sub-pixel of the corresponding driving of line, the third data line and the 4th data line is tactic red, green, blue and white
Pixel；Alternatively,
The son of the corresponding driving of first data line, second data line, the third data line and the 4th data line
Pixel is tactic red, green, blue and yellow sub-pixel.
16. a kind of display panel, which is characterized in that driven including driving chip and such as the described in any item data of claim 1-15
Dynamic circuit.
17. display panel according to claim 16, which is characterized in that
Data lead, first control line and the Article 2 control line of the driving chip and the data drive circuit are electrically connected
It connects, for applying data-signal to the data lead, first control line of Xiang Suoshu applies the first timing control signal, with
And apply second of timing control signal to the Article 2 control line, wherein the data-signal has forward data state
With negative sense data mode；
When the driving chip applies the data-signal of forward data state to the data lead, the driving chip is to described
First control line apply control timing control signal that first switch is opened simultaneously the driving chip to described
Article 2 control line, which applies, controls the timing control signal that second switch is opened, first switch and described
Second switch is simultaneously by the received data signal transmission to the data line of electrical connection；
When the driving chip applies the data-signal of negative sense data mode to the data lead, the driving chip is to described
First control line, which applies, controls the timing control signal that first switch is opened, and first switch will receive
The data signal transmission to electrical connection the data line.
18. a kind of display device, which is characterized in that including such as described in any item display panels of claim 16-17.
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| CN107274853B (en) * | 2017-08-17 | 2020-04-24 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN108776401A (en) * | 2018-05-31 | 2018-11-09 | 武汉华星光电技术有限公司 | Pixel substrate, liquid crystal display panel and liquid crystal display |
| US10777157B2 (en) | 2018-05-31 | 2020-09-15 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display panel having pixel units with difference storage capacitance |
| CN113990265B (en) * | 2018-06-25 | 2023-06-30 | 矽创电子股份有限公司 | Driving method and driving circuit thereof |
| CN115064134A (en) * | 2022-07-04 | 2022-09-16 | 福建华佳彩有限公司 | Demux circuit for improving charging rate of panel positive frame and driving method thereof |
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