CN106649899A - Local memory layout method - Google Patents
Local memory layout method Download PDFInfo
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- CN106649899A CN106649899A CN201510717117.6A CN201510717117A CN106649899A CN 106649899 A CN106649899 A CN 106649899A CN 201510717117 A CN201510717117 A CN 201510717117A CN 106649899 A CN106649899 A CN 106649899A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/06—Structured ASICs
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention relates to a local memory layout method. The method comprises the following steps of mapping chip logic resources of local memories in a user design module; and carrying out constraint detection and conflict analysis on the mapped logic resources. According to the method, resource mapping is carried out on various local memories to ensure that uniform mixed layout is carried out on the chip logic resources, so that layout optimization under mixed constraint can be carried out on the various local memories to avoid layout conflict and save the chip logic resources.
Description
Technical field
The present invention relates to the IC design technical field in microelectronic, particularly a kind of local storage layout side
Method.
Background technology
FPGA is a kind of logic device with abundant hardware resource, powerful parallel processing capability and flexible reconfigurable ability
Part.These features cause FPGA to obtain increasing extensively application in many fields such as data processing, communication, network.
At present, at the scene in programmable gate array (Field Programmable Gate Array, FPGA) application, it is desirable to
Integrated circuit has programmable or configurable interference networks, and gate is connected to each other by configurable interference networks.Make
Extensively it has been applied in a large amount of microelectronic devices for the FPGA that core in individual chips or system is worked.Broad sense
FPGA gate definition, singly do not refer to simple NAND gate, also refer to the combinational logic with configurable functionality and sequential
The logical block (LE, Logic Element) of logic or the logical block for being interconnected and being constituted by multiple logical blocks.
At present industrial quarters does not also propose to ensure that different types of local storage LRAM in solution FPGA well
(Local-RAM) and look-up table (LUT) layout module layout method.
The content of the invention
The purpose of the present invention is the defect for prior art, there is provided a kind of local storage layout method, the method pair
Different types of local storage carries out logical resource mapping, the constraint checking and conflict analysis after then being mapped, with complete
Into different types of mixed layout, such that it is able to be prevented effectively from layout conflict.
The present invention provides a kind of local storage layout method, and the method includes：Local storage in module is designed to user
Carry out the mapping of chip logic resource；Carry out the constraint detection and conflict analysis of logical resource after the mapping.
Preferably, before the local storage in the design module to user carries out the mapping step of chip logic resource,
All modules of traverse user design, find and store different types of local storage.
Preferably, it is described that the mapping step that the local storage that user is designed in module carries out chip logic resource is included：It is right
Different types of local storage carries out respectively 1 couple of n mappings that client layer module is tied to chip-scale constraint, and to quilt
The chip logic resource of mapping is marked.
Preferably, the coordinate position of the line module is mapped on the logical resource of the chip, and to user's mould
It is marked using actual example on block coordinate position, other launch to be marked using actual situation example on n-1 positions.
Preferably, the constraint detecting step for carrying out logical resource after the mapping includes：It is identical in single logical block
On coordinate position, to the first coordinate shared by the labeled chip logic resource and labeled chip logic resource institute
The second coordinate for accounting for is detected.
Preferably, the conflict analysis step includes：Whether first coordinate is same coordinate with second coordinate, if
Coordinate is identical, then conflict is present；If coordinate is differed, then there is no conflict.
Preferably, the position of the same coordinate is that the labeled chip logic resource first takes：If there is conflict, just
The not labeled chip logic resource is removed to another coordinate, and the not labeled logical resource is carried out repeating inspection
The process with conflict analysis is surveyed, till conflict is not present；If there is no conflict, the chip not just being labeled described in fixation
Logical resource.
Preferably, the same coordinate is that the not labeled chip logic resource first takes：If there is conflict, just remove
The labeled chip logic resource to another coordinate, and the labeled chip logic resource is carried out duplicate detection and
The process of conflict analysis, till conflict is not present；If there is no conflict, just the fixation labeled chip logic is provided
Source.
Preferably, another coordinate is the coordinate position on chip in other logical blocks.
A kind of local storage layout method that the present invention is provided, the method carries out logic money to different types of local storage
Source maps, the constraint checking and conflict analysis after then being mapped, to complete different types of mixed layout, such that it is able to
It is prevented effectively from layout conflict.Meanwhile, also save chip logic resource.
Description of the drawings
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, embodiment will be described below needed for be used it is attached
Figure is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, on the premise of not paying creative work, can be attached to obtain others according to these accompanying drawings
Figure.
Fig. 1 provides a kind of local storage layout method schematic flow sheet for the embodiment of the present invention；
Fig. 2 is FPGA local storages LRAM schematic diagrames provided in an embodiment of the present invention；
Fig. 3 a are local storage LRAM64 provided in an embodiment of the present invention × 1SP esource impact schematic diagrames；
Fig. 3 b are local storage LRAM128 provided in an embodiment of the present invention × 1SP esource impact schematic diagrames；
Fig. 3 c are local storage LRAM256 provided in an embodiment of the present invention × 1SP esource impact schematic diagrames；
Fig. 4 is local storage LRAM256 provided in an embodiment of the present invention × 1SP esource impact conflict graph schematic diagrames；
Fig. 5 is the layout schematic flow sheet of another local storage provided in an embodiment of the present invention；
Fig. 6 is a kind of basic logic unit schematic diagram provided in an embodiment of the present invention.
Specific embodiment
To make purpose, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
Accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
The a part of embodiment of the present invention, rather than the embodiment of whole.
The purpose of the present invention is the defect for prior art, there is provided a kind of local storage layout method, the method pair
Different types of local storage carries out logical resource mapping, the constraint checking and conflict analysis after then being mapped, with complete
Into different types of mixed layout, such that it is able to be prevented effectively from layout conflict.Meanwhile, also save chip logic resource.
Fig. 1 provides a kind of local storage layout method schematic flow sheet for the embodiment of the present invention.As shown in figure 1, one kind is originally
The layout method of ground memory includes step S101-S102：
Step S101：The mapping of chip logic resource is carried out to the local storage that user is designed in module；
Step S102：Carry out the constraint detection and conflict analysis of logical resource after the mapping.
Specifically, before the local storage in the design module to user carries out the mapping step of chip logic resource,
All modules of traverse user design, find and store different types of local storage.
Specifically, it is described that the mapping step that the local storage that user is designed in module carries out chip logic resource is included：It is right
Different types of local storage carries out respectively 1 couple of n mappings that client layer module is tied to chip-scale constraint, and to quilt
The chip logic resource of mapping is marked.
Specifically, the coordinate position of the line module is mapped on the logical resource of the chip, and to user's mould
It is marked using actual example on block coordinate position, other launch to be marked using actual situation example on n-1 positions.
Specifically, the constraint detecting step for carrying out logical resource after the mapping includes：It is identical in single logical block
On coordinate position, to the first coordinate shared by the labeled chip logic resource and labeled chip logic resource institute
The second coordinate for accounting for is detected.
Specifically, the conflict analysis step includes：Whether first coordinate is same coordinate with second coordinate, if
Coordinate is identical, then conflict is present；If coordinate is differed, then there is no conflict.
Specifically, the position of the same coordinate is that the labeled chip logic resource first takes：If there is conflict, just
The not labeled chip logic resource is removed to another coordinate, and the not labeled logical resource is carried out repeating inspection
The process with conflict analysis is surveyed, till conflict is not present；If there is no conflict, the chip not just being labeled described in fixation
Logical resource.
Specifically, the same coordinate is that the not labeled chip logic resource first takes：If there is conflict, just remove
The labeled chip logic resource to another coordinate, and the labeled chip logic resource is carried out duplicate detection and
The process of conflict analysis, till conflict is not present；If there is no conflict, just the fixation labeled chip logic is provided
Source.
Specifically, another coordinate is the coordinate position on chip in other logical blocks.
The present invention to different types of local storage by carrying out esource impact so that is unified in chip logic resource
Mixed layout, can carry out the layout optimization under mixed constraints to different types of local storage, so as to avoid layout conflict,
Chip logic resource is saved simultaneously.
Fig. 2 is FPGA local storages LRAM schematic diagrames provided in an embodiment of the present invention.As shown in Fig. 2 locally depositing
The input signal of reservoir LRAM is di0, f [5], f [4:0]、we、preda[4:0]、preda[7:0], output signal be x, xy,
shifout。
Fig. 3 a are local storage LRAM64 provided in an embodiment of the present invention × 1SP esource impact schematic diagrames.Such as Fig. 3 a institutes
Show, the classification of local storage LRAM is divided with its storage size, LRAM64 × 1SP can only be stored with 16
The look-up table LUT of input, when logical resource mapping is carried out, the coordinate position of local storage is mapped to from line module
On the logical resource of chip, and it is marked using actual example on the coordinate position of local storage.
All modules of user's design include：Look-up table means (Lookup table-LUT), register module
(Register-Reg), local storage module (Local memory lram-LRAM), input/output module (Input
Output-IO), embedded storage module (Embedded storage-EMB), Digital Sound Processor module (Digital
Sound field processor-DSP) etc., it is numerous to list herein.
The logical resource of chip, including the look-up table (Lookup table-LUT) of chip, 2 adders (Adder-ADD),
The resources such as 4 registers (Register-Reg), it is numerous to list herein.
It is divided into programmed logical module PLB (Programmable Logic Block) in CME-C1 model fpga chips
With programmed logical module PLBR with local storage (Programmable Logic Block Local memory lram),
In the chips the ratio shared by PLBR and PLB is 1:1, but the area shared by PLBR is big.
Each PLB includes logical block LE and the line inside logical block.One basic logic chip bag
Include look-up table (Lookup table-LUT), 2 adders (Adder-ADD), 4 registers of 26 inputs
(Register-Reg)。
Fig. 6 is a kind of basic logic unit schematic diagram provided in an embodiment of the present invention.As shown in fig. 6, CME-C1 models
In the framework of field programmable gate array (Field Programmable Gate Array, FPGA), a basic logic list
The schematic diagram of unit.One basic logic unit (Logic Element, LE) include 4 basic programmable logic chips (LP,
Logic Parcel), that is, LP0, LP1, LP2, LP3.One basic logic chip includes the look-up table of 26 inputs
(Lookup table-LUT), 2 adders (Adder-ADD), 4 registers (Register-Reg).
Because of the area shared by PLBR greatly, therefore after line module mapping can not be located in same logic chip LP, the position at place
It can only be the 0th, 2,4,6 LUT positions to put, that is, LUT [0], LUT [2], LUT [4], LUT [6].Such as Fig. 3 b
Shown in local storage LRAM128 provided in an embodiment of the present invention × 1SP esource impact schematic diagrames, after line module mapping
Take the 0th, 2 LUT positions；If Fig. 3 c are local storage LRAM256 × 1SP resources provided in an embodiment of the present invention
Shown in mapping schematic diagram, line module carries out taking the 0th, 2,4,6 LUT positions after logical resource mapping.
Fig. 5 is the layout method schematic flow sheet of another local storage provided in an embodiment of the present invention.As shown in figure 5,
A kind of layout method of local storage includes step S501-S509：
Step S501：All modules of traverse user design, find and store different types of local storage；
The module used that user designs is done and only done and is once accessed, find the different local storage of memory capacity, and will
They are stored in the chips.Using the storage size of memory as the standard of classification, different types of local storage includes：
LRAM64 × 1SP, LRAM128 × 1SP, LRAM128 × 2SP, LRAM256 × 1SP etc., it is numerous to list herein,
Only LRAM64 × 1SP, LRAM128 × 1SP, LRAM256 × 1SP are illustrated in the embodiment of the present invention, this
Known to art personnel, it not delimit the scope of the invention.
Step S502：Carry out client layer module is tied to chip-scale constraint 1 respectively to different types of local storage
N is mapped, and the mapped chip logic resource is marked；
Specifically, mark is mapped chip logic resource；Chip has in itself logical resource, and mark is to discriminate between chip
The logical resource of itself and mapped chip logic resource.
Esource impact includes two steps：One is that local storage LRAM is mapped on look-up table LUT；Two is by quilt
The LUT that LRAM is used is marked.
Each local storage is carried out into the mapping that client layer module is tied to 1 couple of n of chip-scale constraint.
Step S503：The coordinate position of the line module is mapped on the logical resource of the chip, and to the use
Family is marked on module coordinate position using actual example, and other expanded positions are marked using actual situation example；
In electronic circuitry design, synthesis tool according to user design input hardware description language (Verilog or
VHDL), user's design is converted to into netlist (netlist), component annexation each other is described using netlist.
User's netlist includes each of each logical block, all of the port of each logical block and each logical block of user's design
The link information of individual port.
According to the annexation between each elementary cell that LE is constituted in user's netlist, object function is set up；According to the mesh
Scalar functions, calculate coordinate value of each elementary cell of each LE in fpga chip layout.Thus the first coordinate position is obtained
With the second coordinate position.
In logical block LE after each mapping, user coordinates is marked on position using actual example, other expansion
N-1 positions are marked using actual situation example.
Step S504：In same coordinate position in single logical block, to shared by the labeled chip logic resource
The first coordinate detected with the second coordinate shared by not labeled chip logic resource；
In same coordinate position in single logical block, specifically, in the logic chip LP of chip logic unit LE,
The position of some LUT is by shared by labeled chip logic resource or has shared by not labeled chip logic resource；
It is detected.
Have 8 LUT inside one LE, that is, have 8 position coordinateses, be followed successively by the 0th from top to bottom, 1,2,3,
4th, 5,6,7 position.The first coordinate on coordinate position and the second coordinate when being detected, after only detection maps；Example
Such as：In mapping once, the 4th position is non-mapped, then avoid the need for detecting the position.Due to the 0th, 2,
4th, 6 positions are that LRAM carries out the position to be accounted for after chip logic esource impact, thus the 1st, 3,5,7 positions not yet
Needs are detected.
Step S505:Whether first coordinate is same coordinate with second coordinate；
Judge whether coordinate position is occupied, for example：6th position of one LE, by shared by the logical resource not being labeled,
Namely the second coordinate；If labeled logical resource is not mapped into the coordinate, that is, without first on the 6th position
Coordinate, then the first coordinate is differed with the second coordinate.
Again for example：6th position of one LE, without the second coordinate；If labeled logical resource is mapped to the position,
So the first coordinate is differed with the second coordinate.
When the first coordinate and the second coordinate are same coordinate, it is meant that the overlap of logical resource occur, therefore account for after removing
With the coordinate of the position.It should be noted that：Coordinate position is by labeled logical resource or by the logic money not being labeled
Source takes, in no particular order；The logical resource for first taking, just first uses the position.
Step S506：Not labeled chip logic resource is removed to another coordinate；
When coordinate position is first taken by labeled chip logic resource, then need to remove not labeled chip logic resource
To another coordinate.Another coordinate is both adjacent LE of possibly mapped logical block in other logical blocks LE,
It is also likely to be non-conterminous LE.When moving in another coordinate, step S504 is returned to, carry out detecting the mistake with conflict analysis
Journey, till conflict is not present.
In partial layout optimization, for the adjustment of logical block, typically carry out in certain scope.Such as,
In a specific example, the adjustment of logical block, be with three same type logic lists being adjusted around logical block
On the position of unit, a new position is found, controlled logical block is moved to into new position.When at adjacent three
When can not find suitable position on the position of same type logical block, can again expanded scope to four adjacent logical blocks.
Step S507:Fixed not labeled chip logic resource；
When coordinate position by labeled chip logic resource first not taken, that is, the first coordinate and the second coordinate not phase
Together, then fixed not labeled chip logic resource.
Step S508：Labeled chip logic resource is removed to another coordinate；
When coordinate position is first taken by the chip logic resource not being labeled, then need to remove not labeled chip logic money
Source is to another coordinate.
In a specific embodiment, Fig. 4 is local storage LRAM256 provided in an embodiment of the present invention × 1SP moneys
Source maps conflict graph schematic diagram.As shown in figure 4, mapping after be located at LUT in the 0th, 2,4,6 coordinate positions, but
The 2nd, 6 coordinate positions are first taken by unlabelled chip logic resource in LUT, produce conflict.So will be mobile labeled
Chip logic resource to the 0th, 2 coordinate positions in neighbouring LUT.
Other processes are identical with step S506, will not be described here.
Step S509：Fixed labeled chip logic resource.
First taken by the chip logic resource not being labeled when coordinate position is no, that is, the first coordinate and the second coordinate are not
It is identical, then fixed labeled chip logic resource.
The present invention to different types of local storage by carrying out esource impact so that is unified in chip logic resource
Mixed layout, the layout optimization under mixed constraints can be carried out to different types of local storage, so as to avoid layout from rushing
It is prominent, while saving chip logic resource.
Professional should further appreciate that, with reference to the list of each example of the embodiments described herein description
Unit and algorithm steps, can with electronic hardware, computer software or the two be implemented in combination in, it is hard in order to clearly demonstrate
The interchangeability of part and software, according to function has generally described the composition and step of each example in the above description.
These functions are performed with hardware or software mode actually, depending on the application-specific and design constraint of technical scheme.
Professional and technical personnel can use different methods to realize described function to each specific application, but this realization
It is not considered that beyond the scope of this invention.
With reference to the method for the embodiments described herein description or the step of algorithm can with hardware, computing device it is soft
Part module, or the combination of the two is implementing.Software module can be placed in random access memory (RAM), internal memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM,
Or in technical field in known any other form of storage medium.
Above-described specific embodiment, has been carried out further in detail to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail it is bright, should be understood that the foregoing is only the present invention specific embodiment, be not intended to limit the present invention
Protection domain, all any modification, equivalent substitution and improvements within the spirit and principles in the present invention, done etc. all should
It is included within protection scope of the present invention.
Claims (9)
1. a kind of local storage layout method, it is characterised in that methods described includes：
The mapping of chip logic resource is carried out to the local storage that user is designed in module；
Carry out the constraint detection and conflict analysis of logical resource after the mapping.
2. method according to claim 1, it is characterised in that in the local storage designed user in module
Before carrying out the mapping step of chip logic resource, all modules of traverse user design find and store different types of
Ground memory.
3. method according to claim 1, it is characterised in that described local storage in module is designed to user to enter
The mapping step of row chip logic resource includes：
Carry out 1 couple of n mappings that client layer module is tied to chip-scale constraint respectively to different types of local storage,
And the mapped chip logic resource is marked.
4. method according to claim 3, it is characterised in that the coordinate position of the line module is mapped to described
On the logical resource of chip, and to being marked using actual example on the line module coordinate position, other launch n-1
It is marked using actual situation example on position.
5. method according to claim 1, it is characterised in that the constraint inspection for carrying out logical resource after the mapping
Surveying step includes：
In same coordinate position in single logical block, to be labeled the chip logic resource shared by the first coordinate with
The second coordinate shared by labeled chip logic resource is not detected.
6. method according to claim 5, it is characterised in that the conflict analysis step includes：
Whether first coordinate is same coordinate with second coordinate, if coordinate is identical, then conflict is present；If coordinate
Differ, then there is no conflict.
7. method according to claim 6, it is characterised in that the position of the same coordinate is the labeled core
Piece logical resource first takes：
If there is conflict, the not labeled chip logic resource is just removed to another coordinate, and be not labeled to described
Logical resource carries out the process of duplicate detection and conflict analysis, till conflict is not present；
If there is no conflict, the chip logic resource not just being labeled described in fixation.
8. method according to claim 6, it is characterised in that the same coordinate is that the not labeled chip is patrolled
Collect resource first to take：
If there is conflict, the labeled chip logic resource is just removed to another coordinate, and to the labeled chip
Logical resource carries out the process of duplicate detection and conflict analysis, till conflict is not present；
If there is no conflict, with regard to the fixation labeled chip logic resource.
9. according to the method for claim 7 or 8, it is characterised in that another coordinate is in other logical blocks on chip
Coordinate position.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112948324A (en) * | 2021-04-16 | 2021-06-11 | 山东高云半导体科技有限公司 | Memory mapping processing method and device and FPGA chip |
| CN113111481A (en) * | 2021-02-28 | 2021-07-13 | 新华三半导体技术有限公司 | Design constraint checking method and device |
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| CN106649899B (en) | 2023-04-18 |
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