CN106643815B - Method and system for decoding signal of induction synchronizer - Google Patents
Method and system for decoding signal of induction synchronizer Download PDFInfo
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Abstract
The invention provides a method and a system for decoding an induction synchronizer signal, wherein the method comprises the following steps: a coupling step, a signal amplifying step, a lock-in amplifying step and a decoding step. The system comprises a digital control circuit, a digital control circuit and a digital control circuit, wherein the digital control circuit is used for outputting an excitation signal so that a sine and cosine winding of an induction synchronizer generates a sine and cosine signal carrying position information under the coupling of the excitation signal; the precise amplifying circuit is used for amplifying the amplitude of the sine and cosine signals carrying the position information output by the induction synchronizer to a volt level; the phase-locked amplifier is connected with the precise amplifying circuit and is used for extracting signals with the same frequency as the excitation signals from the sine and cosine signals amplified by the signal amplifying circuit and filtering other useless signals except the excitation frequencies; the digital control circuit is also connected with the phase-locked amplifier and used for decoding the signal output by the phase-locked amplifier to obtain the position information. The invention has lower cost and higher flexibility, and the filtering of the phase-locked amplifier can ensure the decoding precision.
Description
Technical Field
The present invention relates to the field of signal processing technologies, and in particular, to a method and a system for decoding a signal of an induction synchronizer.
Background
In the fields of military, industry, daily life, aerospace and the like, the application of an induction synchronizer is becoming more and more important, and the induction synchronizer is a displacement sensor for converting an angle or linear displacement signal into alternating voltage, which is also called a planar rotary transformer. In principle, it is not substantially different from a rotary transformer (abbreviated as a resolver), but is different from a resolver in that its stator and rotor are not windings mounted in cylindrical and cylindrical core slots, but are similar to a "printed winding" of a printed circuit board, and such a "winding" has greatly reduced moment of inertia and mass compared with a resolver winding, and thus is widely used in high-precision servo turntable, radar antenna, positioning tracking of artillery and radio telescope, precision numerical control machine tool, and high-precision position detection system.
However, reducing the mass and inertia brings about another problem that the output signal of the induction synchronizer, i.e., the sine and cosine signal carrying the position information, is only in millivolt (mV) level, so that the difficulty of decoding is increased relative to the resolver, especially in the use cases where a high-precision position signal is required.
Disclosure of Invention
The invention aims to provide a method and a system for decoding an induction synchronizer signal, which are used for solving the problem of high decoding difficulty.
In order to solve the problems, the invention provides the following technical scheme:
a method of decoding an inductive synchronizer signal, comprising the steps of: a coupling step, namely enabling the sine and cosine windings of the induction synchronizer to generate sine and cosine signals carrying position information under the coupling of an excitation signal; a signal amplifying step of amplifying the amplitude of the sine and cosine signals carrying the position information obtained in the coupling step to a volt level; a phase-locked amplifying step, namely correspondingly extracting a signal sine and cosine amplitude signal with the same frequency as the exciting signal from the sine and cosine signal amplified by the signal amplifying step, and filtering useless signals except the exciting frequency; and a decoding step, calculating a position signal carrying position information according to the obtained sine and cosine amplitude signals.
In the induction synchronizer signal decoding method as described above, preferably, in the coupling step, the excitation signal U m Satisfies the formula (1), the formula (1) is: u (U) m =a' ·sin ωt, where ω represents the angular frequency of the excitation signal; sine and cosine signals U output by induction synchronizer sin 、U cos Satisfies the formula (2), the formula (2) is:wherein U is sin 、U cos Alpha in (a) is a position angle signal used for representing position information; in the signal amplifying step, the sine and cosine signals obtained after amplification satisfy the formula (3), and the formula (3) is: />Wherein the position angle α is assumed to be invariant.
In the above-described method for decoding an induction synchronizer signal, it is preferable that the filter circuit for filtering out unwanted signals other than the excitation frequency in the lock-in amplifying step is a low-pass filter circuit.
In the method for decoding an induction synchronizer signal as described above, it is preferable that in the phase-locked amplifying step, the sinusoidal signal to be detected is set as x 1 (t)＝V A sin (ωt+a), the cosine signal to be measured is x 2 (t)＝V' A sin (ωt+a), noise n (t), first reference signal y 1 (t) =b·sin (ωt+b), the second reference signal is y 2 (t) =b·sin (ωt+b-90 °); the amplitude B is a known quantity, and a and B respectively represent initial phases of a sinusoidal signal to be detected and a first reference signal; the sinusoidal signal to be detected is multiplied with the first reference signal and the second reference signal respectively to obtain a first multiplication operation result and a second multiplication operation result, wherein the first multiplication operation result satisfies the formula (4), and the formula (4) is:
the second multiplication result satisfies the formula (5), wherein the formula (5) is：
And respectively carrying out filtering treatment on the first multiplication operation result and the second multiplication operation result to correspondingly obtain:
multiplying the cosine signal to be detected with the first reference signal and the second reference signal respectively to obtain a third multiplication operation result and a fourth multiplication operation result, wherein the third multiplication operation result satisfies the formula (6), and the formula (6) is as follows:
the fourth multiplication result satisfies the formula (7), where the formula (7) is:
and respectively carrying out filtering treatment on the third multiplication operation result and the fourth multiplication operation result to correspondingly obtain:
for v 1 (t) and v 2 And (t) square sum, and opening root number to obtain a result which satisfies a formula (8), wherein the formula (8) is as follows: />For v 3 (t) and v 4 And (t) square sum, and opening root number to obtain a result which satisfies a formula (9), wherein the formula (9) is as follows:
in the induction synchronizer signal decoding method as described above, preferably, in the decoding step, the signal is sampled by ADObtaining the signal v after the phase-locked amplifying step 12 、v 34 For v 12 And v 34 The result obtained by performing the division processing satisfies the formula (10), and the formula (10) is: tan α=v 12 /v 34 And (3) carrying out arctangent operation on tan alpha to obtain alpha.
An inductive synchronizer signal decoding system, comprising: the digital control circuit, the precise amplifying circuit and the phase-locked amplifier; the digital control circuit is used for outputting excitation signals so that sine and cosine windings of the induction synchronizer generate sine and cosine signals carrying position information under the coupling of the excitation signals; the precise amplifying circuit is used for amplifying the amplitude of the sine and cosine signals carrying the position information output by the induction synchronizer to a volt level; the phase-locked amplifier is connected with the precise amplifying circuit and is used for correspondingly extracting sine and cosine amplitude signals of signals with the same frequency as the excitation signals from the sine and cosine signals amplified by the signal amplifying circuit and filtering other useless signals except the excitation frequency; the digital control circuit is also connected with the phase-locked amplifier and used for decoding sine and cosine amplitude signals output by the phase-locked amplifier to obtain position information.
In the induction synchronizer signal decoding system as described above, preferably, the precision amplifying circuit includes: the low-pass filter circuit is connected with the induction synchronizer and is an RC filter circuit; and the amplifying circuit is connected with the RC filter circuit.
In the induction synchronizer signal decoding system as described above, preferably, the lock-in amplifier is a quadrature-type lock-in amplifier.
In the induction synchronizer signal decoding system as described above, preferably, the digital control circuit is a digital signal processing chip.
Analysis shows that the invention provides a high-precision resolving scheme for carrying out corresponding signal processing by taking a DSP as a control main control unit and combining a precise operational amplifier circuit and a phase-locked amplifier. Compared with the common scheme of hardware decoding after direct signal amplification, the invention has lower cost and higher flexibility, and the filtering of the phase-locked amplifier can ensure the decoding precision.
Drawings
FIG. 1 is a general block diagram of an embodiment of the present invention;
FIG. 2 is a schematic diagram of a signal amplifying process according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a phase-locked amplifying process according to an embodiment of the present invention;
FIG. 4 is a signal processing flow chart of a lock-in amplifier according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a sinusoidal lock-in amplifier according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a quadrature lock-in amplifier according to an embodiment of the present invention;
FIG. 7 is a decoding schematic diagram of an embodiment of the present invention;
FIG. 8 is a schematic diagram of an excitation signal generation circuit according to an embodiment of the present invention;
FIG. 9 is a high precision amplifying circuit according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a signal generating circuit according to an embodiment of the invention;
fig. 11 is a lock-in amplifier according to an embodiment of the invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
In the principles of the present invention, the operation of decoding an inductive synchronizer can be divided into three steps: a signal amplifying step, a lock-in amplifying step and a decoding step. And respectively amplifying, filtering and decoding according to the characteristic of weak output signals of the induction synchronizer. Particularly in the filtering link, the characteristic that the phase-locked amplifier can extract weak signals with specific frequency from noise is utilized to effectively filter signals to be detected, and the problem caused by the phase can be avoided by the application of the orthogonal phase-locked amplifier.
Based on this, as shown in fig. 1, in the system provided by the present invention, the hardware components mainly include three modules: digital control circuit, precision amplifying circuit, lock-in amplifier. In the digital control circuit, a DSP (Digital Signal Processing, digital signal processor) is used as a main regulation unit, such as a digital chip with the model TMS320X2812, which comprises a minimum system composed of components such as a crystal oscillator and the like, and clock signals with the voltages of 3.3V and 1.8V and a certain frequency for enabling the TMS320X2812 to work are provided. The level conversion circuit 74ACT245 converts the PWM waveform with the amplitude of 3.3V output by the DSP into a PWM waveform signal with the amplitude of 5V, and improves the driving capability of the chip. The high-precision external sampling chip ADS7864 of the sampling module can be used for taking external analog signals in real time, converting the external analog signals into digital signals and transmitting the digital signals to the DSP for processing through a data bus. The simulated programming port circuit JTAG can realize the programming and online program simulation of the chip and improve the development capability. And the OSC-15801 excitation chip is used as an excitation module, a circuit connection schematic of the OSC-15801 excitation chip is shown in fig. 8, and a pin PAOUT is a pin for outputting an excitation signal.
The precision amplifying circuit includes: the RC filter circuit and the amplifying circuit are composed of an instrument amplifier AD625 with high precision and high common mode rejection ratio and peripheral circuits thereof. The circuit connection diagram of the amplifier AD625 is shown in fig. 9, in which the signal to be amplified is a sinusoidal signal to be detected, the pin Vout is the pin from which the amplified sinusoidal signal sin_out is output,
the lock-in amplifier includes: the chip AD9850 is a signal generating chip designed according to the principle of direct digital frequency synthesis, and is based on a direct frequency synthesizer, which applies advanced CMOS technology and can be controlled by using DSP pins. The schematic circuit connection of the signal generator chip AD9850 is shown in fig. 10, in which LPF is a low-pass filter circuit. The chip AD630 internally comprises two operational amplifiers A and B, a change-over switch, a comparator COMP (comprising a triode T), an output integrating amplifier, an on-chip compensation capacitor and an on-chip resistor. The AD630 is used as a phase sensitive detector, namely a multiplier, to complete the design of a related detection circuit when the phase-locked amplifier is designed.
It will be appreciated by persons skilled in the art that while the above description relates to a chip type, the invention is not so limited.
As shown in fig. 1, the digital control circuit outputs a high frequency sinusoidal excitation signal, preferably at a frequency of 10kHz, through its excitation module. The amplitude of the sinusoidal excitation signal may be 10V. Under the coupling of excitation signals, the sine and cosine windings of the induction synchronizer can generate sine and cosine signals carrying position information:
excitation signal: u (U) m ＝A′·sinωt (1)
Wherein ω represents the angular frequency of the excitation signal;
sensing synchronizer output signal:
wherein U is sin 、U cos Alpha in (a) is a position angle signal for representing position information, but due to U sin 、U cos The signal is only in mV-level and is particularly prone to noise interference, so that special processing is required, i.e. the following processing steps are provided.
(one) a first portion: signal amplification
The signal amplification process, shown in fig. 2, has the effect of increasing the amplitude of the sine and cosine output signal (from mV to V) while keeping the signal as undisturbed as possible, but the main purpose of the amplification. The signal method steps can be processed by a precision amplifying circuit, a low-pass filter circuit of the precision amplifying circuit only needs to use an RC filter circuit, an amplifier circuit of the precision amplifying circuit (or called a pre-amplifying circuit) uses an instrument amplifier AD625 with high precision and high common mode rejection ratio, a peripheral circuit of the instrument amplifier AD is designed, and a high-precision configuration resistor is selected, so that the amplification factor can be conveniently and flexibly selected.
The amplified signal is:
since the position angle α is relatively very slow compared to the variation of the excitation frequency (10 kHz), the signal processing can be assumed to be invariant, and thus the amplified signal can be expressed as:
wherein V is A Is a sine amplitude signal, V A ' is a cosine amplitude signal.
(II) a second part: phase-locked amplification
In the field of weak signal detection, compared with accompanying noise, the signal amplitude is generally very small, even in the order of mu V to nV, and the weak signal is difficult to accurately extract by a common means, so that the signal needs to be subjected to filtering processing. Most of the detection methods in the prior art use a band-pass filter as a filtering means, but the method has the defects of narrow bandwidth design, high design requirements and easiness in influence of temperature and voltage. Therefore, in the implementation of the invention, the sine and cosine amplitude signals of the signals (namely useful signals) with the same frequency as the excitation signals are correspondingly extracted from the sine and cosine signals amplified in the signal amplifying step by adopting the lock-in amplifier, and useless signals except the excitation frequencies are filtered out, and the invention is specifically obtained by carrying out lock-in amplification and filtering on the signals. The process of lock-in amplification is shown in fig. 3. The phase-locked amplifier is designed based on the cross-correlation detection principle, the core of the phase-locked amplifier is phase-sensitive detection, and the related principle is not repeated. The signal processing of the lock-in amplifier is shown in fig. 4, and a reference signal is required, and the reference signal must have the same frequency as the sine and cosine signal to be processed (for example, 10kHz, which can be sinusoidal or square wave, and here, sine is taken as an example.
Fig. 5 shows a processing procedure of a sine signal (the decoding signal is a sine and cosine signal), here, taking a sine signal as an example, a cosine signal, and so on. The phase-sensitive detector adopted by the actual circuit is AD630, the signal generator is AD9850, the low-pass filter is an RC filter circuit, namely the phase-locked amplifier comprises: a phase sensitive detector, a signal generator and a low pass filter.
The phase sensitive detector is used for completing multiplication operation of an input signal and a reference signal, and obtaining sum frequency signals and difference frequency signals of the input signal and the reference signal after operation processing. The purpose of the low-pass filter is to filter out high frequency components in the signal, which narrows the frequency band, thus achieving the purpose of extracting weak signals in noise.
Let the sine signal to be measured be x 1 (t)＝V A sin (ωt+a), the noise is n (t), the first reference signal is y 1 (t) =b·sin (ωt+b), the second reference signal y 2 (t) =b·sin (ωt+b-90 °), wherein the amplitude B is known, and a and B represent initial phases of the sinusoidal signal to be measured and the first reference signal, respectively. In the phase-sensitive detection link, the sine signal to be detected and the first reference signal are multiplied, and the result is as follows:
the first term in the formula (5) is a direct current signal, and the value of the direct current signal is proportional to the amplitude value of the two signals and the cosine of the phase difference; the second term is the frequency multiplication signal of the measured signal. The noise and the measured signal are input to the multiplier at the same time and also participate in the multiplication of the reference signal. In the analysis of the results, it can be seen that n (t) Bsin (ωt+b) is almost entirely an alternating signal. The channel of the low-pass filter can be narrow, when the low-pass filter is used for filtering the product signal of the double frequency signal of the target signal, noise and the reference signal, only the direct current signal passes, namelyAs long as the initial phases a and B of the two signals are known, cos (a-B) is determined and there is a determined amplitude B, the amplitude V of the signal to be measured A Are readily available.
However, in general, it is difficult to make cos (a-b) constant and not easily available in a single channel. In order to avoid the influence caused by the detection, the reference signal is shifted by 90 degrees and used as the reference signal of the other path (namely, the second reference signal), so that the quadrature phase-locked amplifier can dynamically complete the detection of the signal and calculate the amplitude and the phase of the signal. Fig. 6 is a schematic diagram of a quadrature phase lock amplifier. The result of the multiplication operation of the sine signal to be detected and the other reference signal is as follows:
the structure of the quadrature phase-locked amplifier has certain symmetry and is composed of two signal channels and correlators. The two signal channels are identical, the signal channels output two paths of identical signals, the reference channel outputs two paths of sine signals with the same frequency, the phase difference is 90 degrees, and the two signals are respectively input into two correlators (AD 630) for operation. The two correlator outputs are respectively:
v 1 (t)＝0.5V A B cos(a-b)
v 2 (t)＝0.5V A B sin(a-b)
the square sum is obtained by the two formulas, and the root number processing (the processing process can be specifically processed by a vector/phase DSP) is obtained:
i.e. < ->
From formula (8), v 12 Can be calculated by sampling and v 12 The signal to be measured amplitude V A And information of the reference signal amplitude B, because B is known, the signal amplitude to be measured can be obtained; namely, the phase-locked amplifier can well detect the amplitude value V of the signal to be detected A Weak signals were successfully detected.
Namely: v (V) A ＝A·sinα
In other words, the sinusoidal amplitude signal of the same frequency as the excitation signal is extracted from the sinusoidal signal amplified by the signal amplifying step.
Let the cosine signal to be measured be x 2 (t)＝V' A sin (ωt+a), the process of processing the cosine signal to be detected is detailed in the processing process of the sine signal:
the cosine signal to be detected is multiplied by the first reference signal and the second reference signal respectively to obtain a third multiplication result and a fourth multiplication result, wherein the third multiplication result is as follows:
the fourth multiplication result is as follows:
filtering by a low-pass filter to obtain the following components:
v 3 (t)＝0.5V' A Bcos(a-b)
v 4 (t)＝0.5V' A Bsin(a-b)
the square sum is obtained by the two formulas, and the root number processing (the processing process can be specifically processed by a vector/phase DSP) is obtained:
i.e. < ->
V A '＝A·cosα
In other words, the cosine amplitude signal of the same frequency as the excitation signal is extracted from the cosine signal amplified in the signal amplifying step.
In application, the phase difference between a and b is fixed by the formula (8), the purpose of locking the phase is achieved, and the initial phase of the reference signal is known, so that the phase of the signal to be detected can be obtained.
(III) third section: decoding
The final decoding is completed by the digital control circuit, as shown in fig. 7, and the signal after the frequency selection processing of the lock-in amplifier is obtained through AD sampling, namely:
obviously, the tan alpha is obtained by dividing the two signals, and the value of the position angle alpha can be obtained by a table look-up method.
In summary, the decoding process of the present invention can be divided into three main parts: signal amplification, lock-in amplification, and decoding. The first partial signal is amplified to amplify the sine and cosine signals carrying position information in the order of millivolts to the order of volts, requiring that distortion of the signals be minimized during the amplification process. And the second part of phase-locked amplification, wherein the phase-locked amplifier is used for extracting signals with the same frequency as the excitation signals, namely useful signals, from the amplified sine and cosine signals and filtering other useless signals except the excitation frequencies, and the function of the phase-locked amplifier is equivalent to a special filter. And the third part is used for calculating a position signal through software built in the digital control circuit according to the sine and cosine amplitude signals obtained after the previous two steps of processing. Tests show that the invention has lower cost and higher flexibility, and the filtering of the phase-locked amplifier can ensure the decoding precision.
It will be appreciated by those skilled in the art that the present invention can be carried out in other embodiments without departing from the spirit or essential characteristics thereof. Accordingly, the above disclosed embodiments are illustrative in all respects, and not exclusive. All changes that come within the scope of the invention or equivalents thereto are intended to be embraced therein.
Claims (2)
1. A method for decoding an inductive synchronizer signal, comprising the steps of:
a coupling step, namely enabling the sine and cosine windings of the induction synchronizer to generate sine and cosine signals carrying position information under the coupling of an excitation signal;
in the coupling step, the excitation signal U m Satisfies the formula (1), the formula (1) is:
U m ＝A′·sinωt
wherein ω represents the angular frequency of the excitation signal;
inductionSine and cosine signals U output by synchronizer sin 、U cos Satisfies the formula (2), the formula (2) is:
wherein U is sin 、U cos Alpha in (a) is a position angle signal used for representing position information;
in the signal amplifying step, the sine and cosine signals obtained after amplification satisfy the formula (3), and the formula (3) is:
wherein the position angle α is assumed to be invariant;
a signal amplifying step of amplifying the amplitude of the sine and cosine signals carrying the position information obtained in the coupling step to a volt level;
in the phase-locked amplifying step, let the sine signal to be measured be x 1 (t)＝V A sin (ωt+a), the cosine signal to be measured is x 2 (t)＝V' A sin (ωt+a), noise n (t), first reference signal y 1 (t) =b·sin (ωt+b), the second reference signal is y 2 (t) =b·sin (ωt+b-90 °); the amplitude B is a known quantity, and a and B respectively represent initial phases of a sinusoidal signal to be detected and a first reference signal;
and (3) multiplying the sinusoidal signal to be detected with the first reference signal and the second reference signal respectively to obtain a first multiplication result and a second multiplication result, wherein the first multiplication result satisfies the formula (4), and the formula (4) is as follows:
the second multiplication result satisfies the formula (5), and the formula (5) is:
and respectively carrying out filtering treatment on the first multiplication operation result and the second multiplication operation result to correspondingly obtain:
v 1 (t)＝0.5V A Bcos(a-b)
v 2 (t)＝0.5V A Bsin(a-b)
multiplying the cosine signal to be detected with the first reference signal and the second reference signal respectively to obtain a third multiplication result and a fourth multiplication result, wherein the third multiplication result satisfies the formula (6), and the formula (6) is:
the fourth multiplication result satisfies the formula (7), where the formula (7) is:
and respectively carrying out filtering treatment on the third multiplication operation result and the fourth multiplication operation result to correspondingly obtain:
v 3 (t)＝0.5V' A Bcos(a-b)
v 4 (t)＝0.5V' A Bsin(a-b)
for v 1 (t) and v 2 And (t) square sum, and opening root number to obtain a result which satisfies a formula (8), wherein the formula (8) is as follows:
for v 3 (t) and v 4 And (t) square sum, and opening root number to obtain a result which satisfies a formula (9), wherein the formula (9) is as follows:
a phase-locked amplifying step, namely correspondingly extracting sine and cosine amplitude signals of signals with the same frequency as the excitation signals from the sine and cosine signals amplified by the signal amplifying step, and filtering useless signals except the excitation frequency;
a decoding step, namely calculating a position signal carrying position information according to the obtained sine and cosine amplitude signals;
in the decoding step, the decoding step is performed,
obtaining a signal v after phase-locked amplification step processing through AD sampling 12 、v 34 For v 12 And v 34 The result obtained by performing the division processing satisfies the formula (10), and the formula (10) is:
tanα＝v 12 /v 34
and (3) carrying out arctangent operation on tan alpha to obtain alpha.
2. The method of claim 1, wherein the filter circuit for filtering unwanted signals other than the excitation frequency in the phase-locked amplifying step is a low-pass filter circuit.
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