CN106611759A - 集成电力封装 - Google Patents

集成电力封装 Download PDF

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Publication number
CN106611759A
CN106611759A CN201610941441.0A CN201610941441A CN106611759A CN 106611759 A CN106611759 A CN 106611759A CN 201610941441 A CN201610941441 A CN 201610941441A CN 106611759 A CN106611759 A CN 106611759A
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conductor
transistor
dielectric medium
medium structure
coupled
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CN106611759B (zh
Inventor
马修·大卫·罗米格
克里斯托弗·丹尼尔·马纳克
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

本申请案涉及一种集成电力封装。集成电力封装包含具有第一表面的衬底及定位在所述衬底内的集成电路。至少一个电导体定位在所述第一表面与所述衬底上的另一点之间。至少一个晶体管电且机械耦合到所述至少一个第一导体。支撑结构电且机械耦合到所述至少一个晶体管，其中所述至少一个晶体管定位在所述衬底的所述第一表面与所述支撑结构之间。

Description

集成电力封装
技术领域
本申请案涉及集成电力封装。
背景技术
集成电力封装传导高电流且需要在小占据面积中的良好的热性能以便被放置在小电子装置中。许多集成电力封装缺乏将集成电路(IC)放置在与高电流晶体管(例如MOSFET)的垂直堆叠中的能力，这是因为此类放置使热性能降级。
许多常规集成电力封装不具有在封装之上的暴露的金属，这降低了MOSFET及控制器的热性能。此外，常规封装使用相同过程步骤以使控制器与MOSFET互连，这导致降级的电性能。
发明内容
一种集成电力封装包含具有第一表面的衬底及定位在所述衬底内的集成电路。至少一个电导体定位在所述第一表面与所述衬底上的另一点之间。至少一个晶体管电且机械耦合到所述至少一个第一导体。支撑结构电且机械耦合到所述至少一个晶体管，其中所述至少一个晶体管定位在所述衬底的所述第一表面与所述支撑结构之间。
附图说明
图1是高电流电路的示意图。
图2是用于图1电路的集成电力封装的实例的侧面剖视图。
图3是图2的集成电力封装的衬底的俯视平面图。
图4是图2的集成电力封装的俯视平面图。
图5是描述用于图2的集成电力封装的实例制造方法的流程图。
具体实施方式
本文揭示实现高电力晶体管接近可控制所述晶体管的操作的集成电路的放置的装置，其中晶体管并排定位。图1是高电流电路100的示意图，其中电流I流过第一FET Q1及第二FET Q2。尽管本文描述FET，但电路100可用其它类型的晶体管替代FET。电流I在第一电压V1与第二电压V2之间流动。定位在第一FET Q1与第二FET Q2之间的节点N1具有电压V3。第一及第二FET Q1及Q2的栅极耦合到IC控制器106，IC控制器106控制栅极电压及流过第一及第二FET Q1及Q2的电流。流过第一及第二FET Q1及Q2的电流I产生可干扰IC控制器106的操作的热量。此外，电流I可能太高以至于无法通过IC控制器106。因此，第一及第二FET Q1及Q2通常定位在IC控制器106外部。本文所描述的电路及结构使IC控制器106能够接近第一及第二FET Q1及Q2定位在提供散热的集成电力封装中。参考图1描述的晶体管为示范性的且可应用其它配置，例如不同的P沟道及N沟道装置。
图2是用于图1电路100的集成电力封装200的实例的侧面剖视图，且图3是封装200的俯视平面图。封装200包含电介质结构202，其中IC控制器106附接到电介质结构202。电介质结构202包含在下文描述的多个导体。在图2的实例中，IC控制器106定位在电介质结构202内，但在其它实例中，IC控制器106附接到电介质结构202的其它部分或表面。在其它实例中，IC控制器106定位在电介质结构202内的其它位置中。电介质结构202由大体上电绝缘的材料(例如通常用于IC封装的制造中的电介质材料)制成。电介质材料包含基于聚合物的材料。
电介质结构202包含顶表面204(其有时被称为第一表面)及底表面206(其有时被称为第二表面)。另外，电介质结构202包含前表面208及后表面210。第一栅极垫214及第二栅极垫216定位在电介质结构202的顶表面204上。本文所描述的垫经说明为具有定位在其上的接合材料。第一栅极垫214充当用于第一FET Q1(图1)的栅极的导体，且第二栅极垫216充当用于第二FET Q2的栅极的导体。第一栅极垫214及第二栅极垫216可为将电子组件电且机械耦合到衬底及其它结构的焊垫。第一源极垫220及第二漏极垫222也定位在电介质结构202的顶表面204上。在IC封装200的配置中，第一FET Q1源极向下放置在第一源极垫220上且第二FET Q2漏极向下放置在第二漏极垫222上。在其它实施例中，FET可具有相对于电介质结构202的其它配置。第一源极垫220及第二漏极垫222可为将电子组件电且机械连接到衬底的焊垫。第一源极垫220及第二漏极垫222可具有本文描述的热及电性质。
电介质结构202包含将垫电连接到外部接触件及IC控制器106的多个导体。图2及3中所展示的导体仅用于说明目的且其它导体配置可定位在电介质结构202内。第一栅极导体230将第一栅极垫214耦合到IC控制器106，且第二栅极导体232将第二栅极垫216耦合到IC控制器106。第一栅极导体230及第二栅极导体232传导第一及第二FET Q1及Q2与IC控制器106之间的栅极电流。因为第一及第二栅极导体230及232传导栅极电流，电流流动相对较低，所以第一及第二栅极导体230及232可相对较小。其它低电流导体(未图示)可定位在电介质结构202内以将外部连接器耦合到IC控制器106。
电介质结构202内的其它导体用以将电流I(图1中所展示)传导通过第一FET Q1及第二FET Q2。第一源极导体240在电介质结构202的外部的点与第一源极垫220之间传导电流。第二漏极导体242在电介质结构202的外部的点与第二漏极垫222之间传导电流。本文所描述的外部点经展示为处于电介质结构202的底表面206上；然而，外部点可定位在电介质结构202上的任何地方。导体240及242由低电阻材料制成且足够大以容纳电流I以便于最小化当电流I流过导体240及242时的损失。在一些实例中，电流I可在1.0到100Amp的范围中。在此类实施例中，导体240及242应小于10mΩ的电阻，且在一些实例中，电阻小于1.0mΩ。
第一FET Q1电且机械耦合到第一栅极垫214及第一源极垫220。更具体来说，第一FET Q1的栅极电且机械耦合到第一栅极垫214且源极电且机械耦合到第一源极垫220。第二FET Q2电且机械耦合到第二栅极垫216及第二漏极垫222。更具体来说，第二FET Q2的栅极电且机械耦合到第二栅极垫216且漏极电且机械耦合到第二漏极垫222。在一些实例中，将FET Q1及Q2接合到其相应垫的材料具有大于五瓦每米开尔文(W/mK)的热导率及小于500微欧姆厘米(uΩCm)的电阻率且具有介于10微米与100微米之间的厚度。
另外参考图4，导体250电且机械耦合到第一FET Q1及第二FET Q2两者。导体250有时被称为“支撑结构”。在图2的实施例中，导体250具有水平部分252及垂直部分254。由于电流I流过水平部分252，因此水平部分252的材料使得其能够容纳电流I且电且机械耦合到FET Q1及Q2两者。举例来说，导体250可由铜或类似材料制成且可具有0.025mm到0.5mm之间的厚度。水平部分252具有顶表面256(其有时被称为第一表面)及底表面258(其有时被称为第二表面)。底表面258具有将第一及第二FET Q1及Q2电且机械耦合到水平部分252的第一漏极垫260及第二源极垫262。水平部分252也可用于从封装200散热。举例来说，当从图4的俯视平面图观看时，水平部分252可比第一及第二FET Q1及Q2大0.5mm到5mm。因此，水平部分252可延伸超越第一及第二FET Q1及Q2的占据面积，这使热量能够从第一及第二FET Q1及Q2传递到水平部分252。热量接着可通过水平部分252传递远离封装200。选择支撑结构250的特定厚度、内容及尺寸以及电且机械互连件以便充分将由第一及第二FET Q1及Q2产生的热量传导掉。
在一些实例中，垂直部分254将导体250固定到电介质结构202且将电压V3耦合到电介质结构202。导体250的电势是图1的电压V3。在图2的实例中，电势通过导体268传导到电介质结构202的底表面206。在图1的电路100的一些实例中，由于电流I流过导体268，因此可以在损失最小的情况下容纳电流I的方式来制造导体268。将第一及第二FET Q1及Q2耦合到导体250的材料可与将第一及第二FET Q1及Q2耦合到垫220及222的材料相同或与其具有相同电及/或热特性。
如图4中所展示，导体250的水平部分252以覆盖FET Q1及Q2两者的方式延伸以便于提供有效的热传递且容纳电流I(图1)。举例来说，水平部分252可为传导热量的金属装置且其可暴露到封装200的外部。当使用封装202时，用于从水平部分252传递热量的散热器或其它装置或方法可最接近水平部分252放置。
封装200具有较之常规封装的许多优点。举例来说，封装200具有定位在IC控制器106之上的第一及第二FET Q1及Q2，这减小了封装200的尺寸。另外，封装200可使导体250的水平部分252暴露，这增强了封装200的热性能。
针对封装200的制造技术提供较之常规封装的进一步增强。电介质结构202与IC控制器106一起制造且导体定位在其中。第一FET Q1及第二FET Q2电且机械耦合到水平部分252的底表面258。在一些实例中，具有上文所描述的电及热性质的焊料或环氧树脂用于耦合FET Q1及Q2。接着，将导体250与FET Q1及Q2的组合放置到衬底202的顶表面204使得FETQ1及Q2接触其在电介质结构202的顶表面204上的适当垫。在其它实例中，FET Q1及Q2耦合到电介质结构202的顶表面204且导体250随后耦合到FET Q1及Q2及电介质结构202。
图5的流程图500描述制造封装200的实例。步骤502包含将集成电路定位在电介质结构内，其中电介质结构具有表面。步骤504包含将第一导体定位在所述表面与所述电介质结构上的另一点之间。步骤506包含将第二导体定位在所述表面与所述电介质结构上的另一点之间。步骤508包含将第一晶体管耦合到导电支撑结构。步骤510包含将第二晶体管耦合到所述支撑结构。步骤512包含将所述支撑结构、所述第一晶体管及所述第二晶体管的组合耦合到所述电介质结构，其中所述第一晶体管耦合到所述第一导体且所述第二晶体管耦合到所述第二导体。
本文已明确地详细描述集成电力封装及制造方法的某些实施例。所属领域的技术人员在阅读本发明之后将想到替代实施例。除了如由现有技术限制，权利要求书希望被广泛解释以涵盖所有此类替代实施例。

Claims (23)

1.一种集成电力封装，其包括：
电介质结构，其具有第一表面；
集成电路，其定位在所述电介质结构内；
至少一个导体，其定位在所述第一表面与所述电介质结构上的另一点之间；
至少一个晶体管，其电且机械耦合到所述至少一个第一导体；及
支撑结构，其电且机械耦合到所述至少一个晶体管，其中所述至少一个晶体管定位在所述电介质结构的所述第一表面与所述支撑结构之间。
2.根据权利要求1所述的封装，其中所述支撑结构具有介于0.025mm与0.5mm之间的厚度。
3.根据权利要求1所述的封装，其进一步包括将所述至少一个晶体管电且机械耦合到所述至少一个第一导体的材料，其中所述材料具有大于五瓦每米开尔文(W/mK)的热导率。
4.根据权利要求1所述的封装，其进一步包括将所述至少一个晶体管电且机械耦合到所述至少一个第一导体的材料，其中所述材料具有小于500微欧姆厘米(uΩCm)的电阻率。
5.根据权利要求1所述的封装，其中所述至少一个电导体包含定位在所述至少一个第一晶体管的栅极与所述集成电路之间的第一导体，及定位在所述电介质结构的外表面上的点与所述至少一个晶体管的漏极或源极中的一者之间的第二导体。
6.根据权利要求1所述的封装，其中所述至少一个晶体管的所述漏极或源极中的一者电且机械耦合到所述第一导体，且其中所述漏极或源极中的另一者电且机械耦合到所述支撑结构。
7.根据权利要求1所述的封装，其中所述电介质结构具有第二表面且其中所述第一导体在所述第一表面与所述第二表面之间延伸。
8.根据权利要求7所述的封装，其中所述第二表面相对于所述第一表面而定位。
9.根据权利要求1所述的封装，其中所述至少一个晶体管包含多个晶体管，所述多个晶体管中的每一者定位在所述电介质结构的所述第一表面与所述支撑结构之间。
10.根据权利要求9所述的封装，其中所述多个晶体管包含：
第一晶体管，其具有电且机械耦合到所述电介质结构的所述第一导体的源极及电且机械耦合到所述支撑结构的漏极；及
第二晶体管，其具有电且机械耦合到所述电介质结构的第二导体的漏极及电且机械耦合到所述支撑结构的源极。
11.根据权利要求10所述的封装，其中所述第二导体延伸到所述电介质结构的第二表面。
12.根据权利要求9所述的封装，其中所述支撑结构在所述多个晶体管之间传导电流。
13.根据权利要求1所述的封装，其中所述支撑结构的占据面积大于所述至少一个晶体管的占据面积。
14.根据权利要求1所述的封装，其中所述支撑结构的所述占据面积比所述至少一个晶体管的所述占据面积大至少0.5mm。
15.根据权利要求1所述的封装，其中所述支撑结构完全覆盖所述至少一个晶体管。
16.根据权利要求1所述的封装，其中所述支撑结构电耦合到延伸通过所述电介质结构的第二导体。
17.根据权利要求1所述的封装，其中所述支撑结构电且机械耦合到延伸通过衬底的第二导体。
18.根据权利要求1所述的封装，其进一步包括将所述支撑结构电且机械耦合到所述电介质结构的材料，所述材料具有大于5瓦每米开尔文(W/mK)的热导率及小于500微欧姆厘米(uOhmCm)的电阻率。
19.一种集成电力封装，其包括：
电介质结构，其具有第一表面；
集成电路，其定位在所述电介质结构内；
第一导体，其在所述第一表面与所述电介质结构上的另一点之间延伸；
第二导体，其在所述第一表面与所述电介质结构上的另一点之间延伸；
第三导体，其在所述第一表面与所述电介质结构上的另一点之间延伸；
第一晶体管，其中源极或漏极耦合到所述第一导体；
第二晶体管，其中源极或漏极耦合到所述第二导体；及
导电支撑结构，其耦合到所述第一晶体管的所述源极或漏极中的另一者、所述第二晶体管的所述源极或漏极中的另一者及所述第三导体。
20.根据权利要求19所述的封装，其中所述第一导体、所述第二导体及所述第三导体在所述电介质结构的所述第一表面与所述电介质结构的至少一个其它表面之间延伸。
21.根据权利要求19所述的封装，其中所述支撑结构完全覆盖所述第一晶体管及所述第二晶体管。
22.一种制造集成电力封装的方法，所述方法包括：
将集成电路定位在电介质结构内，所述衬底具有表面；
将第一导体定位在所述表面与所述电介质结构上的另一点之间；
将第二导体定位在所述表面与所述电介质结构上的另一点之间；
将第一晶体管耦合到导电支撑结构；
将第二晶体管耦合到所述支撑结构；
将所述支撑结构、所述第一晶体管与所述第二晶体管的组合耦合到所述电介质结构，其中所述第一晶体管耦合到所述第一导体且所述第二晶体管耦合到所述第二导体。
23.一种制造集成电力封装的方法，所述方法包括：
将集成电路定位在电介质结构内，所述衬底具有表面；
将第一导体定位在所述表面与所述电介质结构上的另一点之间；
将第二导体定位在所述表面与所述电介质结构上的另一点之间；
将第一晶体管耦合到所述第一导体；
将第二晶体管耦合到所述第二导体；
将所述电介质结构、所述第一晶体管与所述第二晶体管的组合耦合到导电支撑结构。
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