CN106603442B - A kind of cross clock domain high-speed data communication interface circuit of network-on-chip - Google Patents
A kind of cross clock domain high-speed data communication interface circuit of network-on-chip Download PDFInfo
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- CN106603442B CN106603442B CN201611153386.5A CN201611153386A CN106603442B CN 106603442 B CN106603442 B CN 106603442B CN 201611153386 A CN201611153386 A CN 201611153386A CN 106603442 B CN106603442 B CN 106603442B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
A kind of cross clock domain high-speed data communication interface circuit of network-on-chip, is mounted on the routing node of network-on-chip, including following three modules: input multiple selector module, data buffering memory module and output multi-channel selector module；The output end of the input multiple selector module is connected to the input terminal of data buffering memory module, and the output end of data buffering memory module is connected to the input terminal of output multi-channel selector module.The data buffering memory module, including multiple annular asynchronous FIFOs based on token ring, the input terminal of multiple annular asynchronous FIFOs based on token ring is parallel-connected to the output end of input multiple selector module, and the output end of multiple annular asynchronous FIFOs based on token ring is parallel-connected to the input terminal of output multi-channel selector module.In circuit structure, the high data rate bit stream Jing Guo data buffering memory module is continuously carried out to operation and processing, realizes the seamless buffering and transmission of data code flow.
Description
Technical field
The invention belongs to digital integrated electronic circuit fields, and in particular to a kind of cross clock domain high-speed data communication of network-on-chip
Interface circuit.
Background technique
With the complication that the fast development of domestic microelectric technique and FPGA system design, integrate on a single chip
Hundreds of IP kernels have become possibility.The appearance of network-on-chip (Network on chip, NOC) meets numerous IP kernel communications
Demand.However, traditional Design of Synchronization Technology uses single voltage clocks domain, the raising and power consumption of NOC performance are limited
It reduces, has been increasingly becoming the design bottleneck of network-on-chip.In actual engineering, especially high-speed video acquisition and processing system
In, each functional module of internal system generally requires work in the clock domain of different frequency, and cross clock domain processing can not be kept away
Exempt from.
In order to solve this problem, cross clock domain synchronous circuit mechanism and its design method become network-on-chip in recent years
Research hotspot.Common cross clock domain synchronous circuit has: two-stage or multi-level register synchronization, level synchronization, shaking hands synchronizes, is different
Walk FIFO etc..Although these design methods are to a certain extent, cross clock domain is reduced well and transmits brought metastable state
Influence, but still be unable to satisfy network-on-chip and real-time Transmission carried out to large capacity, more bits and high speed stream of video data
Demand.
The design core problem of network-on-chip clock-domain crossing data communication interface at present, first is that how to solve cross clock domain
Metastable issues caused by data transmission；Second is that how to realize the transmission of network-on-chip cross clock domain high-speed data, avoid counting
According to loss and transmit the discontinuous of data.The data transmission that cross clock domain is carried out between network-on-chip adjacent node easily causes Asia
Stable state leads to loss of data, influences the performance of network-on-chip high-speed video data processing system.MTBF(Mean time of
Failure, mean free error time) it is to measure metastable efficiency index, the value of MTBF is bigger, then metastable issues occurs
Probability is with regard to smaller.The calculation formula of MTBF are as follows:
MTBF=eTmet/C2/C1·fclk·fdata
Summary of the invention
In view of the deficiencies of the prior art, the present invention proposes a kind of cross clock domain high-speed data communication interface electricity of network-on-chip
Road.The probability that metastable issues occur is preferably minimized, meanwhile, it meets network-on-chip large capacity, more bits and regards at high speed
The requirement of the real-time Transmission of frequency data code flow.
The specific technical solution of the present invention is as follows:
A kind of clock-domain crossing data communication interface circuit of network-on-chip proposed by the present invention is by input multiple selector
Module, data buffering memory module and output multi-channel selector module three parts composition.Input the defeated of multiple selector module
Outlet is connected to the input terminal of data buffering memory module, and the output end of data buffering memory module is connected to output multi-channel selection
The input terminal of device module.
Data buffering memory module, including multiple annular asynchronous FIFOs based on token ring, multiple rings based on token ring
The input terminal of shape asynchronous FIFO is parallel-connected to the output end of input multiple selector module, and multiple annulars based on token ring are different
The output end of step FIFO is parallel-connected to the input terminal of output multi-channel selector module.
Annular asynchronous FIFO based on token ring, including token ring architecture, token ring architecture include eight latch, eight
The connection type of latch is the input terminal that the output end of the latch of upper level is connected to the latch of next stage, afterbody
The output end of latch be connected to the input terminal of first order latch.
Input data caused by the video acquisition IP kernel of network-on-chip is input to input multiple selector module, described
Input data is sequentially output data buffering memory module in the effective situation of enable signal by input multiple selector module,
The output multi-channel selector module in the effective situation of enable signal by the data in data buffering memory module successively
It reads, and the video that output data is sent into network-on-chip is handled into IP kernel.
Token ring architecture in annular asynchronous FIFO based on token ring, the state of latch are defined as token when being 1, when
When enable signal is effective, the numerical value in upper level latch will be transferred in next stage latch, in afterbody latch
Numerical value will be transferred in first order latch, generated by the movement and adjustment of token based on token ring annular it is asynchronous
The read/write pointer of FIFO controls the read/write operation of the annular asynchronous FIFO based on token ring.
Beneficial effects of the present invention are as follows:
The invention proposes a kind of cross clock domain high-speed data communication interface circuits of network-on-chip.In circuit structure,
Using the design philosophy of the annular asynchronous FIFO based on token ring, pass through input multiple selector module and output multi-channel selector
The design of module allows the annular asynchronous FIFO based on token ring by beat, mutually matched switching, will pass through data buffering
The high data rate bit stream of memory module continuously carries out operation and processing, realizes the seamless buffering and transmission of data code flow.
A kind of cross clock domain high-speed data communication interface circuit of network-on-chip proposed by the invention, ingenious in design, knot
Structure is simple, reliable and metastable influence can be greatly reduced.The experimental results showed that the cross clock domain high speed of the network-on-chip
Data communication interface circuit can realize the real-time biography of large capacity, more bits and high speed stream of video data on network-on-chip
It is defeated, it ensure that the stability of network-on-chip high-speed video data processing system.
Detailed description of the invention
Fig. 1 is the cross clock domain high-speed data communication interface circuit design of the network-on-chip in the specific embodiment of the invention
Block diagram；
Fig. 2 is the token ring architecture figure in the specific embodiment of the invention；Wherein, figure (a) is specific embodiment party of the present invention
The token ring architecture figure of write pointer in formula, figure (b) are the token ring architecture figure of the read pointer in the specific embodiment of the invention；
Fig. 3 is the input multiple selector module RTL structure chart in the specific embodiment of the invention；
Fig. 4 is the output multi-channel selector module RTL structure chart in the specific embodiment of the invention；
Fig. 5 is the cross clock domain high-speed data communication interface circuit in the specific embodiment of the invention in network-on-chip
Application drawing；
Fig. 6 is the cross clock domain high-speed data communication interface circuit top layer of the network-on-chip in the specific embodiment of the invention
RTL structure chart.
Specific embodiment
With reference to the accompanying drawing, with the network-on-chip that is constituted using four parallel token ring annular fifo structures across clock
For numeric field data communication interface circuit, to a kind of embodiment of the invention, it is described further.
A kind of cross clock domain high-speed data communication interface circuit of network-on-chip proposed by the present invention, is selected by input multichannel
Select device module, data buffering memory module and output multi-channel selector module three parts composition.Input multiple selector module
Output end be connected to the input terminal of data buffering memory module, the output end of data buffering memory module is connected to output multi-channel
The input terminal of selector module.The cross clock domain high-speed data communication interface circuit design block diagram of network-on-chip is as shown in Figure 1.
Data buffering memory module, including multiple annular asynchronous FIFOs based on token ring, multiple rings based on token ring
The input terminal of shape asynchronous FIFO is parallel-connected to the output end of input multiple selector module, and multiple annulars based on token ring are different
The output end of step FIFO is parallel-connected to the input terminal of output multi-channel selector module.
Conventional asynchronous FIFO, includes a two-port RAM, and a port is used to the write-in of data, i.e., is stored in data
To asynchronous FIFO, another port is used as the reading of data, i.e., reads data from asynchronous FIFO.Asynchronous FIFO utilization reading/
Write pointer is full come the sky for judging asynchronous FIFO, and when read pointer catch up with write pointer, asynchronous FIFO is sky；Refer to when write pointer catch up with reading
When needle, asynchronous FIFO is full.
Due to being easier to ask when a binary count value is transformed into another clock domain from a clock domain
When inscribing, and being counted using binary counter, all positions may all change simultaneously, multiple along synchronizing in the same clock
Signal is easier generating metastable problem.Therefore the present invention uses token ring architecture, using token as the read/write of asynchronous FIFO
Pointer generates the variation of read/write pointer by the running transform of token, and read/write pointer is synchronized to asynchronous clock domain and is carried out
Compare, and using it as the detection of empty full state.
Annular asynchronous FIFO based on token ring, including token ring architecture, token ring architecture include eight latch, eight
The connection type of latch is the input terminal that the output end of the latch of upper level is connected to the latch of next stage, afterbody
The output end of latch be connected to the input terminal of first order latch, and provide that token ring high level signal is effective, wherein wr
For write pointer, rr is read pointer, and token ring architecture figure is as shown in Fig. 2, wherein Fig. 2 (a) is the token ring architecture figure of write pointer, figure
(b) the token ring architecture figure of read pointer.The output of afterbody is connected with the input of the first order and constitutes an annular, wherein locking
The state of storage is defined as token when being 1, and when enable signal is effective, the numerical value in upper level latch will be transferred to next
In grade latch, the numerical value in afterbody latch will be transferred in first order latch, movement and tune by token
The whole read/write pointer to generate the annular asynchronous FIFO based on token ring, control the annular asynchronous FIFO based on token ring reading/
Write operation.Annular asynchronous FIFO based on token ring has and only one a read pointer rr and write pointer wr, they are to enable
The form of board is transmitted clockwise in token ring, and when the annular asynchronous FIFO based on token ring carries out write operation, write pointer refers to
Data storage is carried out to the annular asynchronous FIFO data storage cell based on token ring, after having stored data, under write pointer is directed toward
Level one data storage unit.Similarly, when the annular asynchronous FIFO based on token ring carries out read operation, read pointer is directed toward based on order
The annular asynchronous FIFO data storage cell of board ring carries out data reading, completes after reading data, read pointer is directed toward next stage data
Storage unit, read-write operation recycle progress with this.
The read/write pointer that the annular asynchronous FIFO based on token ring is generated by the movement and adjustment of token, simplifies
Conventional asynchronous FIFO avoids using a large amount of synchronizer, reduces area space, make the property of the annular FIFO based on token
Can have and improve significantly, can satisfy the requirement of big data quantity video data real-time Transmission.
The input port for inputting multiple selector module includes clock signal port clk1, global reset signal port
Wrst_n and data input signal port data_in, output port include four fifoi_wen (i=1,2,3,4) write-ins
Enable signal port and four data export wi_data (i=1,2,3,4) signal port, input multiple selector module RTL knot
Composition is as shown in Figure 3.The specific work steps for inputting multiple selector module is as follows:
When clock signal clk1 and global reset signal wrst_n effective, valid data pass through the port data_in for data
Write-in input multiple selector module.
Data when fifo1_wen is effective in characterization input multiple selector module are exported from w1_data；
Data when fifo2_wen is effective in characterization input multiple selector module are exported from w2_data；
Data when fifo3_wen is effective in characterization input multiple selector module are exported from w3_data；
Data when fifo4_wen is effective in characterization input multiple selector module are exported from w4_data.
The input port of output multi-channel selector module includes clock signal port clk2, global reset signal port
Rrst_n and four data input signal port data_in2i (i=1,2,3,4), output port include four fifoi_ren (i
=1,2,3,4) it reads enable signal port and a data exports r_data signal port, output multi-channel selector module RTL
Structure chart is as shown in figure 4, specific work steps is as follows.
When fifo1_ren is effective, the data in input port data_in21 are output to by output multi-channel selector module
Output port r_data；
When fifo2_ren is effective, the data in input port data_in22 are output to by output multi-channel selector module
Output port r_data；
When fifo3_ren is effective, the data in input port data_in23 are output to by output multi-channel selector module
Output port r_data；
When fifo3_ren is effective, the data in input port data_in24 are output to by output multi-channel selector module
Output port r_data.
The cross clock domain high-speed data communication interface circuit of designed network-on-chip is mounted on network-on-chip, is such as schemed
Shown in 5.Wherein (0,0) routing node is in the lower left corner of entire network-on-chip, and (3,3) routing node is on the right side of entire network-on-chip
Upper angle, X-coordinate are sequentially increased from left to right, and Y-coordinate is sequentially increased from bottom to top.The routing node of network-on-chip can be with carry phase
Video acquisition IP kernel and video the processing IP kernel answered.Video acquisition IP kernel is mounted to (1,3) routing node, video is handled into IP
Core is mounted to (2,1) routing node.The clock of (1,3) routing node is CLK1, and the clock of (2,1) routing node is CLK2.Piece
Input data caused by the video acquisition IP kernel of upper network is input to input multiple selector module, inputs multiple selector mould
Input data is sequentially output data buffering memory module, output multi-channel selector mould in the effective situation of enable signal by block
Block sequential reads out the data in data buffering memory module in the effective situation of enable signal, and output data is sent into piece
The video of upper network handles IP kernel.
Network-on-chip completion video acquisition, transmission, the specific work steps of processing are as follows:
Firstly, collected valid data are transferred to the input port of input multiple selector by video acquisition IP kernel, lead to
Which wflag flag bit is crossed to judge data buffer storage to the annular asynchronous FIFO based on token ring.
First be written efficiently into the clock cycle arrive when, video acquisition IP kernel by valid data by input multiple selector
The annular asynchronous FIFO 1 based on token ring is written in module first；
Second be written efficiently into the clock cycle arrive when, video acquisition IP kernel by valid data by input multiple selector
The annular asynchronous FIFO 2 based on token ring is written in module；
When third is written efficiently into clock cycle arrival, valid data are passed through input multiple selector by video acquisition IP kernel
The annular asynchronous FIFO 3 based on token ring is written in module；
4th be written efficiently into the clock cycle arrive when, video acquisition IP kernel by valid data by input multiple selector
The annular asynchronous FIFO 4 based on token ring is written in module.
Secondly, being judged by rflag flag bit, the annular based on token ring of output multi-channel selector module output is asynchronous
Valid data in FIFO are read in annular asynchronous FIFO from which based on token ring.
It is when first effective readout clock period arrives, the valid data of the annular asynchronous FIFO 4 based on token ring are defeated
The output port of output multi-channel selector module is arrived out；
It is when second effective readout clock period arrives, the valid data of the annular asynchronous FIFO 1 based on token ring are defeated
The output port of output multi-channel selector module is arrived out；
It is when third effective readout clock period arrives, the valid data of the annular asynchronous FIFO 2 based on token ring are defeated
The output port of output multi-channel selector module is arrived out；
It is when 4th effective readout clock period arrives, the valid data of the annular asynchronous FIFO 3 based on token ring are defeated
The output port of output multi-channel selector module is arrived out.
Finally, passing through the output port of output multi-channel selector module and the local side of network-on-chip (1,3) routing node
Valid data are transferred to network-on-chip by the connection of mouth, output multi-channel selector module, the significant figure in (1,3) routing node
According to by the routing algorithm of network-on-chip, being transmitted to (2,1) routing node, then be transmitted to video by local port and handle IP
Core.
By analyzing above it is found that using input multiple selector module, output multi-channel selector module and data buffering
Memory module, and being used cooperatively reduces a possibility that metastable state occurs to the full extent, simplify network-on-chip across
The structure of clock domain high-speed data communication interface circuit.And use the cross clock domain high-speed data communication interface electricity of network-on-chip
Road, network-on-chip can support the communication of multi-clock zone IP kernel, and it is high can to further decrease the cross clock domain based on network-on-chip
The power consumption of fast data processing system.In addition, passing through input multiple selector module and output multi-channel selector module in the structure
Allow the annular asynchronous FIFO based on token ring by beat, mutually matched switching, by the stream of video data by buffering
It is continuously sent to carry and handles IP kernel in the video of network-on-chip, realize the seamless buffering and transmission of data code flow.If from piece
Data transmission procedure is seen at the both ends of the top-level module of the cross clock domain high-speed data communication interface circuit of upper network, input data and
Output data is all continuously to be written and continuously read, without any pause, as shown in Figure 6.Therefore, the structure
Be very suitable for the pipeline of high-speed data-flow, meet high-speed video data code stream carried out on network-on-chip it is seamless
Buffering and real-time Transmission.
Claims (3)
1. a kind of cross clock domain high-speed data communication interface circuit of network-on-chip, is mounted on the routing node of network-on-chip,
It is characterised in that it includes following three modules: input multiple selector module, data buffering memory module and output multi-channel selection
Device module；
The output end of the input multiple selector module is connected to the input terminal of data buffering memory module, and data buffering is deposited
The output end of storage module is connected to the input terminal of output multi-channel selector module；
The data buffering memory module, including multiple annular asynchronous FIFOs based on token ring, described is multiple based on order
The input terminal of the annular asynchronous FIFO of board ring is parallel-connected to the output end of input multiple selector module, described multiple to be based on
The output end of the annular asynchronous FIFO of token ring is parallel-connected to the input terminal of output multi-channel selector module；
The annular asynchronous FIFO based on token ring, including token ring architecture, the token ring architecture include eight locks
Storage, the connection type of eight latch are that the output end of the latch of upper level is connected to the latch of next stage
Input terminal, the output end of the latch of afterbody are connected to the input terminal of first order latch；
Using token as the read/write pointer of asynchronous FIFO, the variation of read/write pointer is generated by the running transform of token, it will
Read/write pointer is synchronized to asynchronous clock domain and is compared, and using it as the detection of empty full state.
2. a kind of communication party of the cross clock domain high-speed data communication interface circuit of network-on-chip according to claim 1
Method, which is characterized in that input data caused by the video acquisition IP kernel of the network-on-chip is input to input multi-path choice
Input data is sequentially output data in the effective situation of enable signal by device module, the input multiple selector module
Buffered memory module, the output multi-channel selector module is in the effective situation of enable signal by data buffering memory module
In data sequential read out, and by output data be sent into network-on-chip video handle IP kernel.
3. a kind of communication party of the cross clock domain high-speed data communication interface circuit of network-on-chip according to claim 1
Method, which is characterized in that the token ring architecture in the annular asynchronous FIFO based on token ring, when the state of latch is 1
It is defined as token, when enable signal is effective, the numerical value in upper level latch will be transferred in next stage latch, finally
Numerical value in level-one latch will be transferred in first order latch, be generated by the movement and adjustment of token based on token
The read/write pointer of the annular asynchronous FIFO of ring controls the read/write operation of the annular asynchronous FIFO based on token ring.
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| CN201611153386.5A CN106603442B (en) | 2016-12-14 | 2016-12-14 | A kind of cross clock domain high-speed data communication interface circuit of network-on-chip |
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| US10607692B2 (en) * | 2017-06-29 | 2020-03-31 | SK Hynix Inc. | Serializer and memory device including the same |
| CN110191069B (en) * | 2019-05-31 | 2021-04-06 | 西安理工大学 | Annular network on chip with multiple channels |
| CN110365530A (en) * | 2019-07-11 | 2019-10-22 | 电子科技大学 | A kind of test token passing network independently of network-on-chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1524215A (en) * | 2001-06-20 | 2004-08-25 | Ħ��������˾ | First-in, first-out memory system and method thereof |
| CN102063408A (en) * | 2010-12-13 | 2011-05-18 | 北京时代民芯科技有限公司 | Data bus in multi-kernel processor chip |
| CN102541506A (en) * | 2010-12-29 | 2012-07-04 | 深圳市恒扬科技有限公司 | First-in-first-out (FIFO) data register, chip and equipment |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1524215A (en) * | 2001-06-20 | 2004-08-25 | Ħ��������˾ | First-in, first-out memory system and method thereof |
| CN102063408A (en) * | 2010-12-13 | 2011-05-18 | 北京时代民芯科技有限公司 | Data bus in multi-kernel processor chip |
| CN102541506A (en) * | 2010-12-29 | 2012-07-04 | 深圳市恒扬科技有限公司 | First-in-first-out (FIFO) data register, chip and equipment |
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