CN106603113A - Radar signal processor external communication control system - Google Patents
Radar signal processor external communication control system Download PDFInfo
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- CN106603113A CN106603113A CN201611059626.5A CN201611059626A CN106603113A CN 106603113 A CN106603113 A CN 106603113A CN 201611059626 A CN201611059626 A CN 201611059626A CN 106603113 A CN106603113 A CN 106603113A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
- Small-Scale Networks (AREA)
Abstract
The invention discloses a radar signal processor external communication control system. The radar signal processor external communication control system comprises an FPGA, which comprises a transceiving module used for interface management and transceiving of serial communication; a DSP, which is connected with the FPGA, and is used for control of transceiving time sequences, processing of communication protocol content, and configuration of communication parameters; and a connector, which is in a bidirectional connection with the FPGA. The radar signal processor external communication control system is advantageous in that the internal resources of the FPGA and the DSP are fully used, and a special 422 communication chip is not required, and corresponding peripheral circuit design is reduced, and therefore the communication control of the signal processor over other components of the radar is realized stably, and power consumption of a single device and device costs are reduced; parameter configuration is realized, and the requirements of the system on the diverse working modes are satisfied.
Description
Technical field
The present invention relates to radar digital signal processing field, more particularly to a kind of radar signal processor correspondence with foreign country control
System.
Background technology
The component of existing radar system often takes targeted design according to mission requirements, and mode of operation is relatively single,
What the control signal wire design between signal processor and system other assemblies was mostly taken is to be fixedly connected mode.With radar
The variation of working system, Composite, it is no longer single that the complication of the workflow of radar system causes each component mode of operation
One or fixed model, the requirement to component is increasingly improved；Accordingly, the control signal between signal processor and system other assemblies
Quantity be also significantly increased, and in order to avoid different rates and different types of control signal are interfered between wiring, often
The form for taking shielding line to isolate, the method for attachment of traditional control signal wire causes the volume of connector to become system design
Important restriction factor, brings many unnecessary troubles.Meanwhile, radar system also proposed system compact and low-power consumption etc. its
He requires that hardware, software resource need to will be inclined more in terms of signal processing, and project contracts again and again with the R＆D cycle of product
Subtract, therefore control communication of the signal processor to component should take digital form to carry out, communication will with the realization of control function
Ask and realize simplifying and generalization based on existing hardware design, to strengthen the inheritance of design, reduce debugging complexity, reduce
System design and the time of inter-component communication control debugging.
Communicate communication mode reliable as a kind of simple and stable in view of serial 422, fully excavate the interior of FPGA and DSP
Portion's resource, does not increase special 422 communication chips and peripheral circuit, designs a kind of radar signal processor based on serial communication
Communication and the scheme of control module, realize the generalization and simplification of Control on Communication between signal processor and radar system other assemblies
Design, meets the diversified requirement of system operating mode, reduces hardware cost and debugging difficulty, shortens the design cycle and develops week
Phase.
By patent retrieval, Patents 3 are retrieved altogether, respectively：Application for a patent for invention CN104808189A, sends out
A kind of MMW RADAR SIGNAL USING processing system of bright patent name and method；Application for a patent for invention CN104460427A, invention is special
Sharp name module micro-satellite platform Integrated Electronic System；Application for a patent for invention CN203444102U, utility model patent
A kind of marine radar signal processor based on FPGA and Ethernet of title.
A kind of MMW RADAR SIGNAL USING processing system of patent of invention and method are based on a kind of low of DSP minimum circuit systems
COST system is designed, and coordinates DMA control modules to carry out circuit control with multi-channel serial communication interface.Patent of invention modular microfluidic
In type satellite platform Integrated Electronic System with serial communication module realize processor module and platform unit, processor module and its
Its electronic module serial communication.A kind of marine radar signal processor based on FPGA and Ethernet of utility model patent adopt with
Too net and FPGA carry out the design of marine radar signal processor, including signal processor and communication agency, simplify system knot
Structure, with reliability is high, portable good, real-time the features such as.
Retrieved by article, related article 1, design and realization, this article of certain radar data communication system are retrieved altogether
Chapter describes the Ethernet interface hardware designs based on hardware ICP/IP protocol chip stack W5300, and using FPGA to W5300
Control realization and terminal computer between ethernet communication, and devise serial communication modular realize and each subsystem between
Serial communication.
The content of the invention
It is an object of the invention to provide a kind of radar signal processor correspondence with foreign country control system, make full use of FPGA and
DSP internal resources, do not use 422 special communication chips, reduce respective peripheral circuit design, stably realize signal processor pair
The Control on Communication of radar other assemblies, reduces the power consumption and device cost of unit；Parameter configuration is realized, system operating mode is met
Diversified requirement；The design of specification radar system components communication interface simultaneously, the inheritance of strengthening system design, improves soft or hard
Part debugs motility, reduces debugging difficulty, shortens the lead time..
In order to realize object above, the present invention is achieved by the following technical solutions：
A kind of radar signal processor correspondence with foreign country control system, is characterized in, comprising：
FPGA, it includes a transceiver module, for interface management and the transmitting-receiving of serial communication；
DSP, it is connected with FPGA, for receiving and dispatching control, the process of communication protocol content and the configuration of messaging parameter of sequential；
Connector, it is bi-directionally connected with FPGA.
Described connector is connected with several communication components, and described DSP includes some communication submodules, described
Communication component calls corresponding communication submodule to perform corresponding communication task.
Described transceiver module is included：
Address administration submodule, for the decoding to address wire, produces corresponding chip selection signal under respective address strobe；
Interface management submodule, it is connected with address administration submodule, right for being produced according to chip selection signal, frame head and command word
The reception answered/transmission is enabled；
Control submodule is received, it is connected with interface management submodule, for according to command word and data length instruction, configuration to connect
Data length, and the carrying out point/process of frequency multiplication by transmission rate request to communication clock are received, corresponding first caching read-write is produced
Enable；
Control submodule is sent, it is connected with interface management submodule, for according to command word and data length instruction, configuration to be sent out
Data length, and the carrying out point/process of frequency multiplication by transmission rate request to communication clock are sent, corresponding second caching read-write is produced
Enable；
Data receiver submodule, it is connected with control submodule is received, and reads with the first caching for being enabled according to described reception
Write enable and realize data receiver；
Data is activation submodule, its be connected with control submodule is sent, for being enabled according to described transmission and the second caching reading
Write enable and realize that data reception data sends.
Data form is start bit, data bit, check bit sum stop position in described transceiver module.
Some described communication submodules be the first communication submodule, the second communication submodule, third communication submodule and
Fourth communication submodule；The first described communication submodule is using change frame period communication mode；Second and third described communication submodule
The method that block uses timer interrupt call；The method that described fourth communication submodule is called using external interrupt.
The present invention compared with prior art, with advantages below：
1., from the angle of system, signal processor is carried out to outer control and communication module at two aspects of hardware and software
General design, improves the reproducibility and expansion of system design, realizes hardware system schematic diagram circuit design, PCB
The simplification of placement-and-routing and the parameterization operations of software system programming, enhance the versatility of control and communication module, can realize
To the Schema control and parameter configuration of other assemblies under different working condition, with stronger debugging motility, can effectively subtract
Few design and debug time；
2. the demand of current radar system components digital development has been adapted to, the core number and volume of connector can have been efficiently reduced,
The limitation of connector and wiring to overall design is reduced, there is certain reference application valency to the Miniaturization Design of radar system
Value；
3., using the control and the signal processor of communication module, other set to need connection in simulation test experiment or field trial
It is less to the change amount of code with ability is well adapted to when standby, and will not to the original program of radar signal processor and
Function is impacted, and possesses good expanded function.
Description of the drawings
Fig. 1 is a kind of system block diagram of radar signal processor correspondence with foreign country control system of the invention；
Fig. 2 is that RS422 single bytes send reception sequential chart；
Fig. 3 is 422 communications protocol format explanations；
Fig. 4 is the schematic diagram of 422 transceiver modules in FPGA；
Fig. 5 is DSP communicators Module Division and communication mode schematic diagram.
Specific embodiment
Below in conjunction with accompanying drawing, by describing a preferably specific embodiment in detail, the present invention is further elaborated.
As shown in figure 1, a kind of radar signal processor correspondence with foreign country control system, comprising：FPGA, it includes a transmitting-receiving mould
Block, for interface management and the transmitting-receiving of serial communication；DSP, it is connected with FPGA, for receiving and dispatching control, the communication protocol of sequential
The process of content and the configuration of messaging parameter；Connector, it is bi-directionally connected with FPGA.
Above-mentioned connector is connected with several communication components, and described DSP includes some communication submodules, described
Communication component calls corresponding communication submodule to perform corresponding communication task.
Above-mentioned transceiver module is included：Address administration submodule, for the decoding to address wire, produces respective address strobe
Under corresponding chip selection signal；Interface management submodule, it is connected with address administration submodule, for according to chip selection signal, frame head
Corresponding reception/transmission is produced with command word to enable；Control submodule is received, it is connected with interface management submodule, for root
According to command word and data length instruction, configure receiving data length, and by transmission rate request to the carrying out point of communication clock/times
Frequency is processed, and is produced corresponding first caching read-write and is enabled；Control submodule is sent, it is connected with interface management submodule, is used for
According to command word and data length instruction, configuration sends data length, and by transmission rate request to the carrying out point of communication clock/
Process of frequency multiplication, produces corresponding second caching read-write and enables；Data receiver submodule, it is connected with control submodule is received, and uses
Data receiver is realized in enabling according to described reception with the first caching read-write enable；Data is activation submodule, itself and send control
System module is connected, and realizes that data reception data sends with the second caching read-write enable for enabling according to described transmission.
Data form is start bit, data bit, check bit sum stop position in above-mentioned transceiver module.
Some described communication submodules be the first communication submodule, the second communication submodule, third communication submodule and
Fourth communication submodule；The first described communication submodule is using change frame period communication mode；Second and third described communication submodule
The method that block uses timer interrupt call；The method that described fourth communication submodule is called using external interrupt.
Specifically, above-mentioned connector is connected with several communication components, respectively first and second ... eight communication component,
First communication component and signal processor communicating requirement variable period transceiving data, second and third communication component is required and signal processing
Machine realizes fixed cycle data transmission-receiving function but communication cycle is different；The transmission data of the first communication component and third communication component
Amount is larger, and with reference to Fig. 2 single bytes 422 sequential chart is received and dispatched, and is calculated according to the data length and transfer rate of communication protocol content
Go out transmission time, be compared with the data update cycle, the first communication component and third communication component need to be used alone communication and connect
Mouthful, and other communication component common user communication interfaces will be unsatisfactory for data transportation requirements；Fourth, fifth and six at communication component and signal
The communication of reason machine sends for signal processor unidirectional cycle, and data volume is less and to send the cycle consistent, the second communication component and the 4th,
Five is identical with the transmission cycle of six communication components, is calculated in communication cycle, can complete respective communication according to specified order
Action, second, four, five, six communication components can be with common user communication interface；The communication of the seven, the eight communication components and signal processor
Receive for the signal processor unidirectional cycle, it is desirable to after the completion of the data is activation of the seven, the eight communication components, signal processor is just corresponding
Receive, within the data receiver cycle, can in a designated order complete the communication task of the seven, the eight communication components.
External serial communication interface quantity is 4 inside DSP used in the present embodiment, and DSP communication modules can draw
It is divided into 4 submodules, the first communication submodule, the second communication submodule, third communication submodule and fourth communication submodule, its
4 internal serial interfaces of DSP are corresponded to respectively, complete the assignment of allocation of communication submodule and DSP communication interfaces.Therefore in system
During design, the first communication component and third communication component are individually divided into into the first communication submodule and second and are communicated submodule；
Second communication component and fourth, fifth, clematis stem letter component clustering are third communication submodule 3；Seven, the eight communication components 8 are divided into
Fourth communication submodule, referring to Fig. 5.
2. VHDL hardware program languages are used, the Programming Design and parametrization of the transceiver module of serial 422 are completed in FPGA
Encapsulation, referring to Fig. 2,422 single byte of data forms are by the way of " start bit+data bit+check bit+stop position ".
Referring to Fig. 4,422 transceiver modules in FPGA need to be comprising address administration submodule, interface management submodule, control
The parts such as signal generation, transmitting/receiving program and caching.Referring to Fig. 3, the variable element set content of transceiver module includes first and second
Frame head, first, second and third command word, data length and transmission/receiving data.
Address administration by the decoding to address wire, to produce respective address strobe under corresponding chip selection signal.With reference to
First and second frame head and first and second command word, in being input to interface management submodule, produce corresponding transmitting-receiving control and enable, and select
422 modules corresponding with address wire, complete the function of data receiver or transmission.
Receive control submodule and send control submodule according to the 3rd command word and data length instruction, configuration send or
Person's receiving data length, and the carrying out point/process of frequency multiplication by transmission rate request to 422 communication clocks, produce corresponding caching
Read-write is enabled, it is ensured that data correctly entering and export.
Data is activation submodule first will in the case where the transmission that interface management program is produced is enabled and cached with effect signal control
The byte data write caching that DSP sends, router adds start bit before data, addition check bit sum stops after data
Position, meets the single byte transmission call format for sending data.Under the control that 422 communication clocks and speed adjust are instructed, adjustment
Transmission rate, the data sending terminals of Jing 422 send successively, realize data is activation function.
Data receiver program is enabled under signal control, in 422 communication clocks and speed in the reception that interface management program is produced
Under the control of rate adjust instruction, receiving velocity is adjusted, first FPGA is received into data in reception program according to start bit and stopping
Only to divide data segment, data verification is carried out according to check bit, the byte data that will be generated under caching write enable signal control
Write caching, in the case of caching is read to enable effectively, DSP reads data, realizes data receiver function.
According to different interface and component, the data address and mailing address of each serial communication interface are determined, in encapsulation DSP
Serial communication program function, in dsp software Row control, for different Control on Communication the corresponding Control on Communication of addition is required
Program.
Referring to Fig. 5, using frame period communication mode is become, signal procedure is DSP timing control programs to the first communication submodule
A part, communications control signal is frame end mark.Second communication submodule and third communication submodule use timing
The method of device interrupt call, using the timer inside DSP, the priority of the first timer is higher than the second timer to timer,
When timer interrupts to arrive, corresponding signal procedure is called, in third communication submodule, performed successively and each communication component
Communication task, complete to reset timer after communication function, wait timer interrupt next time.Fourth communication submodule is using outside
The method of interrupt call, is mainly used for receive information, and external interrupt is produced by 422 receiver modules of FPGA, in response external
Having no progeny interruption sequence of first carry out, the first external interrupt and the second external interrupt are performed successively, after completing data receiver, return to wait
State.
The signal procedure call-by mechanism of each submodule is different with control signal is interrupted, it is ensured that communicate between different submodules
It is mutually isolated.But the call format of signal procedure is identical, all by the way of parameterized function is called, first and second is configured successively
Frame head 1, first and second and three command words, data length and data content, realize generalization and simplify the thought of design.
In the present embodiment, according to communication module dividing condition, the transceiver module of packaged 4 422 is called in FPGA.
In addition, program related in FPGA also includes address administration and interface management etc..In determination sub-module is divided and communicated
After disconnected mode, the design of hardware is carried out, connect shared address wire with data wire and respective address decoding control signal, outside
Interrupt etc., realize that FPGA and DSP and correspondence with foreign country control the connection of hardware system, complete other circuits such as power supply, clock, driving
Design work.
The present invention on the basis of serial communication, based on FPGA and DSP architecture, the Control on Communication between radar system components
Using identical communication format so that the control of DSP signal procedures can realize the General design that parametrization is configured.Meanwhile,
The transmission-receiving functions of the communication of programming realization 422, eliminate 422 communication chips and peripheral circuit, while inside using DSP in FPGA
Serial communication interface, simplifies hardware designs, has saved hardware cost, facilitates implementation the adjustment of traffic rate.At signal
Control on Communication between reason machine and system other assemblies employs serial communication mode, changes original Control on Communication connection side
Formula, reduces the quantity of control line and the volume of wiring, the advantage with Miniaturization Design, with engineering realizability.
Although present disclosure has been made to be discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
Various modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (5)
1. a kind of radar signal processor correspondence with foreign country control system, it is characterised in that include：
FPGA, it includes a transceiver module, for interface management and the transmitting-receiving of serial communication；
DSP, it is connected with FPGA, for receiving and dispatching control, the process of communication protocol content and the configuration of messaging parameter of sequential；
Connector, it is bi-directionally connected with FPGA.
2. radar signal processor correspondence with foreign country control system as claimed in claim 1, it is characterised in that described connector
Several communication components are connected with, and described DSP includes some communication submodules, described communication component calls corresponding logical
Letter submodule performs corresponding communication task.
3. radar signal processor correspondence with foreign country control system as claimed in claim 1, it is characterised in that described transmitting-receiving mould
Block is included：
Address administration submodule, for the decoding to address wire, produces corresponding chip selection signal under respective address strobe；
Interface management submodule, it is connected with address administration submodule, right for being produced according to chip selection signal, frame head and command word
The reception answered/transmission is enabled；
Control submodule is received, it is connected with interface management submodule, for according to command word and data length instruction, configuration to connect
Data length, and the carrying out point/process of frequency multiplication by transmission rate request to communication clock are received, corresponding first caching read-write is produced
Enable；
Control submodule is sent, it is connected with interface management submodule, for according to command word and data length instruction, configuration to be sent out
Data length, and the carrying out point/process of frequency multiplication by transmission rate request to communication clock are sent, corresponding second caching read-write is produced
Enable；
Data receiver submodule, it is connected with control submodule is received, and reads with the first caching for being enabled according to described reception
Write enable and realize data receiver；
Data is activation submodule, its be connected with control submodule is sent, for being enabled according to described transmission and the second caching reading
Write enable and realize that data reception data sends.
4. radar signal processor correspondence with foreign country control system as claimed in claim 1, it is characterised in that described transmitting-receiving mould
Data form is start bit, data bit, check bit sum stop position in block.
5. radar signal processor correspondence with foreign country control system as claimed in claim 1, it is characterised in that some described logical
Letter submodule is the first communication submodule, the second communication submodule, third communication submodule and fourth communication submodule；Described
First communication submodule is using change frame period communication mode；Second and third described communication submodule uses timer interruption
The method called；The method that described fourth communication submodule is called using external interrupt.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108181846A (en) * | 2017-12-12 | 2018-06-19 | 中国电波传播研究所（中国电子科技集团公司第二十二研究所） | A kind of multiple array radar module sequential control method |
| CN108667507A (en) * | 2018-05-31 | 2018-10-16 | 中国空间技术研究院 | A kind of intelligent open integrated electronic system of satellite |
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| CN107728517B (en) * | 2017-09-29 | 2020-05-29 | 北京航空航天大学 | Universal intermediate frequency signal processing method based on embedded ARM |
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| CN108181846A (en) * | 2017-12-12 | 2018-06-19 | 中国电波传播研究所（中国电子科技集团公司第二十二研究所） | A kind of multiple array radar module sequential control method |
| CN108181846B (en) * | 2017-12-12 | 2020-02-18 | 中国电波传播研究所（中国电子科技集团公司第二十二研究所） | Multi-array radar module time sequence control method |
| CN108667507A (en) * | 2018-05-31 | 2018-10-16 | 中国空间技术研究院 | A kind of intelligent open integrated electronic system of satellite |
| CN108667507B (en) * | 2018-05-31 | 2020-11-20 | 中国空间技术研究院 | Intelligent open type integrated electronic system for satellite |
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| CN106603113B (en) | 2019-04-23 |
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