CN1065997C - Two stage mixed direct series spread spectrum/code devision multiple access communication fast capturing structure - Google Patents
Two stage mixed direct series spread spectrum/code devision multiple access communication fast capturing structure Download PDFInfo
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- CN1065997C CN1065997C CN98103027A CN98103027A CN1065997C CN 1065997 C CN1065997 C CN 1065997C CN 98103027 A CN98103027 A CN 98103027A CN 98103027 A CN98103027 A CN 98103027A CN 1065997 C CN1065997 C CN 1065997C
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Abstract
The present invention relates to a two stage mixed direct sequence spread spectrum/code division multiple access communication fast capturing structure. A matched filter is utilized to combine a detection method of fixed dwell time [integral time] with a detection method of variable dwell time to obtain the fast capturing aim. The present invention has the characteristics that the verification time of the existing capturing method can be greatly reduced, and the receiving time of the receiver of the direct sequence spread spectrum/code division multiple access communication is effectively reduced. The present invention belongs to the spread spectrum/code division multiple access communication field.
Description
The invention belongs to spread spectrum and CDMA communication field.The present invention relates to two stage mixed direct sequence spread spectrum/CDMA communication and arrest soon and catch structure, utilize matched filter fixedly the detection method of dead time (time of integration) and variable dead time combine, reach and realize the purpose of catching fast.Characteristics of the present invention are the checking time that can shorten greatly in the existing method for catching, thereby effectively shorten the turn-on time of receiver in direct sequence spread spectrum/CDMA communication.
Many Inherent advantages of code division multiple access (CDMA) make its optimal candidate that becomes the 3G (Third Generation) Moblie multiple access technology, but reliable initial fast the seizure remains the problem that needs solve.Catch the checks that generally are counted as two simple hypothesises that oppose mutually, testing process judges whether the phase difference of received signal and local reference signal drops within the capture range of tracking circuit.The performance of capturing technology is general to be weighed with average pull-in time and detection probability and false alarm probability, under necessarily detection probability and false alarm probability condition, requires average pull-in time short as far as possible.
In the big capacity C DMA system, improve capture velocity and mean the reduction system interference, improve the level of resources utilization, scheme that realization is caught fast and algorithm are so far still in continuous research and discussion.Existing quick seizure scheme mostly adopts matched filter to realize, serial, parallel and string and mixing are arranged on the structure, and parallel organization has higher capture velocity but complexity is bigger, and string and mixed structure fall between.Catch the algorithm pair pause modes that adopt, be divided into two-stage: search and verification are also referred to as two kinds of patterns more.The first order is got rid of the less state (cell) of synchronous possibility fast, and the second level makes false alarm probability reduce to minimum.The majority logic method is generally adopted in verification, and blanking time, T carried out threshold judgement one time second, and detection variable surpasses thresholding more than B time in A judgement then confirms to catch successfully, starts tracking circuit work, otherwise reinitializes, and returns search pattern.As seen no matter court verdict certainly whether, the verification stage must spend AT time second.
Sequential detection is the detection method of a kind of variable dead time, is with the maximum difference of fixing dead time, judges that a hypothesis is whether definite in advance for very needed hits (or pull-in time), but result according to the observation and deciding.The information of utilizing observation post to provide, sequential the detection always detection efficiency than fixed sampling number are higher.Be called sequential probability than the sequential detection of (SPRT) in all possible detection method, under given detection probability and false alarm probability condition, it is the shortest to reach judgement required time (or sampling number), in this sense, is a kind of best approach.Under the prerequisite that guarantees same detection probability and false alarm probability, the capture velocity of SPRT can be than fast two to ten times of the capture velocity of single fixing dead time structure of pausing.
The fixing capturing structure of dead time, its pull-in time consumed in a large number in the verification stage, adopted parallel organization to shorten search time, can not compress checking time.
The objective of the invention is to utilize the characteristic of matched filter, the fixing detection method of dead time and variable dead time is combined, a kind of circuit arrangement fast and method are provided.Quick capturing technology scheme of the present invention is mixed fast capturing structure based on the two-stage of serial matched filter and is finished, the first order adopts the matched filter of fixed sample number, matched filter is transformed in the second level, make it to become the integrator of quick output, in order to realize the SFRT of variable sampling number, the result that mix at the two poles of the earth can shorten checking time greatly, thereby shortens whole pull-in time.
Circuit arrangement of the present invention is characterised in that:
1) this circuit arrangement is made of the two-stage cascade, and the first order is a matched filter, and the second level is a quick point device, and the latter is in order to realize the integration to first order output;
2) matched filter of the first order adopts the syndeton of band reference arm, be described matched filter by straight-through matched filter with form with reference to matched filter, straight-through matched filter provides the baseband signal of channel, provides estimation to channel disturbance with reference to matched filter;
3) partial quick point device is the simplification to matched filter, can think to be equivalent to the matched filter of local reference signal for complete " 1 ".
The first order realizes the fixedly detection of dead time, and the basic estimation of thresholding is provided by the reference matched filter.After the first order captures signal, enter partial verification, when carrying out verification, the reference matched filter of the first order transfers the reference that the second level provides channel estimating to, comprises the biasing and the signal-to-noise ratio (SNR) estimation of second level needs.
Partial algorithm is finished jointly by the matched filter and the partial quick point device of the first order, realizes the detection of variable dead time, and promptly preface is used to detect.
Fixedly the seizure of dead time is isolated observes, and last observation post obtains information and do not utilized by later observation, therefore, no matter finally which kind of judgement is hypothesis made, even the result who negates also will wait for the same time.With regard to capture velocity, matched filter (MF) is directly proportional with complexity than the relevant degree that improves of sliding, and also promptly exchanges capture velocity for circuit complexity.In fact, MF structure shown in Figure 1 provides the potentiality of three aspects: (1) output speed is fast, and every sampling output once.This is that the big time-bandwidth product of MF determines, this point is higher than its initial capture velocity to slide relevant just.(2) output signal-to-noise ratio height.With directly carry out the square-law envelope and compare from input, signal to noise ratio improves M doubly.(3) channel disturbance power is estimated accurately.More than three aspect potentiality in traditional MF seizure mechanism and be underutilized.Yet the but variable just dead time of these three characteristics, mechanism institute was necessary.
The dead time of SPRT according to the observation the result and decide, the useful information that continuous integration is repeatedly observed, input signal-to-noise ratio are big more, the information accumulation process is fast more, required detection time is short more, and detecting reliability is also high more, so the performance of SPRT is responsive to input signal-to-noise ratio.The decision threshold of SPRT is decided according to the design point signal to noise ratio, and whether the estimation of biasing is accurate, directly influences court verdict, so SPRT also is responsive to biasing.
The input signal of traditional SPRT is directly taken from receiver inlet, and all based on little signal to noise ratio design, building method is relevant to slide.Consider that matched filter is actually structure high-performance SPRT necessary condition is provided, if cascade-SPRT has then formed the mixed type fast capturing structure, both can utilize the quick seizure performance of MF, the useful potentiality that it is provided are applied to SPRT again, constitute high performance second level checking mode.For effectively shortening the observation cycle, the distressed structure of matched filter is adopted in the second level of the present invention, and no local reference signal is the simplification to matched filter, only realizes output integrator fast with shift register and adder.(as shown in Figure 1).
The inventive method workflow is as follows:
(1) definition second level decision threshold is B;
(2) the maximum amount of testing in the definition second level is N
t
(3) first order be multiply by the threshold value of COEFFICIENT K as first order judgement with reference to the output R of matched filter, with all N of the second level
tThe whole zero clearings of level shift register.When the output X of the straight-through matched filter of the first order surpasses threshold value, entered for the 4th step, otherwise repeated for the 3rd step;
(4) second level begins to start.The output X of the straight-through matched filter of the first order is as partial input, and the first order is multiplied by channel estimation coefficient B as biasing D with reference to the output R of matched filter;
(5) with the output S of second level adder
kCompare with thresholding B, if S
k＞B entered for the 6th step, otherwise return for the 3rd step;
(6) shift register displacement in the second level once if second level shift register is full, confirms then to have realized that synchronously, second level checking procedure finishes, and sets up synchronously, if second level shift register is discontented, gets back to for the 4th step.Description of drawings: Fig. 1 is a circuit arrangement functional-block diagram of the present invention;
Fig. 2 is the inventive method workflow block diagram.Good effect of the present invention:
1. shorten the checking time in the method for catching greatly.
2. effectively shorten the turn-on time of receiver in direct sequence spread spectrum/CDMA communication.
Embodiments of the invention are shown in Figure of description 1.Two stage mixed direct sequence spread spectrum/CDMA communication capturing structure is made of the incoherent matched filter of square-law and a quick point device cascade of a band reference arm.Among the figure, the signal that r (t) expression receiver is received, cos (ω
0T) and sin (ω
0T) represent local homophase and quadrature carrier components, ω respectively
0The expression carrier angular frequencies.MF
RExpression is with reference to matched filter, MF
DThe straight-through matched filter of expression.K is a first order thresholding coefficient.T represents the time span of matched filter, and unit is second.
Comprise several chip width in the time span T, X is the output signal of first order matched filter put-through channel, R is the output signal of first order matched filter reference channel, D is partial input biasing, is multiplied by a channel estimation coefficient and is obtained by the output signal R of first order reference channel.X is through being spaced apart T
sSampling after, subtract each other with second level input biasing D and to obtain Z
i, Z
iInput signal for second level quick point device.N
tProgression for second level shift register.SK is the output signal of second level quick point device.
Capture-process of the present invention is divided into two kinds of patterns: search pattern and checking mode.Search mission is served as by the MF of the first order, adopts fixedly dead time mode, in case threshold judgement passes through, then supposition has realized entering second level checking mode immediately synchronously.Search procedure branch two-stage is carried out, partial checking procedure adopts the sequential detection of variable dead time, partial circuit is realized being made of a shift register and an adder, adder is finished the addition to all taps of shift register, realizes the quick point to the output of first order matched filter.The partial SPRT mode that is verified as the variable dead time.If the second level by verification, is promptly confirmed to have realized that capture-process declares to be finished synchronously; On the contrary, when negating when having realized synchronous hypothesis, then reinitializes, return the first order and enter initial seizure.
First order matched filter is realized the fixedly detection of dead time, and the verification to hypothesis that the first order produces is finished in the second level.Variable dead time check is realized in the second level, or claims sequential detection.Its operation principle detects than (SPRT) based on monolateral sequential probability.
The inventive method workflow is described below: (referring to accompanying drawing 2)
1. definition second level decision threshold is B, and B can be definite value, or adopts adaptive approach channel is estimated and to be got.(accompanying drawing 2, square frame 1)
2. the maximum amount of testing in the definition second level is N
t, i.e. the progression of second level shift register (accompanying drawing 2, square frame 2) in the accompanying drawing 1.
3. the first order be multiply by the threshold value of COEFFICIENT K as first order judgement with reference to the output R of matched filter, with all N of the second level
tThe whole zero clearings of level shift register.When the output X of the straight-through matched filter of the first order surpasses threshold value, entered for the 4th step, otherwise repeated for the 3rd step (accompanying drawing 2, square frame 3).
4. the second level begins to start.The output X of the straight-through matched filter of the first order is as partial input, and the first order is multiplied by channel estimation coefficient as biasing D (accompanying drawing 2, square frame 4) with reference to the output R of matched filter.
5. with the second level adder output S of quick point device
KCompare with thresholding B, if S
K＞B entered for the 6th step; Otherwise return for the 3rd step (accompanying drawing 2, square frame 5).
6. shift register displacement in the second level once if second level shift register is full, confirms then to have realized that synchronously, second level checking procedure finishes, and sets up synchronously.If second level shift register is discontented, got back to for the 4th step (accompanying drawing 2, square frame 6).
By the above course of work as seen, decide according to the result who detects each time required detection time the second level, so be variable detection time (or dead time).
Claims (4)
1. two-stage direct sequence spread spectrum/CDMA communication catching circuits device is characterized in that:
(1) this circuit arrangement is made of the two-stage cascade, and the first order is a matched filter, and the second level is a quick point device, and the latter is in order to realize the integration to first order output;
(2) matched filter of the first order adopts the syndeton of band reference arm, be described matched filter by straight-through matched filter with form with reference to matched filter, straight-through matched filter provides the baseband signal of channel, provides estimation to channel disturbance with reference to matched filter;
(3) partial quick point device is the simplification to matched filter, can think to be equivalent to the matched filter of local reference signal for complete " 1 ".
2. according to the two-stage direct sequence spread spectrum/CDMA communication catching circuits device of claim 1, it is characterized in that: partial quick point device realizes that by shift register and adder it is the distressed structure of matched filter.
3. the two poles of the earth direct sequence spread spectrum/CDMA communication method for catching is characterized in that carrying out work according to following flow process:
(1) definition second level decision threshold is B;
(2) the maximum amount of testing in the definition second level is Nt;
(3) first order be multiply by the threshold value of COEFFICIENT K as first order judgement with reference to the output R of matched filter, with the whole zero clearings of all Nt level shift registers of the second level.When the output X of the straight-through matched filter of the first order surpasses threshold value, entered for the 4th step, otherwise repeated for the 3rd step;
(4) second level begins to start.The output X of the straight-through matched filter of the first order is as partial input, and the first order is multiplied by channel estimation coefficient B as biasing D with reference to the output R of matched filter;
(5) output Sk and the thresholding B with second level adder compares, if Sk＞B entered for the 6th step, otherwise returns for the 3rd step;
(6) shift register displacement in the second level once if second level shift register is full, confirms then to have realized that synchronously, second level checking procedure finishes, and sets up synchronously, if second level shift register is discontented, gets back to for the 4th step.
4. according to the two poles of the earth direct sequence spread spectrum/CDMA communication method for catching of claim 3, it is characterized in that described second level decision threshold can be definite value or adopts adaptive approach channel is estimated and to be obtained.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1116477A (en) * | 1993-10-14 | 1996-02-07 | Ntt移动通信网株式会社 | Correlation detector and communication apparatus |
| EP0838910A2 (en) * | 1996-10-23 | 1998-04-29 | Ntt Mobile Communications Network Inc. | Acquisition scheme and receiver for an asynchronous DS-CDMA cellular communication system |
| GB2318952A (en) * | 1996-10-29 | 1998-05-06 | Motorola Inc | Fast pilot channel acquisition using a matched filter in a CDMA radiotelephone |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1116477A (en) * | 1993-10-14 | 1996-02-07 | Ntt移动通信网株式会社 | Correlation detector and communication apparatus |
| EP0838910A2 (en) * | 1996-10-23 | 1998-04-29 | Ntt Mobile Communications Network Inc. | Acquisition scheme and receiver for an asynchronous DS-CDMA cellular communication system |
| GB2318952A (en) * | 1996-10-29 | 1998-05-06 | Motorola Inc | Fast pilot channel acquisition using a matched filter in a CDMA radiotelephone |
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