CN106559071A - A kind of phaselocked loop automatic calibrating method - Google Patents
A kind of phaselocked loop automatic calibrating method Download PDFInfo
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- CN106559071A CN106559071A CN201611035563.XA CN201611035563A CN106559071A CN 106559071 A CN106559071 A CN 106559071A CN 201611035563 A CN201611035563 A CN 201611035563A CN 106559071 A CN106559071 A CN 106559071A
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- phaselocked loop
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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Abstract
The present invention proposes a kind of phaselocked loop automatic calibrating method, and phaselocked loop includes the preset DA of phase discriminator, integrating circuit, switch, VCO, frequency divider, FPGA and VCO, first by frequency divider output frequency, phaselocked loop slightly calibrated, and phaselocked loop is successfully pinned；Then accurate calibration is carried out to phaselocked loop by phaselocked loop integrated error voltage.The phaselocked loop automatic calibrating method of the present invention realizes automatic calibration accurately and fast in the situation that need not be manually done any debugging.
Description
Technical field
The present invention relates to technical field of measurement and test, more particularly to a kind of phaselocked loop automatic calibrating method.
Background technology
Phaselocked loop is commonly used due to its outstanding performance, relative simplicity and low cost.With the progress of technology
With the needs for using, while single-side belt noise is optimized, using the frequency more and more higher of phaselocked loop VCO.
Due to the performance of phaselocked loop, its preset voltage is non-linear in its operating frequency, the preset calibration of conventional phase locked loops
Using manual calibration very elapsed time.The phaselocked loop of such as 3GHz～6GHz, needs preset at interval of 100MHz settings one
Value, a phaselocked loop is accomplished by 31 parameters, if each parameter needs 30s, whole preset debugging is accomplished by 930s, and debugging is very
It is time-consuming.And when production in enormous quantities in enormous quantities, as indivedual phase-locked loop performances are poor, phaselocked loop can be caused to occur in high/low temperature
Losing lock, this is accomplished by arranging more parameters, and so arranging more needs the time.
Typical principle of phase lock loop figure is as shown in figure 1, phaselocked loop is by phase discriminator, integrating circuit, switch, VCO (VCOs
Device), frequency divider, the preset DA of FPGA and VCO (digital to analog converter) constitute.First, when phaselocked loop is started working, sent by industrial computer
Preset parameter gives VCO preset DA, then send frequency dividing ratio to frequency divider, then controls phase discriminator, closes finally by switch 1, entirely
Phaselocked loop completes to lock phase.Wherein, the number that send of the preset DA of VCO is the preset parameter for needing manual debugging phaselocked loop.
The debugging flow process of phaselocked loop shown in Fig. 1 as shown in Fig. 2 as shown in Figure 2, after whole machine is started shooting for the first time, industrial computer
Phaselocked loop FPGA is given by the initial preset software parameter numbers of phaselocked loop VCO by step 1, the numerical value that phaselocked loop FPGA is received is through step
Rapid 2 give the preset DA of VCO, and the preset DA of VCO give VCO power transmission pressures through step 3.
When needing debugging phaselocked loop VCO preset, phaselocked loop is connected into audiofrequency spectrometer, opens phaselocked loop manually by step 4
Ring, debugs present frequency point manually, through step 5, makes VCO output frequencies be close to phaselocked loop arranges value, then preserves.
Assume phase-locked loop frequency from 3GHz～6GHz when because VCO's is non-linear, need every 100MHz arrange one it is soft
Parameter value, is required for through manual debugging step every value, if VCO is linearly very poor, needs to be changed into interval from 100MHz
50MHz is less.
When phaselocked loop switch operating frequency, industrial computer is needed to calculate the corresponding VCO preset parameter values of present frequency point, than
Such as ongoing frequency 3.01GHz, it is 3GHz and 3.1GHz to arrange software parameter number, and needs are according to software parameter the numerical value D1 and 3.1GHz of 3GHz
Being calculated, acquiescence is linear, the software parameter numerical value of 3.01GHz for software parameter numerical value D2：
VCO preset parameter values are changed into into voltage-drop loading on VCO through above-mentioned steps 1, step 2, step 3, whole machine lock is made
Phase.
Conventional solution has as a drawback that：
(1), as manual debugging software parameter number is limited, the Frequency point in the middle of each two software parameter number needs acquiescence linearly to count
Calculate, prior art needs phaselocked loop to have wider lock phase bandwidth, and otherwise high/low temperature is easy to losing lock；
(2), need manually to carry out the preset debugging of VCO.
The content of the invention
To solve above-mentioned deficiency of the prior art, the present invention proposes a kind of phaselocked loop automatic calibrating method.
The technical scheme is that what is be achieved in that：
A kind of phaselocked loop automatic calibrating method, the phaselocked loop include phase discriminator, integrating circuit, VCO, frequency divider, FPGA and
The preset DA of VCO, first by frequency divider output frequency, are slightly calibrated to phaselocked loop, phaselocked loop is successfully pinned；Then pass through
Phaselocked loop integrated error voltage carries out smart calibration to phaselocked loop.
Alternatively, the thick calibration process is comprised the following steps：
Initial value is given FPGA by step 1, industrial computer；
Initial value is given the preset DA of VCO by step 2, phaselocked loop；
The preset DA of step 3, VCO produces voltage and is added on VCO；
Step 4, industrial computer indicate to judge whether phaselocked loop pins by the losing lock of phaselocked loop；
If step 5, pinning, industrial computer store current software parameter numerical value；By phaselocked loop open loop if not pinning；
If step 6, step 5 are by phaselocked loop open loop, phase demodulation clock of the frequency-dividing clock that frequency divider is exported with phaselocked loop
It is compared；
Step 7, if frequency-dividing clock is more than the phase demodulation clock of phaselocked loop, industrial computer reduces the preset software parameter numbers of VCO；If point
Phase demodulation clock of the frequency clock less than phaselocked loop, the preset software parameter numbers of industrial computer increase VCO；
Step 8, by phaselocked loop closed loop, judge whether phaselocked loop pins, if pin if store software parameter numerical value, then calibrate
The software parameter number of next Frequency point；If can not pin, step 6 and step 7 are continued executing with, till pinning.
Alternatively, the smart calibration process is as follows：
Little ring of numbers closed loop, tests current phaselocked loop integrated error voltage, if phaselocked loop integrated error voltage is less than error
Threshold value, then store current software parameter number, if phaselocked loop integrated error voltage is more than error threshold, is missed according to current phaselocked loop integration
Potential difference, judges soft parameter variation range, changes software parameter number, until phaselocked loop integrated error voltage is less than error threshold.
The invention has the beneficial effects as follows：
(1) preset to VCO manually need not calibrate；
(2) VCO preset parameters are more quick, accurate, prevent high/low temperature losing lock.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is typical principle of phase lock loop figure；
Preset parameter flow charts of the Fig. 2 for manual debugging phaselocked loop；
Fig. 3 is the flow chart of the thick calibration process of automatic calibrating method of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
The automatic calibrating method of the present invention, using typical phase locked loop circuit as shown in Figure 1, is exported by frequency divider first
Frequency, carries out preliminary calibration to phaselocked loop, phaselocked loop is successfully pinned；Then by phaselocked loop integrated error voltage to lock
Phase ring carries out accurate calibration.The present invention need not debug manually phaselocked loop it is preset in the case of calibrated automatically, calibrate
As a result it is very accurate.
The phaselocked loop automatic calibrating method of the present invention is described in detail with reference to Figure of description.
The phaselocked loop automatic calibrating method of the present invention is divided into thick calibration process and smart calibration process, as shown in figure 3, thick calibrate
Process is comprised the following steps：
Initial value is given FPGA by step 1, industrial computer, and (acquiescence industrial computer is automatically automatic to frequency divider, phase discriminator and switch
Configuration).
Initial value is given the preset DA of VCO by step 2, phaselocked loop.
The preset DA of step 3, VCO produces voltage and is added on VCO.
Step 4, industrial computer indicate to judge whether phaselocked loop pins by the losing lock of phaselocked loop.
If step 5, pinning, industrial computer store current software parameter numerical value；If do not pin needed phaselocked loop open loop.
If step 6, step 5 by phaselocked loop open loop, need the frequency-dividing clock that exports frequency divider with the phase demodulation of phaselocked loop
Clock is compared.
If step 7, frequency-dividing clock are more than the phase demodulation clock of phaselocked loop, industrial computer reduces the preset software parameter numbers of VCO；If point
Phase demodulation clock of the frequency clock less than phaselocked loop, the preset software parameter numbers of industrial computer increase VCO.
In Fig. 1, phase demodulation clock is reference clock 1, and the reference clock of FPGA is reference clock 2, if frequency-dividing clock is more than lock
The phase demodulation clock of phase ring, with the reference clock of FPGA as clock come to frequency division counter, so that it may judge current frequency size.It is false
If reference clock 2 is 100MHz, phase demodulation frequency is 50MHz, in FPGA, arranges clock each rising edge and is counted, DANGSHEN
Examine the i1 of clock 2 from 0 count down to 100 when, in Fig. 3, frequency-dividing clock i2 should count down to 50 from 0, if i2 ＜ 50, i2* frequency dividing
Than being current VCO output frequencies, if very big with arranging frequency distance, according to the data that VCO is provided, it is assumed that voltage Vref
Change VCO frequencyVCO needs to change voltageAccording to per the change of software parameter number
VCO preset voltage values calculate the parameter value for needing to change；If i2 ＞ 50, software parameter numerical value can be changed in the same manner；When i2* frequency dividing ratios
When being close to phaselocked loop setting frequency, DA values should increase and decrease one every time.
Step 8, by phaselocked loop closed loop, judge whether phaselocked loop pins, if pin if store software parameter numerical value, then calibrate
The software parameter number of next Frequency point；If can not pin, step 6 and step 7 are continued executing with, till pinning.In order to anti-
Only coarse adjustment interval can be diminished by accurate adjustment losing lock, such as mono- point of 50MHz.
On the basis of above-mentioned thick calibration process, the smart calibration process of phaselocked loop automatic calibrating method of the present invention is as follows：
Little ring of numbers closed loop, tests current phaselocked loop integrated error voltage, if voltage less than error threshold (for example ±
0.1V), then current software parameter number is stored, if greater than error threshold (such as ± 0.1V), according to current voltage, judges that software parameter number becomes
Change scope (having already known each soft parameter change error voltage value), change software parameter number, until voltage is less than error threshold (example
Such as ± 0.1V).As this process is very quick, a calibration point can be arranged with every 10MHz.
It is that the preset calibrations of VCO are carried out in the case of arranging manually that the purpose of thick calibration is, makes phaselocked loop success
Pin；Essence calibration purpose be it is more time-consuming, more accurately.
The phaselocked loop automatic calibrating method of the present invention realizes lock phase by counting to the fractional frequency signal that frequency divider is exported
Ring automatic locking in the case of losing lock；In the case of by pinning to phaselocked loop, the automatic calibration of the preset software parameter numbers of VCO, makes VCO
Preset parameter is finer, and calibration process is very quick.
Presently preferred embodiments of the present invention is the foregoing is only, not to limit the present invention, all essences in the present invention
Within god and principle, any modification, equivalent substitution and improvements made etc. should be included within the scope of the present invention.
Claims (3)
1. a kind of phaselocked loop automatic calibrating method, the phaselocked loop include phase discriminator, integrating circuit, VCO, frequency divider, FPGA and VCO
Preset DA, it is characterised in that first by frequency divider output frequency, slightly calibrated to phaselocked loop, makes phaselocked loop successfully pin；
Then smart calibration is carried out to phaselocked loop by phaselocked loop integrated error voltage.
2. a kind of phaselocked loop automatic calibrating method as claimed in claim 1, it is characterised in that the thick calibration process include with
Lower step：
Initial value is given FPGA by step 1, industrial computer；
Initial value is given the preset DA of VCO by step 2, phaselocked loop；
The preset DA of step 3, VCO produces voltage and is added on VCO；
Step 4, industrial computer indicate to judge whether phaselocked loop pins by the losing lock of phaselocked loop；
If step 5, pinning, industrial computer store current software parameter numerical value；By phaselocked loop open loop if not pinning；
If the frequency-dividing clock that frequency divider is exported is carried out by step 6, step 5 by phaselocked loop open loop with the phase demodulation clock of phaselocked loop
Relatively；
Step 7, if frequency-dividing clock is more than the phase demodulation clock of phaselocked loop, industrial computer reduces the preset software parameter numbers of VCO；If during frequency dividing
Phase demodulation clock of the clock less than phaselocked loop, the preset software parameter numbers of industrial computer increase VCO；
Step 8, by phaselocked loop closed loop, judge whether phaselocked loop pins, if pin if store software parameter numerical value, then calibrate next
The software parameter number of individual Frequency point；If can not pin, step 6 and step 7 are continued executing with, till pinning.
3. a kind of phaselocked loop automatic calibrating method as claimed in claim 2, it is characterised in that the smart calibration process is as follows：
Little ring of numbers closed loop, tests current phaselocked loop integrated error voltage, if phaselocked loop integrated error voltage is less than error threshold,
Current software parameter number is stored then, if phaselocked loop integrated error voltage is more than error threshold, according to current phaselocked loop integral error electricity
Pressure, judges soft parameter variation range, changes software parameter number, until phaselocked loop integrated error voltage is less than error threshold.
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| CN201611035563.XA CN106559071A (en) | 2016-11-15 | 2016-11-15 | A kind of phaselocked loop automatic calibrating method |
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| CN201611035563.XA CN106559071A (en) | 2016-11-15 | 2016-11-15 | A kind of phaselocked loop automatic calibrating method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108880540A (en) * | 2018-06-08 | 2018-11-23 | 中国电子科技集团公司第四十研究所 | A method of improving phase-locked loop frequency switching time |
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|---|---|---|---|---|
| US20070247234A1 (en) * | 2006-04-04 | 2007-10-25 | Honeywell International Inc. | Method for mitigating single event effects in a phase locked loop |
| CN102291131A (en) * | 2006-03-31 | 2011-12-21 | 日本电波工业株式会社 | Frequency synthesizer |
| CN102739246A (en) * | 2011-04-01 | 2012-10-17 | 联发科技（新加坡）私人有限公司 | Clock generating apparatus and frequency calibrating method of the clock generating apparatus |
| CN102859879A (en) * | 2010-05-13 | 2013-01-02 | 华为技术有限公司 | System and method for calibrating output frequency in phase locked loop |
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2016
- 2016-11-15 CN CN201611035563.XA patent/CN106559071A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102291131A (en) * | 2006-03-31 | 2011-12-21 | 日本电波工业株式会社 | Frequency synthesizer |
| US20070247234A1 (en) * | 2006-04-04 | 2007-10-25 | Honeywell International Inc. | Method for mitigating single event effects in a phase locked loop |
| CN102859879A (en) * | 2010-05-13 | 2013-01-02 | 华为技术有限公司 | System and method for calibrating output frequency in phase locked loop |
| CN102739246A (en) * | 2011-04-01 | 2012-10-17 | 联发科技（新加坡）私人有限公司 | Clock generating apparatus and frequency calibrating method of the clock generating apparatus |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108880540A (en) * | 2018-06-08 | 2018-11-23 | 中国电子科技集团公司第四十研究所 | A method of improving phase-locked loop frequency switching time |
| CN108880540B (en) * | 2018-06-08 | 2022-03-15 | 中国电子科技集团公司第四十一研究所 | Method for improving frequency switching time of phase-locked loop |
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Application publication date: 20170405 |