CN106558492A - A kind of manufacture method of fin and semiconductor device - Google Patents
A kind of manufacture method of fin and semiconductor device Download PDFInfo
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- CN106558492A CN106558492A CN201510624492.6A CN201510624492A CN106558492A CN 106558492 A CN106558492 A CN 106558492A CN 201510624492 A CN201510624492 A CN 201510624492A CN 106558492 A CN106558492 A CN 106558492A
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 230000003647 oxidation Effects 0.000 claims abstract description 29
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 29
- 238000005516 engineering process Methods 0.000 claims abstract description 27
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 101
- 239000000463 material Substances 0.000 description 17
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- 229910052581 Si3N4 Inorganic materials 0.000 description 5
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- 230000000694 effects Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
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- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
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- 229920005591 polysilicon Polymers 0.000 description 3
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- 238000010276 construction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of manufacture method of fin, including：Substrate is provided；Initial graph pattern layer is formed on substrate, the initial graph pattern layer is semi-conducting material, and carries out oxidation technology, initial oxide layer is formed on the side wall of initial graph pattern layer, the initial graph pattern layer for being formed with initial oxide layer is first structure；The (n+1)th structure is formed, including：Form the n-th side wall on the side wall of the n-th structure, the n-th side wall is semi-conducting material, and carries out oxidation technology, on the side wall of the n-th side wall forms the n-th oxide layer, the n-th side wall for being formed with the n-th oxide layer is the (n+1)th structure, n from 1 to N, N >=1 and be positive integer；Initial graph pattern layer is removed, and initial oxide layer and the first oxide layer are to the n-th oxide layer；First side wall is transferred in substrate to the pattern of the n-th side wall, to form fin.The method forms the mask of highdensity fin, and then the integrated level of raising fin, meanwhile, the fin of acquisition has more preferable pattern.
Description
Technical field
The present invention relates to the system of semiconductor device and manufacture field, more particularly to a kind of fin and semiconductor device
Make method.
Background technology
Highly integrated with semiconductor device, MOSFET channel length constantly shortens, it is a series of
In the long raceway groove models of MOSFET, negligible effect becomes more significantly, or even becomes impact device
The leading factor of energy, this phenomenon are referred to as short-channel effect.Short-channel effect can deteriorate the electricity of device
Performance, such as causes threshold voltage of the grid to decline, power consumption increases and signal to noise ratio is the problems such as decline.
Fully- depleted (Fully-Depleted) nonplanar device, such as FinFET (fin FET),
It is the ideal chose of 20 nanometers and following technology generation.As FinFET can be realized in extremely short raceway groove
The effective control of short-channel effect, substantially reduces the serious drain phenomenon in raceway groove, the S factors during reduction,
Device operating voltages are reduced, realizes that low pressure and low consumption is operated.Meanwhile, the conducting channel of FinFET can be provided
Higher conductive current, dramatically increases device and circuit performance.
In the manufacturing process of FinFET, fin is formed generally by etched substrate, however, being subject to photoetching
The restriction of technology, it is difficult to the high fin of integrated level is formed in FinFET techniques, it is difficult to further improve device
Integrated level.
The content of the invention
In view of this, it is an object of the invention to provide the manufacture method of a kind of fin and semiconductor device, carries
The integrated level of high fin.
For achieving the above object, the present invention has following technical scheme：
A kind of manufacture method of fin, including：
Substrate is provided；
Initial graph pattern layer is formed on substrate, the initial graph pattern layer is semi-conducting material, and carries out oxidation work
Skill, to form initial oxide layer on the side wall of initial graph pattern layer, is formed with the initial graph of initial oxide layer
Pattern layer is first structure；
The (n+1)th structure is formed, including：The n-th side wall, the n-th side wall are formed on the side wall of the n-th structure
For semi-conducting material, and oxidation technology is carried out, the n-th oxide layer, shape are formed on the side wall of the n-th side wall
Be the (n+1)th structure into the n-th side wall for having the n-th oxide layer, n from 1 to N, N >=1 and be positive integer；
Initial graph pattern layer is removed, and initial oxide layer and the first oxide layer are to the n-th oxide layer；
First side wall is transferred in substrate to the pattern of the n-th side wall, to form fin.
Optionally, before initial graph pattern layer is formed, also include：The first hard mask layer is deposited on substrate；
First side wall is transferred in substrate to the pattern of the n-th side wall, is included the step of to form fin：
Perform etching with the first side wall to the n-th side wall to shelter, form the first hard mask layer of patterning；
The first side wall is removed to the n-th side wall；
It is to shelter the etching for carrying out substrate with the first hard mask layer, to form fin；
The first side wall is removed to the n-th side wall.
Optionally, the initial graph pattern layer and the first side wall have identical semi-conducting material.
Optionally, the semi-conducting material is polysilicon or non-crystalline silicon.
Optionally, before carrying out oxidation technology, the thickness range of the n-th side wall is 10～100nm.
Optionally, the thickness range of the n-th oxide layer is 5～50nm.
Additionally, present invention also offers a kind of manufacture method of semiconductor device, using any of the above-described method
The fin of formation is forming fin formula field effect transistor device.
The manufacture method of fin provided in an embodiment of the present invention and semiconductor device, forms the first of semi-conducting material
Beginning patterned layer simultaneously after being aoxidized, repeatedly forms the side wall of semi-conducting material, and carry out oxygen on the wall of side
Chemical industry skill, afterwards, after removing initial graph pattern layer and oxide layer, remaining side wall is mask, carries out fin
Transfer, so, there is smooth sidewall profile by the side wall mask that oxidation technology is formed, by this
Side wall pattern carries out the transfer of fin, and the fin of acquisition has more preferable pattern, meanwhile, by the thickness of side wall
The size of easily controllable fin, by the spacing between the easily controllable fin of oxidation technology, so as to be easy to be formed
The mask of highdensity fin, and then improve the integrated level of fin.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to reality
Apply accompanying drawing to be used needed for example or description of the prior art to be briefly described, it should be apparent that, below
Accompanying drawing in description is some embodiments of the present invention, for those of ordinary skill in the art, not
On the premise of paying creative work, can be with according to these other accompanying drawings of accompanying drawings acquisition.
Fig. 1 shows the manufacture method flow chart of fin according to embodiments of the present invention；
Fig. 2-Figure 14 show manufacture method according to embodiments of the present invention formed fin each during cut open
Face structural representation.
Specific embodiment
It is understandable to enable the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
Many details are elaborated in the following description in order to fully understand the present invention, but this
Bright to be different from alternate manner described here implementing using other, those skilled in the art can be with
Similar popularization, therefore the present invention are done in the case of without prejudice to intension of the present invention not by following public concrete
The restriction of embodiment.
Secondly, the present invention is described in detail with reference to schematic diagram, when the embodiment of the present invention is described in detail, is just
In explanation, represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and the signal
It is example to scheme, and its here should not limit the scope of protection of the invention.Additionally, should wrap in actual fabrication
Three-dimensional space containing length, width and depth.
As the description of background technology, in order to improve the density of fin, and then the integrated level of raising device, this
Invention proposes a kind of manufacture method of fin, and with reference to shown in Fig. 1, the method includes：
Substrate is provided；
Initial graph pattern layer is formed on substrate, the initial graph pattern layer is semi-conducting material, and carries out oxidation work
Skill, to form initial oxide layer on the surface of initial graph pattern layer, is formed with the initial pattern of initial oxide layer
Layer is first structure；
The (n+1)th structure is formed, including：The n-th side wall, the n-th side wall are formed on the side wall of the n-th structure
For semi-conducting material, and oxidation technology is carried out, the n-th oxide layer, shape are formed on the surface of the n-th side wall
Be the (n+1)th structure into the n-th side wall for having the n-th oxide layer, n from 1 to N, N >=1 and be positive integer；
Remove initial graph pattern layer, and initial oxide layer and the n-th oxide layer；
The pattern of the n-th side wall is transferred in substrate, to form fin.
In the method for the invention, initial graph pattern layer be semi-conducting material, by oxidation after, initial
Oxide layer is formed on the side wall of patterned layer, and then, semi-conducting material is formed in the side wall of initial graph pattern layer
Side wall, and aoxidized, oxide layer is defined on the side wall side wall of semi-conducting material, repeatedly shape
Into the side wall of semi-conducting material and the step of aoxidized, then, initial graph pattern layer and all of oxygen are removed
Change layer, remaining side wall can form size less pattern by side wall technique as the pattern for forming fin,
Meanwhile, after oxidation technology, side wall pattern can be caused more to smooth, meanwhile, by oxygen can be passed through
Change the spacing between the THICKNESS CONTROL fin of layer, so as to be easy to be formed covering for high density and the smooth fin of pattern
Film, and then the integrated level of fin is improved, meanwhile, form high-quality fin.The manufacture method can be using existing
The manufacturing process of some cmos devices need not be subject to completing the manufacture of small size, the fin of high integration
The restriction of photoetching technique, process is simple and feasibility are high.
In order to be better understood from technical scheme and technique effect, below with reference to specific flow process
Schematic diagram Fig. 1 is described in detail to specific embodiment.
First, in step S01, there is provided substrate 100, with reference to shown in Fig. 2.
In embodiments of the present invention, the substrate be Semiconductor substrate, can for Si substrates, Ge substrates,
SiGe substrate, SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator,
Germanium On Insulator) etc..In other embodiments, the Semiconductor substrate can also be bag
The substrate of other elements quasiconductor or compound semiconductor, such as GaAs, InP or SiC etc. are included, also
Can be laminated construction, such as Si/SiGe etc. can be with other epitaxial structures, and such as SGOI is (absolutely
Germanium silicon on edge body) etc..In the present embodiment, the substrate is body silicon substrate.
Then, in step S02, initial graph pattern layer 110, the initial graph pattern layer 110 are formed on the substrate 100
For semi-conducting material, and oxidation technology is carried out, initial oxide layer 114, shape are formed in initial graph pattern layer 110
It is first structure into the initial graph pattern layer 110 for having initial oxide layer 447, with reference to shown in Fig. 4.
In the present embodiment, before the processing technique of first structure is carried out, first formed on the substrate 100
First hard mask layer, first hard mask layer for by the transfer of the pattern of the fin being subsequently formed, while will
Substrate surface is covered, to protect to substrate.First hard mask layer can be monolayer or laminated construction,
Suitable material can be selected according to the Etch selectivity between subsequent material to form the first hard mask
Layer, for example, can be silicon oxide, silicon nitride, silicon oxynitride or their lamination, in the present embodiment, ginseng
Examine shown in Fig. 2, first hard mask layer is the lamination of oxygen pad layer 102 and silicon nitride layer 104, pads oxygen
Layer 102 can reduce stress between silicon nitride and silicon substrate.
Then, form first structure.Specifically, first, initial pattern material 106, the initial material are deposited
Cap rock 108 can also be further formed on the bed of material, as shown in Fig. 2 the initial pattern material 106 is half
Conductor material, initial pattern material can for example be polysilicon, non-crystalline silicon or other suitable quasiconductor materials
Material, in the present embodiment, initial pattern material is polysilicon, and the cap rock can be silicon nitride or nitrogen oxidation
Silicon or their lamination, for protecting initial pattern, in the present embodiment, the cap rock 108 is silicon nitride.
Then, the photosensitive etching agent of spin coating on the cap rock, and by cap rock 108 and initial pattern material 106
Patterning, so as to form initial graph pattern layer 110, initial graph pattern layer overlying is stamped cap rock 112, then, goes
Except photosensitive etching agent, as shown in figure 3, the width range of the initial graph pattern layer 110 can be 60～500nm,
The initial graph pattern layer 110 determines the spacing between every group of fin substantially.
Then, oxidation technology is carried out, can is dry oxygen or wet oxygen technique, in the present embodiment, can adopt
Thermal oxidation technology, so, defines initial oxide layer 114 on 110 exposed side wall of initial graph pattern layer,
After oxidation technology, the side wall of initial graph pattern layer 110 is more smoothed, and is put down beneficial to pattern is subsequently formed
The pattern of sliding fin, can form the oxide layer of desired thickness by the time of control oxidation technology.For
It is easy to description, forms the initial graph pattern layer 110 after initial oxide layer 114 and be denoted as first structure.
Then, in step S03, the (n+1)th structure is formed, including：Is formed on the side wall of the n-th structure
N side walls 116,120,124, the n-th side wall 116,120,124 is semi-conducting material, and is aoxidized
Technique, forms the n-th oxide layer 118,122,126 on the side wall of the n-th side wall 116,120,124,
The n-th side wall for being formed with the n-th oxide layer is the (n+1)th structure, n from 1 to N, N >=1 and be positive integer,
With reference to shown in Fig. 5-Fig. 8.
Form multiple sidewall structure in this step, can be according to device it needs to be determined that the side wall of formation
The number of times of structure, in the present embodiment, is illustrated as a example by forming 3 sidewall structures, namely N is
3.It is understood that the number of times of N is merely illustrative herein, the present invention is not limited to this, can be with root
According to specific it needs to be determined that forming the number of times of sidewall structure.
First, the formation of the second structure is carried out, specifically, first, is formed on the side wall of first structure
First side wall 116, the first side wall 116 is semi-conducting material, and the semi-conducting material of the first side wall 116 can be with
Select and initial graph pattern layer identical semi-conducting material or different semi-conducting materials, in the present embodiment, the
One side wall 116 is selected and initial graph pattern layer identical semi-conducting material, is all polycrystalline silicon material, Ke Yitong
The first spacer material of deposition is crossed, the thickness of the first spacer material of deposition can be 10～100nm, then lead to
RIE (reactive ion etching) is crossed, so that the first side wall 116 is formed on the side wall of first structure, such as
Shown in Fig. 5.Then, oxidation technology is carried out, can is dry oxygen or wet oxygen technique, in the present embodiment, can
To adopt thermal oxidation technology, after carrying out thermal oxide, in 116 exposed side wall of the first side wall and upper table
First oxide layer 118 is defined on face all, as shown in fig. 6, the thickness of the first oxide layer 118 can pass through
The time of control thermal oxidation technology is adjusted, and the thickness of the first oxide layer 118 can be 5～50nm, so,
It is formed on the wall of side being formed with the first side wall 116 of the first oxide layer 118, with the first oxide layer 118
The first side wall 116 be denoted as the second structure.
Then, the formation of the 3rd structure is carried out, with the formation process of the second structure, first, in the second knot
The second side wall 120 is formed on the side wall of structure, the second side wall 120 is semi-conducting material, the second side wall 120
Semi-conducting material can be selected and the first side wall identical semi-conducting material, in the present embodiment, be all polycrystalline
Silicon materials, can be by depositing the second spacer material, the thickness of the second spacer material of deposition and the first side
Wall thickness is identical, then by RIE (reactive ion etching), so as to the shape on the side wall of the second structure
Into the second side wall 120, as shown in Figure 7.Then, oxidation technology is carried out, can is dry oxygen or wet oxygen technique,
In the present embodiment, thermal oxidation technology can be adopted, after carrying out thermal oxide, is exposed in the second side wall 120
Side wall and upper surface on all define the second oxide layer 122, as shown in figure 8, the second oxide layer 122
Thickness can be by controlling the time of thermal oxidation technology adjusting, the thickness of the second oxide layer 122 and the
One oxidated layer thickness is identical, so, is formed on the wall of side being formed with the second side of the second oxide layer 122
Wall 120, the second side wall 120 with the second oxide layer 122 are denoted as the 3rd structure.
Then, the formation of the 4th structure is carried out, with the formation process of the 3rd structure, first, in the 3rd knot
The 3rd side wall 122 is formed on the side wall of structure, concrete grammar can be identical with the method for forming the second side wall, and
Afterwards, oxidation technology is carried out, the 3rd oxide layer 126 is formed, as shown in figure 8, concrete grammar can be with formation
The method of the second oxide layer is identical, so, is formed on the wall of side being formed with the of the 3rd oxide layer 126
Three side walls 122, the 3rd side wall 122 with the 3rd oxide layer 126 are denoted as the 4th structure.
In the present embodiment, initial graph pattern layer and the first side wall to the 3rd side wall all employ identical half
Conductor material, is so easy to the selection and control of technique, it is, of course, understood that they can also
Using different semi-conducting materials.
In this step, the side wall of semi-conducting material is defined, and then is aoxidized, in semi-conducting material
Side wall side wall on form oxide layer, the region covered under side wall is the region formed by fin, so,
After oxidation, the thickness of side wall determines the size of fin substantially, and the thickness of oxide layer is determined between fin substantially
Spacing, by this technique, be on the one hand easy to control the spacing between the size and fin of fin, need not
Limited by photoetching technique, the fin of high integration can be just realized using traditional technique, on the other hand,
After oxidation technology so that the surface of side wall more smooths, as the pattern of fin, pattern is advantageously formed more
Good fin.
Then, in step S04, initial graph pattern layer 110, and initial oxide layer 114 and the first oxygen are removed
Change 118 to the n-th oxide layer 126 of layer, with reference to shown in Figure 11.
Specifically, it is possible, firstly, to utilize TMAH wet etchings selectively to remove initial graph pattern layer 110
On cap rock 112, as shown in Figure 9.Then, it is possible to use dry or wet etch selectivities remove initial
Patterned layer 110, as shown in Figure 10.Then, by all of oxide layer 114,118,122,126, i.e.,
Initial oxide layer 114, the first oxide layer 118, the second oxide layer 122 and the 3rd oxide layer 126, select
Property remove, only retain the first side wall 116, the second side wall 120 and the 3rd side wall 124, these side walls will make
To form the pattern of fin.
Then, in step S04, the pattern of 116 to the n-th side wall 124 of the first side wall is transferred to into substrate
In 100, to form fin 130, with reference to shown in Figure 14.
The pattern of 116 to the n-th side wall 124 of the first side wall can be transferred to by substrate using suitable technique
In 100, in the present embodiment, first, perform etching with 116 to the n-th side wall 124 of the first side wall to shelter,
The first hard mask layer 104,102 of patterning is formed, the pattern of side wall is transferred in the first hard mask layer,
As shown in figure 12.Then, 116 to the n-th side wall 124 of the first side wall is removed, as shown in figure 13, and with
First hard mask layer 104,102 carries out the etching of substrate 100, so as to form fin 130, most to shelter
Afterwards, the first hard mask layer 104,102 is removed, as shown in figure 14.
So far, the structure of the fin of the embodiment of the present invention is defined in the substrate.Then can on the fin after
It is continuous to form semiconductor device, i.e. fin formula field effect transistor device, front grid technique or rear grid work can be adopted
Skill, isolation, grid, source and drain and contact between formation fin etc., so as to form fin field effect crystal
Pipe.
The above is only the preferred embodiment of the present invention, although the present invention is disclosed with preferred embodiment
As above, however be not limited to the present invention.Any those of ordinary skill in the art, without departing from this
Under inventive technique scheme ambit, all using the methods and techniques content of the disclosure above to skill of the present invention
Art scheme makes many possible variations and modification, or the Equivalent embodiments for being revised as equivalent variations.Therefore,
Every content without departing from technical solution of the present invention, according to the technical spirit of the present invention to above example institute
Any simple modification, equivalent variations and the modification made, still falls within the model of technical solution of the present invention protection
In enclosing.
Claims (7)
1. a kind of manufacture method of fin, it is characterised in that include：
Substrate is provided；
Initial graph pattern layer is formed on substrate, the initial graph pattern layer is semi-conducting material, and carries out oxidation work
Skill, to form initial oxide layer on the side wall of initial graph pattern layer, is formed with the initial graph of initial oxide layer
Pattern layer is first structure；
The (n+1)th structure is formed, including：The n-th side wall, the n-th side wall are formed on the side wall of the n-th structure
For semi-conducting material, and oxidation technology is carried out, the n-th oxide layer, shape are formed on the side wall of the n-th side wall
Be the (n+1)th structure into the n-th side wall for having the n-th oxide layer, n from 1 to N, N >=1 and be positive integer；
Initial graph pattern layer is removed, and initial oxide layer and the first oxide layer are to the n-th oxide layer；
First side wall is transferred in substrate to the pattern of the n-th side wall, to form fin.
2. manufacture method according to claim 1, it is characterised in that formed initial graph pattern layer it
Before, also include：The first hard mask layer is deposited on substrate；
First side wall is transferred in substrate to the pattern of the n-th side wall, is included the step of to form fin：
Perform etching with the first side wall to the n-th side wall to shelter, form the first hard mask layer of patterning；
The first side wall is removed to the n-th side wall；
It is to shelter the etching for carrying out substrate with the first hard mask layer, to form fin；
The first side wall is removed to the n-th side wall.
3. manufacture method according to claim 1, it is characterised in that the initial graph pattern layer and
One side wall has identical semi-conducting material.
4. manufacture method according to claim 3, it is characterised in that the semi-conducting material is many
Crystal silicon or non-crystalline silicon.
5. manufacture method according to claim 1, it is characterised in that before carrying out oxidation technology,
The thickness range of the n-th side wall is 10～100nm.
6. manufacture method according to claim 1, it is characterised in that the thickness model of the n-th oxide layer
Enclose for 5～50nm.
7. a kind of manufacture method of semiconductor device, it is characterised in that using arbitrary in claim 1-6
The fin that method described in is formed.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080023803A1 (en) * | 2006-07-31 | 2008-01-31 | Freescale Semiconductor, Inc. | Method for forming vertical structures in a semiconductor device |
| CN104022022A (en) * | 2013-02-28 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of multigraph |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080023803A1 (en) * | 2006-07-31 | 2008-01-31 | Freescale Semiconductor, Inc. | Method for forming vertical structures in a semiconductor device |
| US7556992B2 (en) * | 2006-07-31 | 2009-07-07 | Freescale Semiconductor, Inc. | Method for forming vertical structures in a semiconductor device |
| CN104022022A (en) * | 2013-02-28 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of multigraph |
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