CN106558083A - A kind of accelerated method in webp compression algorithms infra-frame prediction stage, apparatus and system - Google Patents
A kind of accelerated method in webp compression algorithms infra-frame prediction stage, apparatus and system Download PDFInfo
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- CN106558083A CN106558083A CN201611092708.XA CN201611092708A CN106558083A CN 106558083 A CN106558083 A CN 106558083A CN 201611092708 A CN201611092708 A CN 201611092708A CN 106558083 A CN106558083 A CN 106558083A
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- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
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- G06T9/004—Predictors, e.g. intraframe, interframe coding
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Abstract
The invention discloses a kind of accelerated method in webp compression algorithms infra-frame prediction stage, apparatus and system, for data center server, are included in the picture that CPU ends obtain webp forms, picture is divided into into the macro block its positional information of default size；Macro block to be predicted is selected as current block, judges that surrounding's predeterminated position of current block, with the presence or absence of encoded macro block, if having, current block and encoded macro block is sent to computing chip according to the positional information of current block；Default several prediction is respectively carried out according to current block and encoded macro block for computing chip to calculate, obtain predicting the outcome and distortion rate for every kind of prediction calculating, send to CPU；Choose the minimum prediction of distortion rate and calculate the corresponding coding predicted the outcome as current block；Continue to select next one current block, until the whole macro blocks in picture are encoded and completed.Logical judgment is distinguished by the present invention with vector calculating, is processed by different chips respectively, and the speed of infra-frame prediction is fast.
Description
Technical field
The present invention relates to picture infra-frame prediction technical field, more particularly to a kind of webp compression algorithms infra-frame prediction stage
Accelerated method, apparatus and system.
Background technology
In the Internet+epoch, according to incompletely statistics, image data accounts for 60% of the Internet total flow or so, mass picture
The transmission of data increased network delay.WebP picture formats are a kind of picture compression forms, using complicated compression algorithm come
Exchange higher compression ratio for.
In whole WebP compression processes, infra-frame prediction is an important stage, and the purpose of infra-frame prediction is to picture point
Each macro block obtained after cutting is encoded.In this process due to processing various predictive modes, therefore complicated logic is needed to sentence
Disconnected and substantial amounts of vector calculates operation, and traditional CPU can not realize that high-speed parallel is calculated well, and processing speed is slow.
Therefore, how to provide a kind of picture intra-frame prediction method of the fast webp forms of processing speed, apparatus and system is
Those skilled in the art need the problem for solving at present.
The content of the invention
It is an object of the invention to provide a kind of accelerated method in webp compression algorithms infra-frame prediction stage, apparatus and system,
Logical judgment etc. is operated and is made a distinction with vector calculating operation, carried out by CPU and computing chip respectively, at two kinds of chip division of labor
Reason, the speed of infra-frame prediction are fast.
To solve above-mentioned technical problem, the invention provides a kind of acceleration side in webp compression algorithms infra-frame prediction stage
Method, for data center server, including：
Step s101：The picture of webp forms is obtained at CPU ends, the picture is divided into into the macro block of default size and is remembered
Record the positional information of each macro block；
Step s102：Current macro block to be predicted is selected as current block, is judged according to the positional information of the current block
On the picture, surrounding's predeterminated position of the current block whether there is encoded macro block, if having, by the current block and
The encoded macro block is sent to computing chip；For computing chip according to the current block and the encoded macro block point
Do not carry out it is default it is several prediction calculate, obtain it is every kind of it is described prediction calculate predict the outcome and distortion rate, and send to
The CPU；
Step s103：Choose the minimum prediction of distortion rate and calculate the corresponding coding predicted the outcome as the current block,
Repeat step s102, until the whole macro blocks in the picture are encoded and completed.
Preferably, the surrounding predeterminated position is specially left side, top and the upper left side of the current block.
Preferably, the default several prediction calculating is specifically included：
The combination of one or more in horizontal forecast, vertical prediction, DC predictions and motion prediction.
To solve above-mentioned technical problem, present invention also offers a kind of acceleration dress in webp compression algorithms infra-frame prediction stage
Put, for data center server, including：
The picture, for the picture of webp forms is obtained at CPU ends, is divided into default size by picture acquisition module
Macro block simultaneously records the positional information of each macro block；
Chosen module, for selecting current macro block to be predicted as current block, according to the positional information of the current block
Surrounding's predeterminated position of the current block on the picture is judged with the presence or absence of encoded macro block, if having, by the current block
And the encoded macro block is sent to computing chip；For computing chip according to the current block and described encoded grand
Block carries out default several prediction respectively and calculates, and obtains predicting the outcome and distortion rate for every kind of prediction calculating, concurrently
Deliver to the CPU；
Coding module, calculates the corresponding volume predicted the outcome as the current block for choosing the minimum prediction of distortion rate
Code；And the selected next macro block to be predicted of the chosen module is triggered, until the whole macro blocks in the picture have been encoded
Into.
To solve above-mentioned technical problem, present invention also offers a kind of acceleration system in webp compression algorithms infra-frame prediction stage
System, for data center server, including CPU and computing chip, include above picture infra-frame prediction device in the CPU.
Preferably, the computing chip is specially FPGA.
The invention provides a kind of accelerated method in webp compression algorithms infra-frame prediction stage, apparatus and system, in CPU
The division of macro block is carried out, and surrounding's predeterminated position of current block is operated with the presence or absence of the logical judgment of encoded macro block, afterwards
Calculating is predicted to current block and encoded macro block to be carried out by computing chip.I.e. logical judgment etc. is operated by the present invention
Operation is calculated with vector to make a distinction, is carried out by CPU and computing chip respectively, computing chip is compared CPU and is more suitable for being counted
Operation is calculated, and CPU is then only used for processing the operation such as logical judgment, processed by two kinds of chip division of labor, improve the speed of infra-frame prediction
Degree.
Description of the drawings
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, below will be to institute in prior art and embodiment
The accompanying drawing that needs are used is briefly described, it should be apparent that, drawings in the following description are only some enforcements of the present invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can be being obtained according to these accompanying drawings
Obtain other accompanying drawings.
A kind of flow process of the process of the accelerated method in webp compression algorithms infra-frame prediction stage that Fig. 1 is provided for the present invention
Figure；
Current block and the encoded macro block schematic diagram of surrounding in a kind of specific embodiment that Fig. 2 is provided for the present invention；
A kind of structural representation of the acceleration system in webp compression algorithms infra-frame prediction stage that Fig. 3 is provided for the present invention.
Specific embodiment
The core of the present invention is to provide a kind of accelerated method and its device in webp compression algorithms infra-frame prediction stage, will patrol
Collect the operation such as judgement to make a distinction with vector calculating operation, carried out by CPU and computing chip respectively, two kinds of chip division of labor process,
The speed of infra-frame prediction is fast.
To make purpose, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
The a part of embodiment of the present invention, rather than the embodiment of whole.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
The invention provides a kind of accelerated method in webp compression algorithms infra-frame prediction stage, for data center services
Device, a kind of shown in Figure 1, the process of the accelerated method in webp compression algorithms infra-frame prediction stage that Fig. 1 is provided for the present invention
Flow chart；The method includes：
Step s101：The picture of webp forms is obtained at CPU ends, picture is divided into into the macro block of default size and is recorded every
The positional information of individual macro block；
It is understood that the picture uses YUV colour coding methods, each macro block is by a luminance block and two
Chrominance block is constituted, and as Y (luminance component) is different from UV (chromatic component) sample rate, Y, UV is divided into different size of piece,
Wherein the size of Y luminance blocks is 16*16, and the size of UV chrominance blocks is 8*8；Certainly, specific size of the present invention to each macro block
Do not limit.
Step s102：Current macro block to be predicted is selected as current block, picture is judged according to the positional information of current block
Surrounding's predeterminated position of upper current block whether there is encoded macro block, if having, current block and encoded macro block be sent
To computing chip；Default several prediction is respectively carried out according to current block and encoded macro block for computing chip to calculate,
Predicting the outcome and distortion rate for every kind of prediction calculating is obtained, and is sent to CPU；
Wherein, positional information here is specially coordinate, for example, can be xy coordinates.In addition, in addition it is also necessary to according to current block
Coordinate and the ranks width gauge of current block calculate the initial address of current block, for carrying out using when macro block sends.
Preferably, surrounding predeterminated position is specially left side, top and the upper left side of current block.Surrounding predeterminated position is regarded
Depending on prediction calculation, the present invention is not construed as limiting to this.
In addition, after current block and encoded macro block is sent to computing chip, CPU can send startup control instruction extremely
Computing chip, is predicted calculating for arranging relevant parameter and control computing chip.Certainly, parameter setting here regards tool
Depending on body situation.
Further, after the completion of prediction, computing chip can send end mark to CPU, after CPU receives the end mark
Generate and read instruction, what the various predictions of reading were calculated predicts the outcome and distortion rate.
Step s103：Choose the minimum prediction of distortion rate and calculate the corresponding coding predicted the outcome as current block, repeat
Step s102, until the whole macro blocks in picture are encoded and completed.
Wherein, default several prediction calculating is specifically included：
The combination of one or more in horizontal forecast, vertical prediction, DC predictions and motion prediction.
For convenience of understanding, by taking the macro block of 4*4 as an example.Shown in Figure 2, Fig. 2 is embodied as one kind that the present invention is provided
Current block and the encoded macro block schematic diagram of surrounding in example.
Wherein, the relational expression that every kind of prediction is calculated is as follows：
Horizontal forecast：Xij=Li；I.e. horizontal forecast when current block each pixel predict the outcome it is same equal on the left of which
The coding of the capable macro block for having programmed.
Vertical prediction：Xij=Aj；I.e. vertical prediction when current block each pixel the side thereon such as predict the outcome it is same
The coding of the macro block for having programmed of row.
DC is predicted：Xij=(Li+Aj/2
Motion prediction：Xij=Li+Aj-C
The equal ∈ of wherein i, j (0,1,2,3), XijRepresent each the pixel prediction result to current macro.
The invention provides a kind of accelerated method in webp compression algorithms infra-frame prediction stage, carries out macro block in CPU
Divide, and surrounding the predeterminated position of current block with the presence or absence of encoded macro block logical judgment operation, afterwards to current block with
And encoded macro block be predicted calculating be then to be carried out by computing chip.I.e. the operation such as logical judgment and vector are calculated by the present invention
Operation makes a distinction, and is carried out by CPU and computing chip respectively, and computing chip is compared CPU and is more suitable for carrying out calculating operation, and
CPU is then only used for processing the operation such as logical judgment, is processed by two kinds of chip division of labor, improves the speed of infra-frame prediction.
Present invention also offers a kind of accelerator in webp compression algorithms infra-frame prediction stage, for data center services
Device, the device include：
Picture, for the picture of webp forms is obtained at CPU ends, is divided into the grand of default size by picture acquisition module 11
Block simultaneously records the positional information of each macro block；
Chosen module 12, for selecting current macro block to be predicted as current block, sentences according to the positional information of current block
On disconnected picture, surrounding's predeterminated position of current block whether there is encoded macro block, if having, by current block and encoded grand
Block is sent to computing chip 2；Carried out according to current block and encoded macro block respectively for computing chip 2 default several pre-
Survey and calculate, obtain predicting the outcome and distortion rate for every kind of prediction calculating, and send to CPU1；
Coding module 13, calculates the corresponding volume predicted the outcome as current block for choosing the minimum prediction of distortion rate
Code；And the selected next macro block to be predicted of chosen module 12 is triggered, until the whole macro blocks in picture are encoded and are completed.
The invention provides a kind of accelerator in webp compression algorithms infra-frame prediction stage, carries out macro block in CPU
Divide, and surrounding the predeterminated position of current block with the presence or absence of encoded macro block logical judgment operation, afterwards to current block with
And encoded macro block be predicted calculating be then to be carried out by computing chip.I.e. the operation such as logical judgment and vector are calculated by the present invention
Operation makes a distinction, and is carried out by CPU and computing chip respectively, and computing chip is compared CPU and is more suitable for carrying out calculating operation, and
CPU is then only used for processing the operation such as logical judgment, is processed by two kinds of chip division of labor, improves the speed of infra-frame prediction.
Present invention also offers a kind of acceleration system in webp compression algorithms infra-frame prediction stage, for data center services
Device, a kind of shown in Figure 3, the structure of the acceleration system in webp compression algorithms infra-frame prediction stage that Fig. 3 is provided for the present invention
Schematic diagram.The system includes including above picture infra-frame prediction device in CPU1 and computing chip 2, CPU1.
Wherein, computing chip 2 here is specially FPGA.It is understood that FPGA (Field-Programmable
Gate Array, field programmable gate array) calculating speed is fast, it is adaptable to carry out the operation comprising a large amount of vector operations and process.
In addition, the present invention needs caching is arranged in FPGA, the caching can arrange the DDR internal memory (Double with FPGA
Data Rate, Double Data Rate synchronous DRAM) on, certainly, the present invention does not limit the position of caching.The caching is used
Predicted after the completion of the coding of the macro block that predetermined position has been programmed and prediction around the current block that CPU1 sends is with which
And distortion rate as a result.
In addition, the present invention can generate corresponding arthmetic statement using OpenCL high-level languages, and then generate respectively
The host side program run on CPU1, and towards the Kernel ends program of FPGA platform.Then, using GCC compilers to master
Generator terminal program is compiled, and generates the executable program file that can be performed on CPU1；Using Altera SDK for OpenCL
(AOC) High Level Synthesis instrument is compiled synthesis to Kernel program files, generates the AOCX files that can be run on FPGA.
Finally, connected using PCI-E interface between CPU1 and FPGA, enter row data communication；Using the DDR3 internal memories on FPGA development boards
As data buffer storage.Certainly, it is more than preferred embodiment, depending on specifically how generating program according to practical situation.
It should be noted that in this manual, such as first and second or the like relational terms are used merely to one
Individual entity or operation are made a distinction with another entity or operation, and are not necessarily required or implied these entities or operate it
Between there is any this actual relation or order.And, term " including ", "comprising" or its any other variant are intended to
Cover including for nonexcludability, so that a series of process, method, article or equipment including key elements not only includes those
Key element, but also including other key elements being not expressly set out, or also include for this process, method, article or set
Standby intrinsic key element.In the absence of more restrictions, the key element for being limited by sentence "including a ...", it is not excluded that
Also there is other identical element in the process including the key element, method, article or equipment.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
Various modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized without departing from the spirit or scope of the present invention in other embodiments.Therefore, the present invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope for causing.
Claims (6)
1. a kind of accelerated method in webp compression algorithms infra-frame prediction stage, for data center server, it is characterised in that bag
Include：
Step s101：The picture of webp forms is obtained at CPU ends, the picture is divided into into the macro block of default size and is recorded every
The positional information of individual macro block；
Step s102：Current macro block to be predicted is selected as current block, judges described according to the positional information of the current block
On picture, surrounding's predeterminated position of the current block whether there is encoded macro block, if having, by the current block and described
Encoded macro block is sent to computing chip；Entered according to the current block and the encoded macro block respectively for computing chip
The default several prediction of row is calculated, and is obtained predicting the outcome and distortion rate for every kind of prediction calculating, and is sent to CPU；
Step s103：Choose the minimum prediction of distortion rate and calculate the corresponding coding predicted the outcome as the current block, repeat
Step s102, until the whole macro blocks in the picture are encoded and completed.
2. method according to claim 1, it is characterised in that the surrounding predeterminated position is specially a left side for the current block
Side, top and upper left side.
3. method according to claim 1, it is characterised in that the default several prediction calculating is specifically included：
The combination of one or more in horizontal forecast, vertical prediction, DC predictions and motion prediction.
4. a kind of accelerator in webp compression algorithms infra-frame prediction stage, for data center server, it is characterised in that bag
Include：
The picture, for the picture of webp forms is obtained at CPU ends, is divided into the macro block of default size by picture acquisition module
And record the positional information of each macro block；
Chosen module, for selecting current macro block to be predicted as current block, judges according to the positional information of the current block
On the picture, surrounding's predeterminated position of the current block whether there is encoded macro block, if having, by the current block and
The encoded macro block is sent to computing chip；For computing chip according to the current block and the encoded macro block point
Do not carry out it is default it is several prediction calculate, obtain it is every kind of it is described prediction calculate predict the outcome and distortion rate, and send to
The CPU；
Coding module, calculates the corresponding coding predicted the outcome as the current block for choosing the minimum prediction of distortion rate；
And the selected next macro block to be predicted of the chosen module is triggered, until the whole macro blocks in the picture are encoded and are completed.
5. a kind of acceleration system in webp compression algorithms infra-frame prediction stage, for data center server, it is characterised in that bag
Include.
6. system according to claim 4, it is characterised in that the computing chip is specially FPGA.
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| CN107154062A (en) * | 2017-05-12 | 2017-09-12 | 郑州云海信息技术有限公司 | A kind of implementation method of WebP Lossy Compression Algorithms, apparatus and system |
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| CN107507125A (en) * | 2017-08-31 | 2017-12-22 | 郑州云海信息技术有限公司 | Alpha passage palettes generation method, system and host side in a kind of WebP compression of images |
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| CN107612681A (en) * | 2017-09-25 | 2018-01-19 | 郑州云海信息技术有限公司 | A kind of data processing method based on SM3 algorithms, apparatus and system |
| CN108156457A (en) * | 2017-12-27 | 2018-06-12 | 郑州云海信息技术有限公司 | A kind of JPEG turns the method for encoding images and device of WebP |
| CN108156457B (en) * | 2017-12-27 | 2021-10-15 | 郑州云海信息技术有限公司 | Image coding method and device for converting JPEG (Joint photographic experts group) into WebP (Web WebP) |
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Application publication date: 20170405 |