CN106549668A - Multi-modulus frequency divider and its basic frequency unit - Google Patents
Multi-modulus frequency divider and its basic frequency unit Download PDFInfo
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- CN106549668A CN106549668A CN201610886083.8A CN201610886083A CN106549668A CN 106549668 A CN106549668 A CN 106549668A CN 201610886083 A CN201610886083 A CN 201610886083A CN 106549668 A CN106549668 A CN 106549668A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/08—Output circuits
- H03K21/10—Output circuits comprising logic circuits
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Abstract
The invention discloses a kind of multi-modulus frequency divider and its basic frequency unit, the multi-modulus frequency divider is formed by multiple basic frequency units cascades.The basic frequency unit is for reducing the frequency of divided input signal according to mode input signal and control bit signal, the basic frequency unit includes four latch, wherein, the basic frequency unit also includes pulse width modulation circuit, and the pulse width modulation circuit is used for the pulsewidth for increasing the mode input signal.Basic frequency unit in the multi-modulus frequency divider can be widened to the pulsewidth of mode input signal, when the pulsewidth of the mode input signal that the basic frequency unit is received is not enough, the basic frequency unit can export correct divided output signal under divide-by-three mode, enable to divide the divided input signal of higher frequency by the multi-modulus frequency divider of the basic frequency unit cascade, that is, realize broader locking bandwidth.
Description
Technical field
The present invention relates to electronic circuit technology field, more particularly, to multi-modulus frequency divider and its basic frequency unit.
Background technology
Frequency divider is one of wired most crucial module with transceiver, is widely used in high-speed communication and circuit
In, its major function is that input signal is generated output signal by certain frequency dividing ratio.Multi-modulus frequency divider (Multi-modulus
Divider, MMD) it is a kind of programmable frequency divider, it can obtain various frequency dividing ratios by programming, so as to produce various frequencies
The output signal of rate.Multi-modulus frequency divider is commonly used to the feedback branch of phaselocked loop with the switching between completing channel.
Multi-modulus frequency divider can be formed by the cascade of basic frequency unit, and each basic frequency unit can be input into according to pattern
Signal realizes the function of two divided-frequency or three frequency division.When the frequency of divided input signal reaches certain value, the pattern input
The pulsewidth deficiency of signal can cause the three frequency division function of basic frequency unit realize, therefore, the pulsewidth of mode input signal
The locking bandwidth of frequency divider can be affected.
Therefore, expect to further expand the locking bandwidth of multi-modulus frequency divider.
The content of the invention
In order to solve the problems, such as above-mentioned prior art, the present invention provides a kind of multi-modulus frequency divider, and which has broader
Locking bandwidth.
According to an aspect of the present invention, there is provided a kind of basic frequency unit of multi-modulus frequency divider, the basic frequency dividing is single
Unit for the frequency of divided input signal being reduced according to mode input signal and control bit signal, the basic frequency unit bag
Four latch are included, wherein, the basic frequency unit also includes pulse width modulation circuit, and the pulse width modulation circuit is used to increase
The pulsewidth of the mode input signal.
Preferably, the pulse width modulation circuit includes：Delay circuit, which is used to be input into the pattern according to time delay
Signal delay, so as to obtain the postpones signal of the mode input signal；AND gate, which is by the postpones signal and institute
State mode input signal phase with, so as to obtain merge signal；First phase inverter and the second phase inverter of series connection, which is by the merging
What signal obtained the pulse width modulation circuit widens signal；First buffer and the 3rd phase inverter of series connection, which is by the merging
Signal obtains the inversion signal for widening signal.
Preferably, it is less than first threshold the time delay.
Preferably, pulsewidth of the first threshold less than or equal to the mode input signal, and it is defeated less than the frequency dividing
Enter the half of signal period.
Preferably, the time delay is adjustable, and the delay circuit includes：Chain of inverters, which is by even number of inverters level
Connection is formed；MUX, its first input end receive the postpones signal, and its second input receives institute's delays time to control letter
Number, the MUX has multiple outfans, in the plurality of outfan a outfan and the chain of inverters
Outfan is connected, the node phase between other outfans and its adjacent inverters in the chain of inverters of the plurality of outfan
Even, it is defeated that in the plurality of outfan is connected to described first according to the delay control signal by the MUX
Enter end so that the delay circuit can generate various time delays according to the delay control signal.
Preferably, four latch of the basic frequency unit include the first latch, the second latch, the 3rd
Latch and the 4th latch, first latch receive the positive and negative output signal of second latch and described the
The positive and negative output signal of four latch, second latch receive the positive and negative output signal of first latch, described
3rd latch receives the positive and negative output signal of second latch, described widen signal and described widen the anti-of signal
Phase signals, the 4th latch receive the positive and negative output signal of the 3rd latch, the control bit signal and described
The inversion signal of control bit signal, four latch are respectively provided with positive clock end and negative clock end, and the positive clock end
The signal inversion that the signal of reception is received with the negative clock end, first latch are equal with the positive clock end of the 3rd latch
Receive the divided input signal of the basic frequency unit, the negative clock of second latch and the 4th latch
End receives the divided input signal, and the positive output signal of second latch is described point of the basic frequency unit
Frequency output signal, the positive output signal of the 3rd latch is the mode output signal of the basic frequency unit.
Preferably, the circuit structure of second latch is first structure, and the first structure is CML
Latch structure, the latch structure of the CML includes two pull-up resistors and multiple transistors.
Preferably, the circuit structure of first latch, the 3rd latch and the 4th latch be different from it is described
Second structure of first structure, second structure are comprising the latch structure with gate logic and CML.
According to a further aspect in the invention, there is provided a kind of multi-modulus frequency divider, the multi-modulus frequency divider is single by basic frequency dividing
Unit's cascade is formed, the basic frequency unit for according to mode input signal and control bit signal by the frequency of divided input signal
Rate is reduced, and the basic frequency unit includes four latch, wherein, the basic frequency unit also includes pulse-width regulated electricity
Road, the pulse width modulation circuit are used for the pulsewidth for increasing the mode input signal.
The realization of CML (Current Mode Logic, CML) structure is employed in above-mentioned optimal technical scheme
Sampling and latch function, the CML structures can realize less output voltage swing and shorter output setup time, therefore can
To reach higher speed；And as CML structures are fully differential structures, therefore, it is possible to suppression common mode noise well.
To be embedded in the first latch, the 3rd latch and the 4th latch with gate logic in above-mentioned optimal technical scheme,
Prevent it is independent produce larger time delay in logic circuits with gate circuit, so as to further improve the operating rate of circuit.
The basic frequency unit of the multi-modulus frequency divider that the present invention is provided can be widened to the pulsewidth of mode input signal,
When the pulsewidth of the mode input signal that the basic frequency unit is received is not enough, the basic frequency unit can be in three frequency division mould
Correct divided output signal is exported under formula so that can be to higher by the multi-modulus frequency divider of the basic frequency unit cascade
The divided input signal of frequency is divided, that is, realize broader locking bandwidth.
Description of the drawings
By description referring to the drawings to the embodiment of the present invention, the above-mentioned and other purposes of the present invention, feature and
Advantage will be apparent from.
Fig. 1 illustrates the schematic block diagram of existing multi-modulus frequency divider.
Fig. 2 illustrates a kind of schematic circuit of existing basic frequency unit.
Fig. 3 illustrates the first latch or the second latch or the 3rd latch or the 4th lock in existing basic frequency unit
The illustrative circuitry of storage.
Fig. 4 illustrates the schematic block diagram of the multi-modulus frequency divider of the embodiment of the present invention.
Fig. 5 illustrates the illustrative circuitry of the basic frequency unit for constituting the embodiment of the present invention.
Fig. 6 illustrates the first latch, the 3rd latch and the 4th latch in the basic frequency unit of the embodiment of the present invention
The illustrative circuitry of device.
Fig. 7 illustrates the schematic diagram of the first implementing circuit of the pulse width modulation circuit in the embodiment of the present invention.
Fig. 8 illustrates the time diagram of the first implementing circuit of the pulse width modulation circuit in the embodiment of the present invention.
Fig. 9 a and Fig. 9 b are shown respectively the schematic circuit of delay circuit in pulse width modulation circuit as shown in Figure 9, figure
9c and Fig. 9 d are shown respectively the circuit diagram of the circuit diagram and buffer of phase inverter.
Figure 10 illustrates the schematic diagram of second implementing circuit of the pulse width modulation circuit of the embodiment of the present invention.
Figure 11 illustrates the schematic circuit of the delay circuit in pulse width modulation circuit as shown in Figure 10.
Specific embodiment
The present invention is more fully described hereinafter with reference to accompanying drawing.In various figures, identical element is attached using what is be similar to
Icon is remembered to represent.For the sake of clarity, the various pieces in accompanying drawing are not necessarily to scale.Additionally, may not show in figure
Go out part known to some.
Describe hereinafter many specific details of the present invention, the structure of such as device, material, size, place's science and engineering
Skill and technology, to be more clearly understood that the present invention.But just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Below, the present invention is described in detail referring to the drawings.
Fig. 1 illustrates the schematic block diagram of existing multi-modulus frequency divider.
As shown in figure 1, multi-modulus frequency divider 1000 is formed by the cascade of multiple basic frequency units 100, it is respectively from left to right
The basic frequency unit of the first order is to (n+1)th grade of basic frequency unit.Wherein, each basic frequency unit has frequency dividing input
Fin, frequency division output terminal Fout, pattern input Min, pattern outfan Mout and control bit end P.The first order divides list substantially
The frequency dividing input Fin of unit receives initial signal f (in), the basic frequency unit of every one-level after the basic frequency unit of the first order
Frequency dividing input Fin be all connected with frequency division output terminal Fout of the basic frequency unit of its previous stage, so as to basic at (n+1)th grade
Frequency division output terminal Fout of frequency unit produces the first down-scaled signals f (out).The first order is to (n+1)th grade of basic frequency unit
Control bit end P receives control bit signal P [0] respectively to P [n].The pattern input Min of (n+1)th grade of 2/3 frequency dividing circuit receives high
Level signal H, the pattern input Min of the basic frequency unit of every one-level before (n+1)th grade of basic frequency unit with thereafter
The pattern outfan Mout of the basic frequency unit of one-level is connected, so as to the pattern outfan in the basic frequency unit of the first order
Mout produces the second down-scaled signals m (out).
Operationally, per one-level, basic frequency unit 100 can be in control bit end P and pattern for above-mentioned multi-modulus frequency divider 1000
Divide-by-two mode or divide-by-three mode are realized under the control of the signal received by input Min：When pattern input Min connects
When the signal for receiving is low level, the output low level of pattern outfan Mout, the signal frequency of signal output part Fout outputs
/ 2nd of the signal frequency received for signal input part Fin；When the signal that pattern input Min is received is high level
And when the signal that control bit end P is received is low level, the signal frequency of signal output part Fout outputs is signal input part
/ 2nd of the signal frequency that Fin is received, the signal exported by pattern outfan Mout are received for signal input part Fin
Signal frequency 1/2nd；When the signal that pattern input Min is received is that high level and control bit end P are received
When signal is high level, three points of the signal frequency that the signal frequency that signal output part Fout is exported is received for signal input part
One of, 1/3rd of the signal frequency that the signal exported by pattern outfan Mout is received for signal input part.
Therefore, above-mentioned multi-modulus frequency divider 1000 can be by control bit signal P [n:0] it is configured, by initial signal f
(in) with different frequency dividing ratio frequency reducings, to obtain the first down-scaled signals f (out) and the second down-scaled signals m (out).For example, work as n
During equal to 1, multi-modulus frequency divider 1000 is made up of the basic frequency unit of two-stage 100.As control bit signal P [1:When 0]=00, multimode
The frequency of the frequency and the second down-scaled signals m (out) of the first down-scaled signals f (out) that frequency divider 1000 is provided is just
The a quarter of beginning signal f (in) frequency；As control bit signal P [1:When 0]=01, multi-modulus frequency divider 1000 provided first
The frequency of the frequency of down-scaled signals f (out) and the second down-scaled signals m (out) be initial signal f (in) frequency five/
One；As control bit signal P [1:When 0]=10, the frequency of the first down-scaled signals f (out) that multi-modulus frequency divider 1000 is provided with
And second the frequency of down-scaled signals m (out) m (out) be 1/6th of initial signal f (in) frequency；As control bit signal P
[1:When 0]=11, the frequency and the second down-scaled signals m of the first down-scaled signals f (out) that multi-modulus frequency divider 1000 is provided
(out) frequency is 1/7th of initial signal f (in) frequency.As can be seen here, multi-modulus frequency divider 1000 is believed in control bit
Number P [n:0] frequency dividing ratio of continuous variable can be realized under control.
Fig. 2 illustrates a kind of schematic circuit of existing basic frequency unit.For convenience of by outside basic frequency unit
Portion port title is corresponding with internal signal title, in fig. 2 be described below, each outside port title is in inside modules conduct
The signal name for being input into from the outside port or exporting occurs.
As shown in Fig. 2 basic frequency unit 100 includes the first latch 110, the second latch 120, the 3rd latch
130th, the 4th latch 140, and door U150 and door U160 and with door U170.Wherein, the first latch 110, the second latch
120th, the 3rd latch 130 and 140 structure of the 4th latch are identical.
With two inputs of door U150 reversed-phase output Qb and the second latch respectively with the 4th latch 140
120 reversed-phase output Qb is connected, and is connected with the data input pin D of the first latch 110 with the outfan of door U150, the first lock
The positive output end Q of storage 110 is connected with the data input pin D of the second latch 120.The positive output of the second latch 120
End Q output frequency division output signals Fout, receive divided output signal Fout and pattern respectively with two inputs of door U160
Input signal Min, is connected with the data input pin D of the 3rd latch 130 with the outfan of door U160.3rd latch 130
Positive output end Q output mode output signals Mout, two input difference receptive pattern output signals Mout with door U170
And control bit signal P, it is connected with the data input pin D of the 4th latch 140 with the outfan of door U170.
Aforementioned four latch 110 to 140 is respectively provided with positive clock end CLK, the first latch 110 and the 3rd latch 130
Positive clock end CLK receive divided input signal Fin, the second latch 120 connect with the positive clock end CLK of the 4th latch 140
Receive the inversion signal of divided input signal Fin.
In above-mentioned basic frequency unit 100, when mode input signal Min is low level, mode output signal Mout
Permanent is low level, and the frequency of divided output signal Fout is 1/2nd of divided input signal Fin frequencies；When pattern input is believed
Number Min is high level and when control bit signal P is low level, and the frequency of divided output signal Fout is divided input signal
/ 2nd of Fin frequencies, the frequency of mode output signal Mout is 1/2nd of divided input signal Fin frequencies, is realized
Divide-by-two mode；When mode input signal Min is high level and control bit signal P is high level, divided output signal
The frequency of Fout for divided input signal Fin frequencies 1/3rd, the frequency of mode output signal Mout is frequency dividing input letter
/ 3rd of number Fin frequencies, realize divide-by-three mode.
Fig. 3 illustrates the first latch or the second latch or the 3rd latch or the 4th lock in existing basic frequency unit
The illustrative circuitry of storage.
As shown in figure 3, each latch in basic frequency unit 100 include the first transistor M01, transistor seconds M02,
Third transistor M03, the 4th transistor M04, the 5th transistor M05, the 6th transistor M06, first resistor R01 and second are electric
Resistance R02.Wherein, this six transistors of the transistor M06 of the first transistor M01 to the 6th are N-type MOSFET.The first transistor
M01 and transistor seconds M02 is a pair of difference pipes, the source electrode of the first transistor M01 and the source electrode and the 3rd of transistor seconds M02
The drain electrode of transistor M03 is connected, the drain electrode of the first transistor M01 and the drain electrode of transistor seconds M02 respectively with reversed-phase output
Qb is connected with positive output end Q.The drain electrode of the grid and the 5th transistor M05 of the 4th transistor M04 is connected to positive output end
The drain electrode of the grid and the 4th transistor M04 of Q, the 5th transistor M05 is connected to inverting input Qb, the 4th transistor M04's
The source electrode of source electrode and the 5th transistor M05 is connected with the drain electrode of the 6th transistor M06.The source electrode of third transistor M03 and the 6th
The grid of the source grounding of transistor M06, the grid of third transistor M03 and the 6th transistor M06 respectively with positive clock end
CLK is connected with negative clock end CLKb.One end of first resistor R01 receives supply voltage Vcc with one end of second resistance R02,
The other end of first resistor R01 is connected with reversed-phase output Qb, and the other end of second resistance R02 is connected with normal phase input end Q.
In above-mentioned elementary cell 100 in the course of work of each latch：When positive clock end CLK is connect with normal phase input end
When receiving high level, inverting input Db receives low level, transistor seconds M02 shut-offs, the first transistor M01 and third transistor
M03 is turned on, now positive output end Q outputs high level, reversed-phase output Qb output low levels；When positive clock end CLK receives high
When level and normal phase input end D receive low level, inverting input Db receives high level, the first transistor M01 shut-offs, second brilliant
Body pipe M02 is turned on third transistor M03, now positive output end Q outputs low level, reversed-phase output Qb output high level,
So as to realize that, when positive clock end CLK receives high level, the magnitude of voltage of positive output end Q is equal to received by normal phase input end D
Magnitude of voltage, i.e. sample states.When positive clock end CLK receives low level, bear clock end CLKb and receive high level, now not
Low level or high level are received by normal phase input end D and inverting input Db, positive output end Q is equal with reversed-phase output Qb
Keep output voltage values during last positive clock end CLK reception high level constant.So as to realize latch to its output valve
Lock-out state.
However, building as under divide-by-three mode, mode output signal Mout is enough with divided output signal Fout needs
Between immediately, therefore when the pulsewidth of mode input signal Min is not enough, the divide-by-three mode of above-mentioned basic frequency unit cannot be real
It is existing, and then limit the locking bandwidth of multimode latch.
To realize the locking bandwidth of broader multi-modulus frequency divider, a kind of prior art by basic frequency unit 100 each
First resistor R01 and second resistance R02 of latch replaces with load inductance, but load inductance can be taken very in domain
Big area.
Fig. 4 illustrates the schematic block diagram of the multi-modulus frequency divider of the embodiment of the present invention.
As shown in figure 4, the multi-modulus frequency divider 2000 of the embodiment of the present invention is formed by the cascade of basic frequency unit 200, its level
Connection mode is identical with the cascade system of the existing multi-modulus frequency divider 1000 shown in Fig. 1, will not be described here.Below mainly to this
The basic frequency unit 200 of inventive embodiments multi-modulus frequency divider 2000 is described.
Fig. 5 illustrates the illustrative circuitry of the basic frequency unit for constituting the embodiment of the present invention.
Larger time delay is in logic circuits taken with gate circuit due to independent, therefore will be with the embedded latch of gate circuit
In, improve the operating rate of circuit.
As shown in figure 5, basic frequency unit 200 includes the first latch 210, the second latch 220, the 3rd latch
230th, the 4th latch 240 and pulse width modulation circuit 250, wherein, the first latch 210, the 3rd latch 230 and the 4th
240 structure of latch is identical, and the second latch 220 is because not comprising different from the structure of Men Eryu other three latch.
Pulse width modulation circuit 250 produces mode input signal Min_w and expansion expanded according to mode input signal
The inversion signal Minb_w of mode input signal.
First normal phase input end A of the first latch 210 is connected with the reversed-phase output Qb of the 4th latch 240, and first
First inverting input Ab of latch 210 is connected with the positive output end Q of the 4th latch 240.The of first latch 210
Two normal phase input end B are connected with the positive output end Q of the second latch 220, the second inverting input Bb of the first latch 210
It is connected with the reversed-phase output Qb of the second latch 220.
The normal phase input end D of the second latch 220 is connected with the positive output end Q of the first latch 210, the second latch
220 inverting input Db is connected with the reversed-phase output Qb of the first latch 210.The positive output end Q of the second latch 220
Divided output signal Fout is provided.
First normal phase input end A of the 3rd latch 230 receives mode input signal Min_w expanded, and first is anti-phase defeated
Enter to hold Ab to receive the inversion signal Minb_w of the mode input signal expanded.Second normal phase input end B of the 3rd latch 230 with
Second latch, 220 positive output end Q is connected, and the second inverting input Bb of the 3rd latch 230 is anti-with the second latch 220
Phase output terminal Qb is connected.The positive output end Q of the 3rd latch 230 provides mode output signal Mout.
First normal phase input end A of the 4th latch 240 receives control bit signal P, and the first of the 4th latch 240 is anti-phase
Input Ab receives the inversion signal Pb of control bit signal.The second normal phase input end B reception patterns output of the 4th latch 240
Signal Mout, the second inverting input Bb of the 4th latch 240 are connected with the reversed-phase output Qb of the 3rd latch 230.
Aforementioned four latch 210 to 240 is respectively provided with positive clock end CLK and negative clock end CLKb, the first latch 210 with
The positive clock end CLK of the 3rd latch 230 and negative clock end CLKb receive divided input signal Fin and divided input signal respectively
Inversion signal Finb, the second latch 220 connect respectively with the positive clock end CLK and negative clock end CLKb of the 4th latch 240
Receive the inversion signal Finb and divided input signal Fin of divided input signal.
It is identical with the operation principle of existing basic frequency unit 100 in above-mentioned basic frequency unit 200, can be in control
Divide-by-two mode and divide-by-three mode are realized under the control of position signal P.Due to the pulse width modulation circuit 250 in the embodiment of the present invention
The pulsewidth of mode input signal Min is increased, therefore the basic frequency unit of the embodiment of the present invention can divide to higher frequency
Frequency input signal carries out three frequency division, so as to expand the locking bandwidth of the multi-modulus frequency divider of the embodiment of the present invention.
In the basic frequency unit of the embodiment of the present invention, the illustrative circuitry of the second latch is same as shown in Figure 4, here
Repeat no more.
Fig. 6 illustrates the first latch, the 3rd latch and the 4th latch in the basic frequency unit of the embodiment of the present invention
The illustrative circuitry of device.
The circuit structure of the first latch 210, the 3rd latch 230 and the 4th latch 240 is identical, and the structure is in figure
Add on the basis of latch structure shown in 4 and gate logic.
As shown in fig. 6, the latch circuit knot of the first latch 210, the 3rd latch 230 and the 4th latch 240
Structure includes the 7th transistor M07, the 8th transistor M08, the 9th transistor M09, the tenth transistor M10, the 11st transistor
M11, the tenth two-transistor M12, the 13rd transistor M13, the 14th transistor M14, the 15th transistor M15,3rd resistor
R03 and the 4th resistance R04.Wherein, the 7th transistor M15 of transistor M07 to the 15th this nine transistors are N-type
MOSFET.The source electrode of the source electrode and the 8th transistor M08 of the 7th transistor M07 is connected with the drain electrode of the 9th transistor M09, the
The source electrode of ten transistor M10 is connected with the drain electrode of the 11st transistor M11, the source electrode of the 11st transistor M11 and the 9th brilliant
The source electrode of body pipe M09 is connected with the drain electrode of the tenth two-transistor M12.The drain electrode of the 7th transistor M07 and reversed-phase output Qb phases
Even, the drain electrode of the 8th transistor M08 and the drain electrode of the tenth transistor M10 is connected with positive output end Q.7th transistor M07
Grid be connected with the first normal phase input end A, the grid of the 8th transistor M08 is connected with the first inverting input Ab, and the 9th is brilliant
The grid of body pipe M09 is connected with the second normal phase input end B, and the tenth transistor M10 receives supply voltage Vcc, the 11st transistor
The grid of M11 is connected with the second inverting input Bb, and the grid of the tenth two-transistor M12 is connected with positive clock end.Tenth is trimorphism
The drain electrode of the grid and the 14th transistor M14 of body pipe M13 is connected to positive output end Q, the grid of the 14th transistor M14 with
The drain electrode of the 13rd transistor M13 is connected to reversed-phase output Qb, the source electrode and the 14th transistor of the 13rd transistor M13
The source electrode of M14 is connected with the drain electrode of the 15th transistor M15.The source electrode and the tenth two-transistor M12 of the 15th transistor M15
Source grounding.The grid of the 15th transistor M15 is connected with negative clock end.One end of 3rd resistor R03 and the 4th resistance
One end receive supply voltage Vcc, the other end of 3rd resistor R03 is connected with reversed-phase output Qb, 3rd resistor R04 it is another
End is connected with positive output end Q.
In the course of work of above-mentioned flip-latch circuit structure, when positive clock end CLK receives high level to be input into：When
When one normal phase input end A and the second normal phase input end B receive high level, the first inverting input Ab and the second anti-phase input
End Bb receives low level, now the tenth two-transistor M12, the 9th transistor M09, the 7th transistor M07 conductings, and the 8th is brilliant
Body pipe M08, the tenth transistor M10 and the 11st transistor M11 shut-offs, therefore positive output end Q output high level, it is anti-phase defeated
Go out to hold Qb output low levels；When at least one end in the first normal phase input end A and the second normal phase input end B receives low level
When, positive output end Q output low levels, reversed-phase output output high level.Therefore, when positive clock end, CLK receives high level
When, the result exported by positive output end Q is connect with the second normal phase input end B by the first normal phase input end A received signals
The signal phase that receives and result.
When positive clock end CLK receives low level to be input into：Negative clock end CLKb receives high level, positive output end Q with
Reversed-phase output Qb keeps in the presence of the 13rd transistor M13 and the 14th transistor M14 once positive clock end CLK with
Output voltage values when receiving high level are constant.So as to realize lock-out state of the latch to its output valve.
Fig. 7 illustrates the schematic diagram of the first implementing circuit of the pulse width modulation circuit in the embodiment of the present invention.
As shown in fig. 7, pulse width modulation circuit 250 includes delay circuit 251, OR gate U252, buffer U253, phase inverter
U254, phase inverter U255 and phase inverter U256.Wherein, delay circuit 251 enters line delay to mode input signal Min, obtains
Pattern time delayed signal Min_d.Proterotype input signal Min is superimposed with the pattern time delayed signal Min_d after time delay with door U252,
The phase inverter U254 and phase inverter U255 that signal after superposition is concatenated obtains mode input signal Min_w widened, meanwhile, fold
Plus after signal the phase inverter U256 that the is concatenated and buffer U253 inversion signal Minb_ of mode input signal that obtains widening
w。
In the alternate embodiment of above-mentioned pulse width modulation circuit 250, the number of phase inverter and buffer can be with above-mentioned the
A kind of implementing circuit is different, but needs to ensure：Obtain the number of the phase inverter before widening mode input signal Min_w and buffer
The number of device is even number, obtains the number of the phase inverter before widening the inversion signal Minb_w of mode input signal and buffers
The number of device is odd number, and obtain the total number of the phase inverter before widening mode input signal Min_w and buffer with
The phase inverter obtained before widening the inversion signal Minb_w of mode input signal is identical with the total number of buffer, so as to ensure
Mode input signal Min_w that is logically true and making to widen is identical with the edge time of occurrence of its inversion signal Minb_w.
Fig. 8 illustrates the time diagram of the first implementing circuit of the pulse width modulation circuit in the embodiment of the present invention.
As shown in figure 8, in the work process of above-mentioned pulse width modulation circuit 250,251 delay circuit of delay circuit 251 pairs
Mode input signal Min enters line delay, obtains pattern time delayed signal Min_d, and time delay, t1 was less than first threshold.Pattern time delay
The pulsewidth of signal Min_d is identical with pulsewidth t0 of mode input signal Min.With door U252 by pattern time delayed signal Min_d with it is former
Mode input signal Min is superimposed, and the pulsewidth of the signal obtained after superposition is t0*2-t1, so as to increase mode input signal Min
Pulsewidth.Wherein, pulsewidth t0 of the first threshold less than or equal to mode input signal Min, so as to avoid the occurrence of pattern time delayed signal
The abnormal discontinuities of Min_d, meanwhile, first threshold should be less than the half in the divided input signal Fin cycles, basic so as to ensure
Frequency unit 200 being capable of normal work under its divide-by-two mode.
Fig. 9 a and Fig. 9 b are shown respectively the schematic circuit of delay circuit in pulse width modulation circuit as shown in Figure 9.
As illustrated in fig. 9, delay circuit 251 is in series by even number of inverters.As a kind of alternative embodiment, such as
Shown in Fig. 9 b, delay circuit 251 is in series by multiple buffers.Wherein, the circuit diagram of phase inverter as is shown in fig. 9 c, delays
Rush the circuit diagram of device as shown in figure 9d.
Figure 10 illustrates the schematic diagram of second implementing circuit of the pulse width modulation circuit of the embodiment of the present invention.
In the first implementing circuit of above-mentioned pulse width modulation circuit, t1 time delay is fixed.In such as Figure 10 institutes
In second implementing circuit of the pulse width modulation circuit for showing, delay circuit 251 also has delays time to control end so that delay circuit
251 can be adjusted to t1 time delay according to the delay control signal dly that delays time to control termination is received.
Figure 11 illustrates the schematic circuit of the delay circuit in pulse width modulation circuit as shown in Figure 10.
As shown in figure 11, delay circuit 251 includes the chain of inverters that constituted of phase inverter connected by even number and many
Road selector 2511.The initiating terminal of chain of inverters is connected with mode input signal Min.The input of MUX 2511 and control
Distinguish reception pattern time delayed signal Min_d and delay control signal dly, one of output of MUX 2511 in end processed
End be connected with the clearing end of chain of inverters, other each outfans optionally with the section between its adjacent inverters in chain of inverters
Point is connected.Wherein, the phase inverter number between the input of MUX 2511 and each outfan is even number.
In the course of work of the delay circuit 251, MUX 2511 is selected which according to delay control signal dly
In an outfan be connected with its input so that mode input signal Min obtains mould through the time delay of even number of inverters
Formula time delayed signal Min_d.Different delay control signal dly can produce different t1 time delay to obtain different patterns
Time delayed signal Min_d, the time delay, t1 was less than first threshold.Wherein, first threshold is less than or equal to mode input signal Min
Pulsewidth t0, so as to avoid the occurrence of the abnormal discontinuities of pattern time delayed signal Min_d, meanwhile, it is defeated that first threshold should be less than the frequency dividing
Enter the half in signal Fin cycles, so as to ensure that basic frequency unit 200 being capable of normal work under its divide-by-two mode.
It should be noted that herein, such as first and second or the like relational terms are used merely to a reality
Body or operation are made a distinction with another entity or operation, and are not necessarily required or implied these entities or deposit between operating
In any this actual relation or order.And, term " including ", "comprising" or its any other variant are intended to
Nonexcludability is included, so that a series of process, method, article or equipment including key elements not only will including those
Element, but also including other key elements being not expressly set out, or also include for this process, method, article or equipment
Intrinsic key element.In the absence of more restrictions, the key element for being limited by sentence "including a ...", it is not excluded that
Also there is other identical element in process, method, article or equipment including the key element.
According to embodiments of the invention as described above, these embodiments do not have all of details of detailed descriptionthe, not yet
It is only described specific embodiment to limit the invention.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is for the principle and practical application of preferably explaining the present invention, so that affiliated
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention only receives right
The restriction of claim and its four corner and equivalent.
Claims (11)
1. the basic frequency unit of a kind of multi-modulus frequency divider, the basic frequency unit is for according to mode input signal and control
The frequency of divided input signal is reduced by position signal, and the basic frequency unit includes four latch,
Wherein, the basic frequency unit also includes pulse width modulation circuit, and the pulse width modulation circuit is used to increase the pattern
The pulsewidth of input signal.
2. basic frequency unit according to claim 1, wherein, the pulse width modulation circuit includes：
Delay circuit, which is used to postpone the mode input signal according to time delay, so as to obtain the pattern input letter
Number postpones signal；
AND gate, its by the postpones signal and the mode input signal phase with so as to obtain merging signal；
First phase inverter and second phase inverter of series connection, which widens letter by what the merging signal obtained the pulse width modulation circuit
Number；
First buffer and the 3rd phase inverter of series connection, which obtains the inversion signal for widening signal by the signal that merges.
3. multi-modulus frequency divider according to claim 2, wherein, the time delay is less than first threshold.
4. basic frequency unit according to claim 3, wherein, the first threshold is less than or equal to pattern input letter
Number pulsewidth, and the half in the cycle less than the divided input signal.
5. basic frequency unit according to claim 2, wherein, the delay circuit includes chain of inverters, described anti-phase
Device chain is formed by even number of inverters cascade.
6. basic frequency unit according to claim 2, wherein, the delay circuit includes buffer chain, the buffering
Device chain is formed by the cascade of multiple buffer devices.
7. multi-modulus frequency divider according to claim 2, the time delay is adjustable, and the delay circuit includes：
Chain of inverters, which is formed by even number of inverters cascade；
MUX, its first input end receive the postpones signal, and its second input receives institute's delay control signal, institute
State MUX and there are multiple outfans, the outfan of in the plurality of outfan a outfan and the chain of inverters
It is connected, other outfans of the plurality of outfan are connected with the node between its adjacent inverters in the chain of inverters, described
One in the plurality of outfan is connected to the first input end according to the delay control signal by MUX, is made
Obtain the delay circuit and various time delays can be generated according to the delay control signal.
8. basic frequency unit according to claim 2, wherein, four latch bags of the basic frequency unit
The first latch, the second latch, the 3rd latch and the 4th latch are included,
First latch receives the positive and negative defeated of the positive and negative output signal and the 4th latch of second latch
Go out signal, second latch receives the positive and negative output signal of first latch, and the 3rd latch receives described
The positive and negative output signal of the second latch, it is described widen signal and the inversion signal for widening signal, the described 4th latches
Device receives the anti-phase letter of the positive and negative output signal, the control bit signal and the control bit signal of the 3rd latch
Number,
Four latch are respectively provided with positive clock end and negative clock end, and the signal that the positive clock end receives is negative with described
The signal inversion that clock end receives,
The positive clock end of first latch and the 3rd latch receives the frequency dividing input of the basic frequency unit
Signal, the negative clock end of second latch and the 4th latch receive the divided input signal, and described second
The positive output signal of latch is the divided output signal of the basic frequency unit, the positive output of the 3rd latch
Signal is the mode output signal of the basic frequency unit.
9. basic frequency unit according to claim 8, wherein, the circuit structure of second latch is the first knot
Structure, latch structure of the first structure for CML, the latch structure of the CML include two
Individual pull-up resistor and multiple transistors.
10. basic frequency unit according to claim 9, wherein, first latch, the 3rd latch and the 4th lock
The circuit structure of storage is the second structure for being different from the first structure, second structure be comprising with gate logic and
The latch structure of CML.
A kind of 11. multi-modulus frequency dividers, the multi-modulus frequency divider is by multiple basic frequency unit cascades as described in claim 1-8
Form.
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