CN1065392C - Method for realization of data interweaving and deinterweaving using dynamic RAM - Google Patents

Abstract

The present invention relates to a method for realization of data interweaving and deinterweaving using dynamic RAM. In a transmitter, data to be interweaved is input from the input end of the dynamic RAM and is output from the output end of the dynamic RAM after corresponding delay, the input/output address of the dynamic RAM is distributed and controlled according to the interweaving scheme to realize the corresponding delay and to complete interweaving process. In a receiver, the data which is interweaved according to the process is input from the input end of the dynamic RAM and output from the output end of the dynamic RAM after delay which is reverse to the delay.

Description

Adopt dynamic ram to realize data interlacing and the method that deinterleaves

The present invention relates to the coding and decoding technology of digital signal, relate more specifically to a kind of dynamic ram that adopts and realize data interlacing and the method that deinterleaves.

Error correction coding is often wanted the binding data interleaving technology in actual applications.This is burst because of mistake in many channels, the mistake that is to say generation has very strong correlation, when taking place one when wrong, often involves a lot of data of back, cause a slice data all to make a mistake, the error correcting capability of error correcting code that made outnumbering of burst error.So add data interleaver at transmitting terminal, add deinterleaver at receiving terminal, make the burst error of channel spread out, the burst error channel is transformed into independently random error chanel, thereby can gives full play to the effect of error correction coding.Sometimes add interweave after, the error-correcting performance of system can improve several orders of magnitude.Quite powerful data interlacing is arranged among the HDTV.

Data interlacing in the HDTV channel coding/decoding circuit, the part that deinterleaves are also uncomplicated technically, but traditional circuit uses d type flip flop, will take very big chip area when making dedicated IC chip, and be very uneconomical.

That the GA scheme adopts is n ₂=208, n ₁=52 interleaver.The deinterleaver schematic diagram of the interleaver of its transmitting terminal and receiving terminal is seen Fig. 1, B=52 among the figure, and M=4 is because each symbol of RS (207,187) sign indicating number is the byte data of 8 bits, so each shift register is a byte among the figure.Be made of 52 road delay lines respectively, two adjacent input data of interleaver are through behind the interleaver, and it increases to 52 * 4=208 byte clock cycle at interval when appearing at output.Interleaver hereto, its any one length are not comprise in 208 the dateout string (or a RS code word) in the input data sequence at a distance of less than any two data of 52.This interleaver postpones D=(B-1) M=(52-1) * 208=10608, memory capacity S=S _n=B (B-1) M/2=52 * (52-1) * 208/2=5304 shift register byte units, thus no matter be to postpone or the memory number all is best, thereby its structure is simpler than the interleaver of other identical performance.Corresponding deinterleaver is the same with interleaver, just convolution out of order.

GA scheme interleaver can realize that the intersegmental of 52 data segments interweaves, the about sixth of degree of depth field (4ms).And deinterleave to recover normal data order at receiving terminal.Adopt RS (207,187) sign indicating number can correct 10 code word mistakes and this and interweave with combining and can correct the burst error that length is 52 * 10=520 byte (156us), so greatly increased the anchor ability of entangling of RS sign indicating number, its effect is very significant.

But, if adopt d type flip flop to realize above-mentioned interweave and deinterleaving according to the conventional method, adopting single shift register, interleaver (deinterleaver) just needs 5304 * 8=42432 D honor trigger.

The purpose of this invention is to provide a kind of dynamic ram that adopts and realize data interlacing and the method that deinterleaves.It can obviously reduce the gross area and the total cost of receiver chip.

Realize data interlacing and the method that deinterleaves according to a kind of dynamic ram that adopts of the present invention, it is characterized in that:

In transmitter, the data that interweave are from the input input of dynamic ram, after corresponding the delay, output output from this dynamic ram, said corresponding delay is to distribute control to realize by the I/O address to said dynamic ram according to the interleaving scheme that will carry out, thereby finishes interleaving process;

In receiver, import from the input of dynamic ram according to the data that said process has interweaved, after corresponding the delay, output output from this dynamic ram, said corresponding delay is by the I/O address of said dynamic ram is realized according to the distribution control opposite with performed distribution control in the transmitter, thereby finishes the process of deinterleaving.

Realize data interlacing and the method that deinterleaves according to above-mentioned a kind of dynamic ram that adopts, it is characterized in that: the said interleaving scheme that will carry out is the interleaving scheme of GA-HDTV.

Realize data interlacing and the method that deinterleaves according to above-mentioned a kind of dynamic ram that adopts, it is characterized in that:

The end that writes at RAM; The 0th data do not postpone by interleaver as the 1 road signal, No. 0 unit of the RAM that then writes direct; The 1st data need postpone 1 * 4 * 52=208 byte clock as the 2 road signal by interleaver, then write the 1+208=209 unit of RAM, I (0≤i≤51) data need postpone i * 4 * 52=i * 208 a byte clock as i+1 road signal by interleaver, then write No. 208 unit, i+i * of RAM, The 51st data need postpone 51 * 4 * 52=10608 byte clock as the 52 road signal by interleaver, then write the 51+10608=10659 unit of RAM, then, original position is got back in the position of the switch of the input of interleaver, so the 52nd data do not have just write direct No. 52 unit of RAM of delay as the 1 road signal; The 53rd data then need postpone 1 * 4 * 52=208 byte clock as the 2 road signal by interleaver, then write the 53+208=261 unit of RAM, So to K (K＞=0) data, need postpone Kmod52 * 4 * 52=Komd52 * 208 byte clocks by interleaver, and write the AddrIn unit of RAM as Komd52+1 road signal;

AddrIn=K+Kmod52×208

At the end of reading of two-port RAM, press from 0,1,2 ... call over each unit, thereby also just make each data be postponed just to have finished interleave function accordingly.

Fig. 1 is the schematic diagram that conventional employing d type flip flop is realized data interlacing and de-interlacing method.

Fig. 2 is a schematic diagram of realizing data interlacing and de-interlacing method according to employing dynamic ram of the present invention.

Fig. 3 has shown the element circuit of d type flip flop.

Fig. 4 has shown the element circuit of static RAM (SRAM) (SRAM).

Fig. 5 has shown the element circuit of DRAM.

Below in conjunction with Fig. 2 most preferred embodiment of the present invention is described.

Fig. 2 is the method for a kind of equivalence of Fig. 1, and it adopts two-port RAM to replace shift register, realizes the buffer memory displacement by the equivalence of control two-port RAM, thereby finishes the function of interleaving and de-interleaving.Fig. 2 is the equivalent method that example illustrates this realization to interweave.

The operational circumstances that writes end at RAM: as can be known by the GA weaving diagram of Fig. 1, the input end switch of interleaver is positioned at topmost when initial, the 0th data do not postpone by interleaver as the 1 road signal, No. 0 unit of RAM then writes direct, the 1st data need postpone the 1+208=209 unit that 1 * 4 * 52=208 byte clock just writes RAM as the 2 road signal by interleaver, i (0≤i≤51) data need postpone No. 208 unit, i+i * that i * 4 * 52=i * 208 a byte clock just writes RAM as i+1 road signal by interleaver,, the 51st data need postpone the 51+10608=10659 unit that 51 * 4 * 52=10608 byte clock just writes RAM as the 52 road signal by interleaver; At this moment, original position is got back in the position of the switch of the input of interleaver, so the 52nd data do not have just write direct No. 52 unit of RAM of delay as the 1 road signal, the 53rd data then need postpone the 53+208=261 unit that 1 * 4 * 52=208 byte clock just writes RAM as the 2 road signal by interleaver, so, need postpone Kmod52 * 4 * 52=Komd52 * 208 byte clocks as Komd52+1 road signal by interleaver and write the AddrIn unit of RAM to K (K＞=0) data;

AddrIn=K+Kmod52×208

At the end of reading of two-port RAM, press from 0,1,2 ... call over each unit, thereby also just make each data be postponed just to have finished interleave function accordingly.

Dual port RAM realize interweaving than d type flip flop realize interweaving improved a lot.The drawn element circuit of static RAM (SRAM) (SRAM) of the drawn element circuit of d type flip flop of Fig. 3, Fig. 4.It has been generally acknowledged that a d type flip flop comprises 5 gate circuits, a ram cell is equivalent to a gate circuit.Data interlacing and deinterleave circuit all need 42432 d type flip flops, are equivalent to 212160 doors; Or 84864 ram memory cells, be equivalent to 84864 doors.

Yet dynamic ram (DRAM) also wants much simple than static RAM (SRAM) (SRAM) from circuit.The drawn element circuit of DRAM of Fig. 5.Usually, the characteristics of DRAM are: memory capacity is big, and chip occupying area is little, and cost is low.

On the other hand, because the drive of PC industry, the manufacturing technology of dram chip is very advanced, is ahead of the manufacturing technology of general communication circuit chip greatly.For example, dram chip has used the technology of 0.25 μ m and 0.18 μ m to make chip, and the chip that the L64240 chip of the TMS320C31DSP that uses always in the telecommunication circuit and Infineon Technologies Corp. all is to use the above technology of 1.0 μ m to make.

In addition, Toshiba Corp etc. at the capacity of researching and producing greatly to the dram chip of 1GB, the DRAM production technology of the following capacity of 16MB has been tending towards superseded, being dirt cheap just can obtain.

In a word, the DRAM technology is introduced in the telecommunication circuit, configuration fritter DRAM has lot of superiority in the chip of HDTV receiver.

It has been generally acknowledged that the shortcoming of dram chip makes it not be suitable for telecommunication circuit.The shortcoming of dram chip mainly contains: 1. DRAM read-write control is complicated, reads control circuits such as all wanting the row, column address decoding with write operation; 2. DRAM need refresh; 3. write complex time owing to reading, read or write speed is slow.

The innovation finds that by analyzing these shortcomings of DRAM are relevant with its application scenario.Usually, there are these shortcomings in DRAM; But be applied to data interlacing, when deinterleaving this class telecommunication circuit, these shortcomings of DRAM do not exist, this is the misunderstandings of people to DRAM.

The interleaver number of memory cells is kbit more than 40 among the HDTV, uses RAM to realize that memory capacity is kbit more than 80, and (more than the 16Mbit) compares very little with the DRAM capacity.Therefore, can save row, column control, only with primary address decoding, highly sensitive sense amplifier is can polygamy a little.

Owing to saved twice decoding in row, column address in the reading and writing sequential, change the primary address decoded mode of common RAM into, the control timing of DRAM is also uncomplicated, and read or write speed also can improve greatly, can satisfy the requirement of interleaver among the HDTV, i.e. reading and writing are finished about 25ns.

To the problem that refreshes, the unit of not reading also not write for a long time among the DRAM must refresh.And interleave circuit read and write constantly.From above knowing, arbitrary unit between reading and writing the longest time interval be below the 4mS, and the time interval that current DRAM must refresh is more than the 16mS.Therefore, the memory of DRAM structure is used in this occasion just not to be needed to refresh much smaller than the time interval that DRAM must refresh the longest time interval between reading and writing in arbitrary unit.

Owing to do not need to refresh; Do not need twice decoding in row, column address, the major defect of DRAM has not just existed, thus DRAM is used in data interlacing, be very suitable in deinterleaving.Compare with SRAM or register, will greatly reduce resources of chip consumption, reduce chip area, reduce the cost.

The circuit that use DRAM realization data interlacing, deinterleaves is similar with the circuit that uses dual port RAM realization data interlacing, deinterleave.Use the control of same address, allow DRAM finish write-once and read, just finished data interlacing or deinterleave.

If dedicated IC chip is done in channel-decoding and demodulation part in the HDTV receiver, remove the data part that deinterleaves, scale is about 300,000.If the data deinterleave circuit adopts the d type flip flop scheme, scale is about 200,000; If adopt the SRAM scheme, scale is about 8.5 ten thousand.It is that serviceability etc. on technical difficulty or the function all should be relative less important part that data deinterleave circuit itself is compared with error correction circuit etc., but has taken too big chip area.Use DRAM to realize the data deinterleave circuit, the chip area of equivalence drops to below 10,000, is a kind of scheme preferably.

Claims (3)

1, a kind of dynamic ram that adopts is realized data interlacing and the method that deinterleaves,

It is characterized in that:

In transmitter, the data that interweave are from the input input of dynamic ram, after postponing, output output from this dynamic ram, said delay is to distribute control to realize by the I/O address to said dynamic ram according to the interleaving scheme that will carry out, thereby finishes interleaving process;

In receiver, import from the input of dynamic ram according to the data that said process has interweaved, after postponing, output output from this dynamic ram, said delay is by the I/O address of said dynamic ram is realized according to the distribution control opposite with performed distribution control in the transmitter, thereby finishes the process of deinterleaving.

2, realize data interlacing and the method that deinterleaves according to a kind of dynamic ram that adopts of claim 1, it is characterized in that: the said interleaving scheme that will carry out is the interleaving scheme of GA-HDTV.

3, realize data interlacing and the method that deinterleaves according to a kind of dynamic ram that adopts of claim 2, it is characterized in that:

The end that writes at RAM: the 0th data do not postpone by interleaver as the 1 road signal, No. 0 unit of the RAM that then writes direct; The 1st data need postpone 1 * 4 * 52=208 byte clock as the 2 road signal by interleaver, then write the 1+208=209 unit of RAM; I (0≤i≤51) data need postpone i * 4 * 52=i * 208 a byte clock as i+1 road signal by interleaver, then write No. 208 unit, i+i * of RAM; The 51st data need postpone 51 * 4 * 52=10608 byte clock as the 52 road signal by interleaver, then write the 51+10608=10659 unit of RAM; Then, original position is got back in the position of the switch of the input of interleaver, so the 52nd data do not have just write direct No. 52 unit of RAM of delay as the 1 road signal; The 53rd data then need postpone 1 * 4 * 52=208 byte clock as the 2 road signal by interleaver, then write the 53+208=261 unit of RAM; So to K (K＞=0) data, need postpone Kmod52 * 4 * 52=Kmod52 * 208 byte clocks by interleaver, and write the AddrIn unit of RAM: AddrIn=K+Kmod52 * 208 as Kmod52+1 road signal

At the end of reading of two-port RAM, press from 0,1,2 ... call over each unit, thereby also just make each data be postponed just to have finished interleave function accordingly.

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