CN106529099A - Method for automatically generating verification model on the basis of interface - Google Patents
Method for automatically generating verification model on the basis of interface Download PDFInfo
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- CN106529099A CN106529099A CN201611186583.7A CN201611186583A CN106529099A CN 106529099 A CN106529099 A CN 106529099A CN 201611186583 A CN201611186583 A CN 201611186583A CN 106529099 A CN106529099 A CN 106529099A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The invention discloses a method for automatically generating a verification model on the basis of an interface. In an interface file, all input and output signals of a tested design module are defined, required signal identification is verified, and a verification model module code and an output checking module code are generated by a script program according to contents defined according to the interface file; after testing incentive data is sent to the verification model module, the verification model module calculates an output result and temporarily stores the output result to one queue; after the testing incentive data is sent to the tested design module, the output result is generated after a certain time period; and when the output enable signal of the tested design module is effective, the output checking module takes out the output result, which is temporarily stored in the queue, of the verification model module, and compares the output result with the output result of the tested design module. By use of the method, a chip verification workload brought by the multi-time update of SPEC (Specification) in chip development can be greatly reduced, and a chip development and research period is effectively shortened.
Description
Technical field
The present invention relates to communication technical field chips verification technique, and in particular to one kind automatically generates checking based on interface
The method of model.
Background technology
In asic chip development process, the functional specification book SPEC of chip generally has the renewal of many versions, therewith
What is come is being repeated for chip checking, and chip checking team needs to update verification platform according to newest SPEC, including to original
There is the change inspection of interface, increasing the definition of interface and signal, data/address bus encoding and decoding, and the interface to no longer existing newly is carried out
Delete etc., this will generally consume the substantial amounts of time and efforts of chip checking personnel.Traditional checking model is focused on testing mostly
The realization of the process and the result of card, for the above-mentioned checking model maintenance problem brought because SPEC updates not
Propose good solution.
The content of the invention
For the deficiencies in the prior art, present invention is primarily targeted at：Propose it is a kind of be based on module interface and SPEC from
The method of movable property life checking model, automatically generates signal definition, data/address bus coding and decoding, signal turnover according to interface document
Control of queue and the outgoing inspection of checking model and tested design, so as to greatly accelerate the checking of module.
To realize object defined above, the invention discloses a kind of method for automatically generating checking model based on interface, concrete to wrap
Include：
The all of input and output signal of tested design module, and the signal post needed for checking are defined in interface document
Know, content creating verification model module code and outgoing inspection block code that shell script is defined according to interface document；
Test and excitation sends excited data to checking model module and tested design module respectively；
After test stimulus data is sent to checking model module, checking model module calculates output result, keeps in at one
In queue；
After test stimulus data is sent to tested design module, through certain hour cycle, produce output result；
When tested design output enable signal it is effective when, outgoing inspection module is by the checking model being temporarily stored in the queue
Module output result is taken out, and is compared with the output result of tested design module.
Preferably, the signal identification needed for the definition checking includes：
Identical keyword is known in the coherent signal subscript for realizing same SPEC functions, carry out results contrast for determining
The essential information of range of signal and definition output queue；
Mark function corresponding with SPEC or task on signal are enabled in the output of tested design module, for determining
Corresponding functional module corresponding queue name in checking model module in SPEC；
The output signal subscript for entering particular queue in checking model module is being needed to know corresponding queue name, for processing
In SPEC it is undefined but it is tested design module have output signal comparison；
Encoding and decoding filename and bus name are identified on output data bus, the coding for generating data/address bus is conciliate
Code.
Preferably, the queue name enables signal according to output and produces.
Compared with prior art, it is an advantage of the current invention that：One kind disclosed by the invention automatically generates checking based on interface
The method of model, by adding information in interface document, automatically generates the output knot in checking model based on the interface document
The work such as fruit is compared, the definition of signal and queue, the encoding and decoding of signal bus, can greatly reduce as in chip development, SPEC is more
The secondary workload for updating the chip checking for bringing, effectively shortens the R＆D cycle of chip.
Description of the drawings
Fig. 1 is a kind of schematic diagram that checking model is automatically generated based on interface that one embodiment of the invention is proposed；
Fig. 2 is one embodiment of the invention proposition for the tested design module of certain functional realiey in SPEC and checking model
Automation comparison procedure schematic diagram.
Specific embodiment
In view of deficiency of the prior art, inventor Jing studies for a long period of time and puts into practice in a large number, is able to propose the present invention's
Technical scheme.The technical scheme, its implementation process and principle etc. will be further explained as follows.
The present invention proposes a kind of method for automatically generating checking model based on interface, the interface text produced based on tested design
Part, adds the various information produced needed for chemical examination model of a syndrome automatically in interface document, reuses shell script generation and chemically examines automatically
The code of model of a syndrome, reaches the purpose for accelerating checking.
Fig. 1 is a kind of schematic diagram that checking model is automatically generated based on interface that the embodiment of the present invention is proposed, such as Fig. 1 institutes
Show, interface document is connected to test and excitation module, tested design module, checking model module and outgoing inspection module, wherein testing
Model of a syndrome module and outgoing inspection module have collectively constituted the automatic checking model produced based on interface document.Its concrete association is closed
It is to be：Interface document defines all of input and output signal of tested design module, and the signal identification needed for checking, pin
This program automatically generates checking model module code and outgoing inspection block code according to interface document content.Test and excitation module
Test stimulus data is sent to checking model module and tested design module respectively, when excitation is sent in checking model module
Afterwards, its corresponding function modularity function meeting instant computing goes out output result, then the result is kept in into queue at；Excitation is sent out
After being sent in tested design module, through a clock cycle, the output result of the module is finally obtained；When tested design module
When output enable signal is effective, the result of calculation of the checking model module stored in above-mentioned queue is taken out by outgoing inspection module,
It is compared with the output result of tested design module, is achieved in the outgoing inspection for automating.
Wherein, the signal identification needed for the definition checking is specifically included：
1. identical keyword is known in the coherent signal subscript for realizing same SPEC functions, carry out results contrast for determining
Range of signal and define output queue essential information；
2. corresponding function or task in SPEC is identified on output enable signal, for determining corresponding function in SPEC
Module corresponding queue name in checking model module；
3. needing the output signal subscript for entering particular queue in checking model module to know corresponding queue name, for locating
Reason in SPEC it is undefined but it is tested design module have output signal comparison；
If some special output signals are being needed into special team in checking model module in tested design module
Row, then identify the queue name in correspondence output signal.
4. encoding and decoding filename and bus name are identified on output data bus, for generating the coding reconciliation of data/address bus
Code.
If certain signal is obtained by internal multiple signals combination, need to be defined into the coding information of the combination and connect
In mouth file, the checking model module for otherwise generating cannot produce this kind of signal corresponding with tested design module.
According to the definition of each signal in interface document, determining for each signal in checking model module can be automatically generated
Justice, without the need for carrying out manual modification to signal name and bit wide.By the related information of the addition checking in interface document, script journey
Sequence is automatically generated the definition of signal, data/address bus coding and decryption, signal turnover control of queue and is tested based on the interface document
Output result in model of a syndrome is compared with the output result automation of tested design, so as to complete automatic Verification.
In order that the objects, technical solutions and advantages of the present invention become more apparent, below in conjunction with accompanying drawing and it is embodied as
Example, the present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only to explain this
It is bright, it is not intended to limit the present invention.
Tested design module and checking model are elaborated below by way of a specific embodiment carries out automation comparison procedure,
Fig. 2 is comparing for the tested design of certain functional realiey in SPEC and the automation of checking model for one embodiment of the invention proposition
Journey schematic diagram, as shown in Figure 2：
After excitation is sent in checking model functional module, its corresponding function modularity function meeting instant computing goes out output knot
Really, then the result is kept in into queue at；
After excitation is sent in tested design function module, through a clock cycle, the output of the module is finally obtained
As a result；
When tested design function module output enable signal is effective, outgoing inspection functional module will be stored in above-mentioned queue
The result of calculation of checking model functional module take out, be compared with the output result of tested design function module, it is thus real
The outgoing inspection for now automating.
Specifically, according to the 1st article of information in above-described embodiment, realize to all correlations for comparing are needed in same function
Signal is compared in the lump, and the definition to output queue；According to above-mentioned 2nd article of information, it may be determined that corresponding in SPEC
The corresponding queue name of functional module and checking model functional module, thus verifies that model functional module can confirm that input signal belongs to
Should compare with the result of which queue in which queue, and the output signal of tested design function module, wherein queue
Name enables signal name according to the output of tested design function module and produces；According to above-mentioned 3rd article of information, can be used to process
Without definition in SPEC, and tested design function module has the comparison of the distinctive signal of output, for this signal, chemically examines automatically
Model of a syndrome can take out expected result from respective queue when being compared, and carry out with the output result of tested design function module
Relatively；According to above-mentioned 4th article of information, can be with the coding of automatically generated data bus and decoding, for some assembly codings of correspondence
The signal of generation.According to the 1st, the 2nd and the 3rd article of information, be just capable of achieving for the tested design of a certain functional realiey in SPEC and
The automation of checking model is compared.
The method for automatically generating checking model based on interface proposed using the embodiment of the present invention, only needs docking port file to enter
Row definition, without the need for verifying that model internal interface be modified, greatly reducing in chip development due to many renewals of SPEC
The workload that the checking model modification for bringing and chip are verified repeatedly, and then it is effectively shortened the R＆D cycle of chip.
It should be appreciated that above-described embodiment technology design only to illustrate the invention and feature, its object is to allow and are familiar with this
The personage of item technology will appreciate that present disclosure and implement according to this, can not be limited the scope of the invention with this.It is all
The equivalence changes made according to spirit of the invention or modification, should all be included within the scope of the present invention.
Claims (3)
- It is 1. a kind of that the method for verifying model is automatically generated based on interface, it is characterised in that：The all of input and output signal of tested design module, and the signal identification needed for checking are defined in interface document, Content creating verification model module code and outgoing inspection block code that shell script is defined according to interface document；Test and excitation sends excited data to checking model module and tested design module respectively；After test stimulus data is sent to checking model module, checking model module calculates output result, keeps in queue at In；After test stimulus data is sent to tested design module, through certain hour cycle, produce output result；When tested design output enable signal it is effective when, outgoing inspection module is by the checking model module being temporarily stored in the queue Output result is taken out, and is compared with the output result of tested design module.
- 2. it is according to claim 1 that the method for verifying model is automatically generated based on interface, it is characterised in that the definition is tested Signal identification needed for card includes：Identical keyword is known in the coherent signal subscript for realizing same SPEC functions, for determining the signal for carrying out results contrast The essential information of scope and definition output queue；Mark function corresponding with SPEC or task on signal are enabled in the output of tested design module, for determining in SPEC Corresponding functional module corresponding queue name in checking model module；The output signal subscript for entering particular queue in checking model module is being needed to know corresponding queue name, for processing In SPEC it is undefined but it is tested design module have output signal comparison；Encoding and decoding filename and bus name are identified on output data bus, for generating coding and the decoding of data/address bus.
- It is 3. according to claim 2 that the method for verifying model is automatically generated based on interface, it is characterised in that：The queue name Signal is enabled according to output to produce.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110188389A (en) * | 2019-04-28 | 2019-08-30 | 上海芷锐电子科技有限公司 | A kind of functional verification structure for artificial intelligence process device chip |
| CN111045948A (en) * | 2019-12-13 | 2020-04-21 | 盛科网络（苏州）有限公司 | Method, apparatus and storage medium for checking interface signal between modules |
| CN112560393A (en) * | 2020-12-17 | 2021-03-26 | 中科芯云微电子科技有限公司 | Comparison verification method and device of EDA software tool |
| CN112988602A (en) * | 2021-04-30 | 2021-06-18 | 北京欣博电子科技有限公司 | Verification platform generation method and device, computer equipment and storage medium |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101008915A (en) * | 2006-12-29 | 2007-08-01 | 深圳市明微电子有限公司 | Automatic verification method of network chip |
| CN101008962A (en) * | 2006-12-29 | 2007-08-01 | 深圳市明微电子有限公司 | Verification method for configurable and replaceable reference model used by network chip |
| CN101183406B (en) * | 2007-12-25 | 2010-06-30 | 盛科网络（苏州）有限公司 | Method for establishing network chip module level function checking testing platform |
| CN102117344A (en) * | 2009-12-30 | 2011-07-06 | 上海华虹集成电路有限责任公司 | Method realizing SIM (subscriber identity module) card chip multi-interface system verification environment |
| CN102957553A (en) * | 2011-08-25 | 2013-03-06 | 中兴通讯股份有限公司 | Method and device for automatic generation of excitation codes |
| CN105677990A (en) * | 2016-01-11 | 2016-06-15 | 盛科网络（苏州）有限公司 | Method for simplifying verification model implementation in chip verification |
| CN105975726A (en) * | 2016-05-27 | 2016-09-28 | 四川省豆萁科技股份有限公司 | Verification method and platform based on SystemVerilog language |
-
2016
- 2016-12-20 CN CN201611186583.7A patent/CN106529099A/en not_active Withdrawn
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101008915A (en) * | 2006-12-29 | 2007-08-01 | 深圳市明微电子有限公司 | Automatic verification method of network chip |
| CN101008962A (en) * | 2006-12-29 | 2007-08-01 | 深圳市明微电子有限公司 | Verification method for configurable and replaceable reference model used by network chip |
| CN101183406B (en) * | 2007-12-25 | 2010-06-30 | 盛科网络（苏州）有限公司 | Method for establishing network chip module level function checking testing platform |
| CN102117344A (en) * | 2009-12-30 | 2011-07-06 | 上海华虹集成电路有限责任公司 | Method realizing SIM (subscriber identity module) card chip multi-interface system verification environment |
| CN102957553A (en) * | 2011-08-25 | 2013-03-06 | 中兴通讯股份有限公司 | Method and device for automatic generation of excitation codes |
| CN105677990A (en) * | 2016-01-11 | 2016-06-15 | 盛科网络（苏州）有限公司 | Method for simplifying verification model implementation in chip verification |
| CN105975726A (en) * | 2016-05-27 | 2016-09-28 | 四川省豆萁科技股份有限公司 | Verification method and platform based on SystemVerilog language |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110188389A (en) * | 2019-04-28 | 2019-08-30 | 上海芷锐电子科技有限公司 | A kind of functional verification structure for artificial intelligence process device chip |
| CN111045948A (en) * | 2019-12-13 | 2020-04-21 | 盛科网络（苏州）有限公司 | Method, apparatus and storage medium for checking interface signal between modules |
| CN112560393A (en) * | 2020-12-17 | 2021-03-26 | 中科芯云微电子科技有限公司 | Comparison verification method and device of EDA software tool |
| CN112560393B (en) * | 2020-12-17 | 2023-01-24 | 中科芯云微电子科技有限公司 | Comparison verification method and device of EDA software tool |
| CN112988602A (en) * | 2021-04-30 | 2021-06-18 | 北京欣博电子科技有限公司 | Verification platform generation method and device, computer equipment and storage medium |
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