CN106510755A - Method of ultrasonic medical apparatus to detect received signals - Google Patents
Method of ultrasonic medical apparatus to detect received signals Download PDFInfo
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- CN106510755A CN106510755A CN201510582098.0A CN201510582098A CN106510755A CN 106510755 A CN106510755 A CN 106510755A CN 201510582098 A CN201510582098 A CN 201510582098A CN 106510755 A CN106510755 A CN 106510755A
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Abstract
The invention relates to the technical field of ultrasonic medical apparatuses, and in particular discloses a method of an ultrasonic medical apparatus to detect received signals. The method of the ultrasonic medical apparatus to detect the received signals provided by the invention has the advantages that the ultrasonic medical apparatus is characterized by comprising a receiving probe for receiving the signals, an FPGA (field programmable gate array) module and an MCU (programmed control unit) module which is connected to the FPGA module; the FPGA module can generate a PWM (pulse-width modulation) signal, and the PWM signal, after undergoing detection and rectification, participates in subtraction with the amplitude of a received analog signal; it is regarded that the PWM signal and the received analog signal are equal when the absolute value of a difference between the signals is less than a designated value, and correspondingly, the pulse width of the PWM is the amplitude of the received analog signal; and when the difference is greater than the designated value, it is regarded that the the PWM signal and the received analog signal are unequal, and the pulse width of the PWM is regulated until the signals are equal. The application of an AD conversion chip, which is relatively expense, is avoided, so that circuit cost is greatly reduced.
Description
Technical field
The present invention relates to ultrasonic medical Instrument technology field, particularly relates to a kind of method that ultrasonic medical instrument detection receives signal.
Background technology
The circuit hardware structure that traditional medical ultrasonic instrument detection receives signal amplitude is as shown in Figure 1, as FPGA/CPLD modules do not have internal AD conversion module, after the amplified circuit of signal for receiving is amplified, into AD conversion chip, AD conversion chip is by numerical data output to FPGA/CPLD modules, FPGA/CPLD modules carry out subsequent treatment again, and external AD conversion chip price is higher, can increase the hardware cost of circuit.
The content of the invention
It is an object of the invention to provide a kind of method that ultrasonic medical instrument detection receives signal, employs a certain amount of software control and calculates, compared with the medical ultrasonic instrument of the independent AD conversion chip of traditional employing, save cost to a certain extent.
To achieve these goals, present invention employs following technical scheme：A kind of method that ultrasonic medical instrument detection receives signal, including the MCU module of the receiving transducer, FPGA/CPLD modules and FPGA/CPLD modules connection for receiving signal；
Again through diode D1, electric capacity C1 detection rectifications after the amplified circuit amplification of signal that the receiving transducer is received, subtraction sign-changing amplifier U1 is entered as deduction item successively Jing resistance R1 from the reverse input end of subtraction sign-changing amplifier U1, constitute subtractor；
The pwm signal of the FPGA/CPLD modules output, Jing after detection rectification and reverse amplification circuit that resistance R3, operational amplifier U2 are constituted, enters subtraction sign-changing amplifier U1 as by deduction item Jing resistance R2；
The outfan of the subtraction sign-changing amplifier U1 is connected respectively to the reverse input end of these three comparators of U3, U4, U5, and the positive input of U3, U4, U5 these three comparators connects V ,-V and 0 respectively（Ground）These three level, the outfan of tri- comparators of U3, U4, U5 then connect three inputs of FPGA/CPLD modules respectively.
Wherein, difference E of subtraction is exported by U1, is compared in comparator U3 and U4 with designated value V and-V respectively, while E is also compared in U5 with zero, result of the comparison is input into FPGA/CPLD modules respectively for comparator U3, U4 and U5, and FPGA/CPLD modules are judged to which.
Wherein, FPGA/CPLD modules adopt following flow process, complete the amplitude adjustment of output pwm signal, and finally determine corresponding input signal amplitude, i.e.,：The initial value of pulse width is 50% duty ratio, if meeting 0≤E<V or-V<E<0 condition, then stop adjustment, draw the amplitude for receiving signal, then restart next wheel measurement；If being unsatisfactory for above-mentioned condition, if E<0, then duty ratio is brought up to into 75%, duty ratio is reduced to into 25% otherwise, then is judged.Judge that the principle that duty ratio changes is every time：It is assumed that existing duty ratio is Dn, if E<0, then duty ratio be revised as Dn+1=Dn+50%* (1-Dn)；If Dn+1=50%*Dn is revised as in E >=0, duty ratio.Modify according to mentioned above principle, until meeting 0≤E<V or-V<E<0 this condition, then draw signal amplitude value, and epicycle adjustment terminates, and Dn is returned to the initial value of 50% duty ratio, starts next round test.
The beneficial effects of the present invention is：After said system, AD conversion chip is not adopted, pwm signal is produced by FPGA/CPLD modules, amplitude subtraction after detection rectification with the analogue signal for receiving, as long as the value that the absolute value of difference is specified less than some, be considered as that two-value is equal, now the pulse width of PWM just it is corresponding be the analogue signal for receiving amplitude；If difference be more than the designated value, be considered as two-value, need to be adjusted the pulsewidth of PWM, until two-value it is equal.The AD conversion chip higher due to eliminating price, circuit cost significantly can decline.
Description of the drawings
In order to be illustrated more clearly that embodiment of the present invention technical scheme, accompanying drawing to be used needed for describing to embodiment below is briefly described, apparently, drawings in the following description are only the present invention to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below accompanying drawing to be used needed for p- embodiment or description of the prior art is briefly described, for those of ordinary skill in the art, on the premise of not paying creative work, can be with according to these other accompanying drawings of accompanying drawings acquisition.
Fig. 1 is the circuit hardware structure chart that traditional medical ultrasonic instrument detection receives signal amplitude；
Fig. 2 is the circuit hardware structure chart of the present invention；
Fig. 3 is the software flow pattern that the FPGA/CPLD modules of the present invention adjust pulse width.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.Based on the embodiment in the present invention, the every other embodiment obtained under the premise of creative work is not made by those of ordinary skill in the art belongs to the scope of protection of the invention.
The method that a kind of ultrasonic medical instrument detection as shown in Figure 1 receives signal, probe receives signal, after amplified circuit amplifies, Jing resistance R1 again, the detection rectification constituted with U2 and the output signal of sign-changing amplifier are linked together Jing after resistance R2, the reverse input end of the subtraction sign-changing amplifier constituted as U1, the positive input ground connection of U1, the outfan and reverse input end of feedback resistance R6 connection U1.The outfan of U1 is connected respectively to the reverse input end of these three comparators of U3, U4, U5, and the positive input of these three comparators connects V ,-V and 0 respectively（Ground）These three level.The outfan of three comparators then connects three inputs of FPGA/CPLD modules respectively.
Pwm signal is produced by FPGA or CPLD, the amplitude subtraction after detection rectification with the analogue signal for receiving, the absolute value of difference are less than some value specified, is considered as that two-value is equal, now the pulse width of PWM just it is corresponding be the analogue signal that receives amplitude；If difference be more than the designated value, be considered as two-value, need to be adjusted the pulsewidth of PWM, until two-value it is equal.
AD conversion chip is saved, using operational amplifier and comparator, and passes through FPGA or CPLD control pulse widths output pwm signal；It is compared with input signal amplitude in a comparator after pwm signal detection rectification；Comparative result is input into FPGA or CPLD again, goes to control the pulse amplitude of pwm signal.It is final that corresponding reception signal amplitude value is obtained according to satisfactory pulse width.
The method for judging satisfactory pulse width, i.e. after receive pulse amplitude and PWM detection rectifications it is concurrent it is big after the absolute value of difference of signal when being less than a certain designated value, the pulse width of PWM just stops adjustment, and the corresponding signal amplitude of pulse width now is exactly the amplitude for receiving signal.
The pulse width of FPGA or CPLD adjustment PWM simultaneously finally determines the software flow for receiving signal amplitude.Implement process as follows：Again through D1, C1 rectification after the amplified device amplification of signal for receiving, the subtractor that amplifier U1 is constituted is entered as deduction item Jing resistance R1, and the pwm signal of FPGA or CPLD outputs, Jing after detection rectification and reverse amplification circuit that amplifier U2 is constituted, U1 is entered as by deduction item Jing resistance R2.Difference E of subtraction is exported by U1, is compared in comparator U3 and U4 with designated value V and-V respectively, while E is also compared in U5 with zero, the output of this 3 comparators respectively enters FPGA or CPLD, FPGA or CPLD is judged to which, if 0≤E<V or-V<E<0, illustrate the absolute value of now difference E of subtraction less than difference V specified, then now the corresponding amplitude of pwm pulse width is exactly the actual margin of input signal；Otherwise, continue adjustment pulse width, until meeting above-mentioned condition.By the method that pulse width is mapped with signal actual margin it is：Signal amplitude, then the pwm pulse width for surveying now corresponding steady statue are received with oscillograph actual measurement.It is linear with the pwm pulse width of steady statue due to receiving signal amplitude, can just show that unit pulse width is corresponding and receive signal amplitude value AP, if pulse width stable after adjusting every time is PW, the amplitude for receiving signal is exactly AM=AP*PW.The software flow of FPGA or CPLD adjustment pulse widths is as shown in figure 3, can so shorten adjustment time.Idiographic flow is as follows：The initial value of pulse width is 50% duty ratio, if meeting 0≤E<V or-V<E<0 condition, then stop adjustment, according to aforesaid method, draws the amplitude for receiving signal, then restarts next wheel measurement；If being unsatisfactory for above-mentioned condition, if E<0, then duty ratio is brought up to into 75%, duty ratio is reduced to into 25% otherwise, then is judged.Judge that the principle that duty ratio changes is every time：It is assumed that existing duty ratio is Dn, if E<0, then duty ratio be revised as Dn+1=Dn+50%* (1-Dn)；If Dn+1=50%*Dn is revised as in E >=0, duty ratio.Modify according to mentioned above principle, until meeting 0≤E<V or-V<E<0 this condition, then draw signal amplitude value, and epicycle adjustment terminates, and Dn is returned to the initial value of 50% duty ratio, starts next round test.
Presently preferred embodiments of the present invention is the foregoing is only, not to limit the present invention, all any modification, equivalent substitution and improvements within the spirit and principles in the present invention, made etc., be should be included within the scope of the present invention.
Claims (3)
1. a kind of method that ultrasonic medical instrument detection receives signal, it is characterised in that：Including the MCU module of the receiving transducer, FPGA/CPLD modules and FPGA/CPLD modules connection for receiving signal；
Again through diode D1, electric capacity C1 detection rectifications after the amplified circuit amplification of signal that the receiving transducer is received, subtraction sign-changing amplifier U1 is entered as deduction item successively Jing resistance R1 from the reverse input end of subtraction sign-changing amplifier U1, constitute subtractor；
The pwm signal of the FPGA/CPLD modules output, Jing after detection rectification and reverse amplification circuit that resistance R3, operational amplifier U2 are constituted, enters subtraction sign-changing amplifier U1 as by deduction item Jing resistance R2；
The outfan of the subtraction sign-changing amplifier U1 is connected respectively to the reverse input end of these three comparators of U3, U4, U5, and the positive input of U3, U4, U5 these three comparators connects V ,-V and 0 these three level respectively, the outfan of tri- comparators of U3, U4, U5 then connects three inputs of FPGA/CPLD modules respectively.
2. a kind of method that ultrasonic medical instrument detection receives signal according to claim 1, it is characterised in that：Difference E of subtraction is exported by U1, it is compared in comparator U3 and U4 with designated value V and-V respectively, E is also compared in U5 with zero simultaneously, and result of the comparison is input into FPGA/CPLD modules respectively for comparator U3, U4 and U5, and FPGA/CPLD modules are judged to which.
3. a kind of method that ultrasonic medical instrument detection receives signal according to claim 1, it is characterised in that：FPGA/CPLD modules adopt following flow process, complete the amplitude adjustment of output pwm signal, and finally determine corresponding input signal amplitude, i.e.,：The initial value of pulse width is 50% duty ratio, if meeting 0≤E<V or-V<E<0 condition, then stop adjustment, draw the amplitude for receiving signal, then restart next wheel measurement；If being unsatisfactory for above-mentioned condition, if E<0, then duty ratio is brought up to into 75%, duty ratio is reduced to into 25% otherwise, then is judged.
Judge that the principle that duty ratio changes is every time：It is assumed that existing duty ratio is Dn, if E<0, then duty ratio be revised as Dn+1=Dn+50%* (1-Dn)；If Dn+1=50%*Dn is revised as in E >=0, duty ratio.
Modify according to mentioned above principle, until meeting 0≤E<V or-V<E<0 this condition, then draw signal amplitude value, and epicycle adjustment terminates, and Dn is returned to the initial value of 50% duty ratio, starts next round test.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510582098.0A CN106510755A (en) | 2015-09-14 | 2015-09-14 | Method of ultrasonic medical apparatus to detect received signals |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106953599A (en) * | 2017-03-27 | 2017-07-14 | 长沙云涯电子科技有限责任公司 | Circuit occurs for output-stage circuit and amplitude modulation physiotherapy electrical stimulation signal |
| CN108494387A (en) * | 2018-03-26 | 2018-09-04 | 慈溪市中发灯饰有限公司 | It can operation type PWM generation circuits |
| CN109938771A (en) * | 2019-03-30 | 2019-06-28 | 河南省省立医院有限公司 | Three-dimensional basin baselap acoustic image processing control system |
| CN115831342A (en) * | 2023-02-16 | 2023-03-21 | 杭州康晟健康管理咨询有限公司 | Medical data information acquisition and processing device, chip and equipment |
| CN116846372A (en) * | 2023-07-04 | 2023-10-03 | 广州联航科电气机械有限公司 | Alternating-current charging pile control guide PWM (pulse-Width modulation) generation and detection circuit |
-
2015
- 2015-09-14 CN CN201510582098.0A patent/CN106510755A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106953599A (en) * | 2017-03-27 | 2017-07-14 | 长沙云涯电子科技有限责任公司 | Circuit occurs for output-stage circuit and amplitude modulation physiotherapy electrical stimulation signal |
| CN108494387A (en) * | 2018-03-26 | 2018-09-04 | 慈溪市中发灯饰有限公司 | It can operation type PWM generation circuits |
| CN108494387B (en) * | 2018-03-26 | 2022-04-19 | 慈溪市中发灯饰有限公司 | Operational PWM generating circuit |
| CN109938771A (en) * | 2019-03-30 | 2019-06-28 | 河南省省立医院有限公司 | Three-dimensional basin baselap acoustic image processing control system |
| CN115831342A (en) * | 2023-02-16 | 2023-03-21 | 杭州康晟健康管理咨询有限公司 | Medical data information acquisition and processing device, chip and equipment |
| CN116846372A (en) * | 2023-07-04 | 2023-10-03 | 广州联航科电气机械有限公司 | Alternating-current charging pile control guide PWM (pulse-Width modulation) generation and detection circuit |
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Application publication date: 20170322 |