CN106470175B - A kind of baseband chip and signal processing method - Google Patents
A kind of baseband chip and signal processing method Download PDFInfo
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- CN106470175B CN106470175B CN201510515423.1A CN201510515423A CN106470175B CN 106470175 B CN106470175 B CN 106470175B CN 201510515423 A CN201510515423 A CN 201510515423A CN 106470175 B CN106470175 B CN 106470175B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
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Abstract
The embodiment of the invention discloses a kind of baseband chips, comprising: CPU array, soft core array and hardware basic unit, the CPU array, the soft core array are connected with the hardware basic unit by bus；CPU array, for sending first task to soft core array, which is that chip handles task；Soft core array, for first task to be sent to hardware basic unit；Hardware basic unit, for executing first task.The embodiment of the present invention further simultaneously discloses a kind of signal processing method.
Description
Technical field
The present invention relates to the wireless access technologys more particularly to a kind of baseband chip and signal processing in wireless communication field
Method.
Background technique
Wireless access technology based on Code Division Multiple Access is widely used in field of wireless communication, and is existing
The important component of wireless access technology.As the depth of internet is flourishing, wireless data traffic is just jumbo with exponential curve
Increase, wireless access way demand is also more and more.So, how quick dilatation, and how according to user demand, efficiently
Customize personalized access device, especially while being finally embodied as user and improving more preferable experience, reduce exploitation cost,
Risk and period.These problems are put forward new requirements to cellular carrier, especially radio equipment manufacturer.
Baseband processing portion is also a wherein vital ring in the radio reception device of Code Division Multiple Access, especially
Chip processing therein part often restricts whole equipment because its real-time, integral operation performance and design difficulty are higher
The important link of performance and function.The chip processing part of the radio reception device of existing Code Division Multiple Access mainly has following several
Kind implementation:
1, field programmable gate array (FPGA, Field-Programmable Gate Array)
With can field programming FPGA realize baseband functions, its advantage is that design can be rapidly completed, and easily scalable
It updates, the disadvantage is that at high cost, FPGA is also controlled by several big giants, and the design area in contexture by self space is limited.
2, specific integrated circuit (ASIC, Application Specific Integrated Circuit)
Most mature implementation method is pure ASIC.Because Code Division Multiple Access drill by comparative maturity, the technology based on ASIC
Into also perfect day by day for many years, its advantage is that cost is extremely low, but disadvantage is also apparent from: the development cycle is long, and difficulty is big, capacity boost or
Person's design area will receive the restriction that ASIC solidifies framework.
3, central processing unit array (CPU, Central Processing Unit)+ASIC
With CPU array+ASIC realize chip processing, substantially be occupy the advanced CPU array in upper layer (such as microprocessor ARM,
Advanced RISC Machines)) resource come complete chip processing part work.Its advantage is that by existing system on chip
Part ASIC function is become software processing by the CPU array of (SOC, System on Chip) platform, reduces difficulty and risk,
Convenient for updating upgrading, the disadvantage is that being often repetitive schedule or inquiry with this partial function of software replacement, CPU array can be consumed
Vast resources, power consumption is big, and cost performance is low.
Therefore, it is designed for Base-Band Processing chip part in the radio reception device of Code Division Multiple Access, in the prior art
The problems such as existing development difficulty is big, the period is long, power consumption or design area are obvious by restriction and defect urgent need to resolve.
Summary of the invention
In order to solve the above technical problems, an embodiment of the present invention is intended to provide a kind of baseband chip and signal processing method, energy
The design difficulty for enough reducing baseband chip, the design area of baseband chip and power consumption are greatly reduced, base band is thereby reduced
The development cycle of chip.
The technical scheme of the present invention is realized as follows:
The embodiment of the present invention provides a kind of baseband chip, and the baseband chip includes: central processor CPU array, soft core
Array and hardware basic unit, the CPU array, the soft core array are connected with the hardware basic unit by bus；
The CPU array, for sending first task to the soft core array, the first task is that chip processing is appointed
Business；
The soft core array, for the first task to be sent to the hardware basic unit；
The hardware basic unit, for executing the first task.
In above-mentioned baseband chip, the soft core array is also used to after the CPU array transmission first task, by institute
It states first task to be sent to before the hardware basic unit, configures at least one subtask for the first task, formed
Task list including at least one subtask.
In above-mentioned baseband chip, the baseband chip further include: direct memory access DMA and memory；The DMA with
The hardware basic unit connection, the DMA are connect by the bus with the soft core array, and the memory passes through described
Bus is connect with the soft core array and the hardware basic unit respectively；
The soft core array is specifically used for being sent corresponding at least one described subtask according to the task list
Order is moved to the DMA, the every height moving order and being used to indicate in described at least one described subtask of DMA transmission
Task is to the hardware basic unit, and instruction has been after the hardware basic unit has handled each subtask, institute
DMA feedback is stated to interrupt to the soft core array；
The DMA, for sending each subtask to the hardware basic unit；
The hardware basic unit is tied specifically for executing each subtask respectively, and by each subtask
Fruit stores in memory；
The DMA is also used to detect the hardware basic unit to the processing status and the processing of a subtask
State is to send described interrupt to the soft core array when completing；
The soft core array, is also used to respond the interruption, and appointing for one subtask is obtained from the memory
Business as a result, and auxiliary function processing is carried out to the task result of one subtask, and auxiliary function processing result is stored
To the memory；
The DMA is also used to report the auxiliary function processing result in the memory, with carry out symbol level or
Bit-level processing.
In above-mentioned baseband chip, the soft core array is also used to after the CPU array transmission first task, sends
It is corresponding at least one described subtask move order to the DMA before, detect the caching shape of the hardware basic unit
State；
When the soft core array also particularly useful for the buffer status of the hardware basic unit is detected is idle, send
It is corresponding at least one described subtask to move order to the DMA.
It include random access memory ram and First Input First Output in the soft core array in above-mentioned baseband chip
FIFO memory；At least one described subtask includes at least one subtask request and at least one described subtask ginseng
Number；
The FIFO memory, for storing at least one subtask request；
The RAM, for storing at least one described subtask parameter.
The embodiment of the present invention provides a kind of signal processing method, which comprises
The first task that soft core array received central processor CPU array is sent, the first task are that chip processing is appointed
Business；
The first task is sent to hardware basic unit by the soft core array, for hardware basic unit execution
The first task.
In the above scheme, after the first task that the soft core array received CPU array is sent, the soft core array will
The first task is sent to before hardware basic unit, the method also includes:
The first task is configured at least one subtask by the soft core array, and being formed includes at least one described son
The task list of task；
Correspondingly, the first task is sent to hardware basic unit by the soft core array, comprising:
For the soft core array according to the task list, transmission is corresponding at least one described subtask to move order extremely
The DMA, so that the DMA sends each subtask to the hardware basic unit and the hardware basic unit point
Each subtask is not executed, and in memory by each subtask result storage, it is described to move order for referring to
Show that the DMA sends each subtask at least one described subtask to the hardware basic unit, and instruction is in institute
It states after hardware basic unit handled each subtask, the DMA feedback is interrupted.
In the above scheme, it is described send it is corresponding at least one described subtask move order to the DMA after,
The method also includes:
The DMA detects the hardware basic unit and is to the processing status of subtask and the processing status
When completion, the interruption of the transmission of DMA described in the soft core array received；
It is interrupted described in the soft core array response, the task result of one subtask is obtained from the memory,
And auxiliary function processing is carried out to the task result of one subtask, and auxiliary function processing result is stored to described and is deposited
Reservoir, so that the DMA reports the auxiliary function processing result in the memory, to carry out symbol level or bit-level
Processing.
In the above scheme, after the first task that the soft core array received CPU array is sent, the soft core array root
According to the task list, send it is corresponding at least one described subtask move order to the DMA before, the method is also
Include:
The buffer status of hardware basic unit described in the soft core array detection.
In the above scheme, the soft core array is sent and at least one described subtask pair according to the task list
That answers moves order to the DMA, comprising:
When the buffer status of the soft core array detection to the hardware basic unit is idle, arranged according to the task
Table, transmission is corresponding at least one described subtask to move order to the DMA.
The embodiment of the invention provides a kind of baseband chip and signal processing method, the baseband chip include: CPU array,
Soft core array and hardware basic unit, the CPU array, the soft core array are connected with the hardware basic unit by bus；CPU gusts
Column, for sending first task to soft core array, which is that chip handles task；Soft core array, being used for will be first
Business is sent to hardware basic unit；Hardware basic unit, for executing first task.Using above-mentioned technic relization scheme, i.e. base
Microarray strip realizes chip processing using CPU array+soft core array+hardware basic unit framework, due to only calculating chip core
Method is realized in a hardware basic unit, and realizes that chip handles task by soft core array scheduling hardware basic unit, this
The design difficulty of the baseband chip of sample design is low, just greatly reduces the design area of baseband chip and power consumption, and then base band
The development cycle of chip just reduces.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of illustrative baseband chip in the prior art；
Fig. 2 is a kind of structural schematic diagram one of baseband chip provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram one of hardware basic unit provided in an embodiment of the present invention；
Fig. 4 is the structural schematic diagram two of hardware basic unit provided in an embodiment of the present invention；
Fig. 5 is a kind of structural schematic diagram two of baseband chip provided in an embodiment of the present invention；
Fig. 6 is a kind of structural schematic diagram three of baseband chip provided in an embodiment of the present invention；
Fig. 7 is a kind of flow chart one of signal processing method provided in an embodiment of the present invention；
Fig. 8 is a kind of flowchart 2 of signal processing method provided in an embodiment of the present invention；
Fig. 9 is a kind of flow chart 3 of signal processing method provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description.
Existing central processing unit array (CPU, Central Processing Unit)+specific integrated circuit (ASIC,
Application Specific Integrated Circuit) structure of chip processing is realized as shown in Figure 1, CPU array is logical
It crosses bus (BUS) and ASIC carries out data interaction, wherein five functional may be implemented in ASIC, wherein n1-n5, which is respectively indicated, to be needed
Five functional modules are wanted to need the quantity using A；C1-C5 respectively indicates the auxiliary function except five functional modules removing A, A
For the core algorithm part of chip.
Since despreading has been completed in A, the data transfer rate of auxiliary function C1-C5 has been greatly reduced, so the embodiment of the present invention is adopted
With software realization (soft core array).
Embodiment one
As shown in Fig. 2, the embodiment of the present invention provides a kind of baseband chip 1, which includes: CPU array 10, soft
Core array 11 and hardware basic unit 12, the CPU array 10, the soft core array 11 and the hardware basic unit 12 pass through
Bus 13 connects.
The CPU array 10, for sending first task to the soft core array, the first task is that chip processing is appointed
Business.
The soft core array 11, for the first task to be sent to the hardware basic unit 12.
The hardware basic unit 12, for executing the first task.
It should be noted that the background of application of the embodiment of the present invention are as follows: base in the radio reception device of Code Division Multiple Access
Tape handling part chip therein handles part, mainly carries out chip processing using baseband chip, and the embodiment of the present invention mentions
The baseband chip 1 of confession realizes chip processing using CPU array+soft core array+hardware basic unit framework.
Further, as shown in figure 3, the hardware basic unit 12 includes: antenna interpolation 120, antenna descrambling 121, day
The submodules such as line despreading 122, frequency deviation compensation 123；Alternatively, as shown in figure 4, the hardware basic unit 12 includes: symbol mapping
124,125 are scrambled plus expands 126, multiply the submodules such as power 127.
It should be noted that will support the hard of the core algorithm processing of chip-level in baseband chip 1 in the embodiment of the present invention
Part part is used as hardware basic unit 12.The core of the structural support uplink chip-level of hardware basic unit 12 shown in Fig. 3
Center algorithm processing, the core algorithm processing of the structural support downlink chip-level of hardware basic unit 12 shown in Fig. 4.Therefore, originally
The baseband chip 1 that inventive embodiments provide can determine to use the knot of hardware basic unit 12 according to the type of actual treatment signal
Structure.
It is understood that the hardware basic unit in the embodiment of the present invention is will be in hardware structure in the prior art
Chip core algorithm part is used by merging and integrating composition using hardware basic unit as hardware resource pool.
Illustratively, as shown in Figure 1, in existing hardware structure, respectively indicating five functional modules of needs by n1-n5 is needed
The tricks of A is used, C1-C5 respectively indicates the auxiliary function except five functional modules removing A, wherein A is exactly chip core
Algorithm；In the embodiment of the present invention, using A as hardware basic unit, realize different number A's using the method that soft core array calls
Scheduling, complete chip core algorithm, then in soft core array complete C1-C5 auxiliary function processing.
Optionally, the soft core array 11 in the embodiment of the present invention is the soft core battle array of firmware formed using simple processor
Column, the specific can be that the simple CPU array such as M series processors of arm, it being capable of supporting bus agreement (AXI, Advanced
EXtensible Interface), the common bus such as peripheral bus (APB, Advanced Peripheral Bus), so as to
Upper layer CPU array and the communication of lower hardware basic unit.
It should be noted that the first task in the embodiment of the present invention refers to doing chip to baseband signal (aerial signal)
The task of processing includes first task request in first task and first task parameter (i.e. what function is characterization baseband signal will do
The chip processing of energy).
Further, hardware basic unit 12 carries out the processing of the core algorithm of chip-level.
Optionally, the soft core array 11 is also used to after the transmission of CPU array 10 first task, by described first
Task is sent to before the hardware basic unit 12, configures at least one subtask for the first task, formation includes
The task list of at least one subtask.
It should be noted that baseband signal to be treated, i.e. aerial signal in the embodiment of the present invention, can be at least one
Section aerial signal, therefore, what CPU array 10 was sent is the chip processing task of at least one section aerial signal；In soft core array 11
In, the chip processing task of every a kind of function of each section of aerial signal is divided into a subtask, soft core battle array by soft core array 11
Column 11 complete at least one corresponding subtask of at least one aerial signal by the scheduling to hardware basic unit.
Optionally, as shown in figure 5, including random access memory ram 110 and first in, first out in the soft core array 11
Queue FIFO memory 111；At least one described subtask include at least one subtask request and it is described at least one
Subtask parameter.
The FIFO memory 111, for storing at least one subtask request.
The RAM 110, for storing at least one described subtask parameter.
It should be noted that soft core array it is multiple it is internuclear do not communicate, realize data friendship by shared RAM or by FIFO
Mutually.
Particularly, CPU array 10 configures basic task (first task) to soft core array 11.Soft core array 11 will be divided into
The request of at least one subtask is fitted in the respective FIFO memory 111 of soft core of soft core array 11, will an at least subtask
In the RAM 110 that parameter configuration is shared to soft core.
Specifically, soft core array reads at least one subtask request in FIFO memory 111, task column are then established
Table, the task list are the task list for including at least one subtask.
It optionally, include the respective subtask mark at least one subtask in above-mentioned task list.Specific subtask
The form and manifestation mode of mark, the embodiment of the present invention is with no restriction.
Optionally, as shown in fig. 6, the baseband chip 1 further include: direct memory access DMA 14 and memory 15；Institute
It states DMA 14 to connect with the hardware basic unit 12, the DMA 14 is connected by the bus 13 and the soft core array 11
It connects, the memory 15 is connect with the soft core array 11 and the hardware basic unit 12 respectively by the bus 14.
The soft core array 11 is specifically used for being sent corresponding at least one described subtask according to the task list
Move order to the DMA 14, it is described move order and be used to indicate the DMA 14 send at least one described subtask
Each subtask to the hardware basic unit 12, and instruction has handled every height in the hardware basic unit 12
After task, the feedback of DMA 14 is interrupted to the soft core array 11.
The DMA 14, for sending each subtask to the hardware basic unit 12.
The hardware basic unit 12, specifically for executing each subtask respectively, and by each subtask
As a result it is stored in memory 15.
The DMA 14 is also used to detect processing status of the hardware basic unit 12 to a subtask, Yi Jisuo
When stating processing status to complete, described interrupt to the soft core array 11 is sent.
The soft core array 11, is also used to respond the interruption, obtains one subtask from the memory 15
Task result, and auxiliary function processing is carried out to the task result of one subtask, and by auxiliary function processing result
It stores to the memory 15.
The DMA 14 is also used to report the auxiliary function processing result in the memory 15, to be accorded with
Number grade or bit-level processing.
It should be noted that the function of DMA 14 is exactly to be dispatched by soft core array 11, it is used to direct and hardware basic unit
12 interactions, that is, move the task parameters that soft core array 11 to be issued and data and parameter that hardware basic unit 12 to be reported.
Specifically, DMA 14 detect hardware basic unit 12 can be with to the implementation of the processing status of a subtask
Are as follows: DMA 14 detects the value of the processing flag bit in hardware basic unit 12 to judge processing status, for example, DMA 14 is detected firmly
Processing spacing wave in part basic unit 12 characterizes a subtask and does not complete when handling spacing wave is 1；When the empty letter of processing
When number being 0, characterizes subtask and complete.
It should be noted that DMA 14 detects hardware basic unit 12 to the implementation of the processing status of a subtask
It can be realized using the various ways of the prior art, the embodiment of the present invention is with no restriction.
Optionally, the soft core array 11 is also used to after the CPU array 10 sends first task, send with it is described
At least one subtask is corresponding move order to the DMA 14 before, detect the caching shape of the hardware basic unit 12
State.
When the soft core array 11 also particularly useful for the buffer status of the hardware basic unit 12 is detected is idle,
Transmission is corresponding at least one described subtask to move order to the DMA 14.
It should be noted that the hardware basic unit 12 in the embodiment of the present invention is used as hardware resource pool,
In the state that the caching of hardware basic unit 12 is available free, soft core array 11 issues subtask to hardware basic unit 12.Example
Such as, first task is divided into 10 subtasks by soft core array 11, and soft core array 11 detects the slow of hardware basic unit 12
Deposit that state is available free, can support the implementation of 2 subtasks, therefore, soft core array 11 just by DMA 14 issue 2 subtasks to
Hardware basic unit 12 is first handled, and until the caching of the hardware basic unit 12 is again the free time, then issues other subtasks.
Specifically, the buffer status implementation that soft core array 11 detects hardware basic unit 12 can be with are as follows: soft core array
11 detect the value of the cache tag position of hardware basic units 12 to judge buffer status, for example, soft core array detection hardware is basic
The non-full signal of unit 12, when non-full signal is 1, the caching of characterization hardware basic unit 12 has been expired；When non-full signal is 0
When, the caching for characterizing hardware basic unit 12 is less than.
It should be noted that the buffer status implementation that soft core array 11 detects hardware basic unit 12 can be using existing
There are the various ways of technology to realize, the embodiment of the present invention is with no restriction.
It is understood that for Base-Band Processing chip part design in the radio reception device of Code Division Multiple Access, this
Inventive embodiments devise a kind of based on CPU array+soft core array (simple processor array)+hardware basic unit (stone frame
Structure) baseband chip, it is original based on pure stone, pure soft core or CPU array+stone framework baseband chip to substitute, because
This, the power consumption and area of chip are greatly reduced, and chip design difficulty and development cycle are greatly reduced.Since soft core array 11 can be with
Subtask is issued side by side to hardware basic unit 12, and therefore, flow success rate greatly improves, and it is quickly fixed to be also convenient for providing for user
Exploration project processed provides quick upgrade expanding.
Further, the sequence that soft core array 11 issues subtask and is is carried out according to task list, when soft core array
11 when judging subtask to be issued, and by according to the sequence of task list, by the mark for needing the subtask issued and moves life
Order is sent to DMA 14, which can identify corresponding subtask parameter from RAM for subtask according to order is moved
Read out, and the request of corresponding subtask, subtask and subtask parameter transmitted to hardware basic unit 12, with into
The processing of row chip.
Further, the process that soft core array 11 issues subtask can be what timing issued, therefore, when soft core array 11
Detect that the buffer status of hardware basic unit 12 for the free time, and reaches when issuing the period, soft core array 11, which just issues, moves life
It enables to DMA 14.
Further, the first task that CPU array 10 is sent to soft core array 11 can be a fixed task packet, this
When, soft core array 11 ends task as long as having handled the task in this task packet.If the first of the transmission of CPU array 10
Task is ceaselessly task always, then, soft core array 11 is exactly the carrying out the configuration of CPU array 10 always of the task.But it is soft
The method that core array 11 executes task is all above-mentioned process.
Baseband chip provided by the embodiment of the present invention, the baseband chip include: CPU array, soft core array and hardware base
This unit, the CPU array, the soft core array are connected with the hardware basic unit by bus；CPU array is used for soft core battle array
Column send first task, which is that chip handles task；Soft core array, it is basic for first task to be sent to hardware
Unit；Hardware basic unit, for executing first task.Using above-mentioned technic relization scheme, i.e. baseband chip uses CPU array
The framework of+soft core array+hardware basic unit realizes chip processing, due to only that chip core algorithm is substantially single in a hardware
It is realized in member, and realizes that chip handles task by soft core array scheduling hardware basic unit, the baseband chip designed in this way
Design difficulty is low, just greatly reduces the design area of baseband chip and power consumption, and then the development cycle of baseband chip just drops
It is low.
Embodiment two
The embodiment of the present invention provides a kind of signal processing method, as shown in fig. 7, this method may include:
The first task that S101, soft core array received CPU array are sent, it is that chip handles task that this, which states first task,.
It should be noted that the background of application of the embodiment of the present invention are as follows: base in the radio reception device of Code Division Multiple Access
Tape handling part chip therein handles part, mainly carries out chip processing using baseband chip, and the embodiment of the present invention mentions
The baseband chip 1 of confession realizes chip processing using CPU array+soft core array+hardware basic unit framework.
Optionally, the soft core array in the embodiment of the present invention is the soft core battle array of firmware formed using simple processor
Column, the specific can be that the simple CPU array such as M series processors of arm, can support the common bus such as AXI, APB, so as to
Upper layer CPU array and the communication of lower hardware basic unit.
It should be noted that the first task in the embodiment of the present invention refers to doing chip to baseband signal (aerial signal)
The task of processing includes that (i.e. what function is baseband signal will do with first task parameter for first task request in first task
Chip processing).
In embodiments of the present invention, the first task that soft core array received CPU array is sent, it is by base that this, which states first task,
The task of band signal progress chip processing.
First task is sent to hardware basic unit by S102, soft core array, for hardware basic unit execute this first
Task.
After the first task that soft core array received CPU array is sent, which is sent to hardware for first task
Basic unit, so that hardware basic unit executes the first task, so that hardware basic unit carries out the core algorithm of chip-level
Processing.
Further, as shown in figure 3, the hardware basic unit 12 includes: antenna interpolation 120, antenna descrambling 121, day
The submodules such as line despreading 122, frequency deviation compensation 123；Alternatively, as shown in figure 4, the hardware basic unit 12 includes: symbol mapping
124,125 are scrambled plus expands 126, multiply the submodules such as power 127.
It should be noted that will support the hard of the core algorithm processing of chip-level in baseband chip in the embodiment of the present invention
Part part is used as hardware basic unit.The core of the structural support uplink chip-level of hardware basic unit 12 shown in Fig. 3
Algorithm process, the core algorithm processing of the structural support downlink chip-level of hardware basic unit 12 shown in Fig. 4.Therefore, this hair
The baseband chip that bright embodiment provides can determine to use the structure of hardware basic unit according to the type of actual treatment signal.
It is understood that the hardware basic unit in the embodiment of the present invention is will be in hardware structure in the prior art
Chip core algorithm part is used by merging and integrating composition using hardware basic unit as hardware resource pool.
Illustratively, as shown in Figure 1, in existing hardware structure, respectively indicating five functional modules of needs by n1-n5 is needed
The tricks of A is used, C1-C5 respectively indicates the auxiliary function except five functional modules removing A, wherein A is exactly chip core
Algorithm；In the embodiment of the present invention, using A as hardware basic unit, realize different number A's using the method that soft core array calls
Scheduling, complete chip core algorithm, then in soft core array complete C1-C5 auxiliary function processing.
A kind of information processing method provided by the embodiment of the present invention, soft core array received CPU array are sent first
Business, the first task are that chip handles task；First task is sent to hardware basic unit by soft core array, for the hardware base
This unit executes first task.Using above-mentioned technic relization scheme, baseband chip is basic using CPU array+soft core array+hardware
The framework of unit realizes chip processing, due to only realizing chip core algorithm in a hardware basic unit, and by soft
Core array scheduling hardware basic unit realizes that chip handles task, and the design difficulty of the baseband chip designed in this way is low, just by base
The design area and power consumption of microarray strip greatly reduce, and then the development cycle of baseband chip just reduces.
Embodiment three
A kind of signal processing method provided by the embodiment of the present invention, as shown in figure 8, this method may include:
The first task that S201, soft core array received CPU array are sent, the first task are that chip handles task.
It should be noted that the background of application of the embodiment of the present invention are as follows: base in the radio reception device of Code Division Multiple Access
Tape handling part chip therein handles part, mainly carries out chip processing using baseband chip, and the embodiment of the present invention mentions
The baseband chip of confession realizes chip processing using CPU array+soft core array+hardware basic unit framework.
Optionally, the soft core array in the embodiment of the present invention is the soft core battle array of firmware formed using simple processor
Column, the specific can be that the simple CPU array such as M series processors of arm, can support the common bus such as AXI, APB, so as to
Upper layer CPU array and the communication of lower hardware basic unit.
It should be noted that the first task in the embodiment of the present invention refers to doing chip to baseband signal (aerial signal)
The task of processing includes that (i.e. what function is baseband signal will do with first task parameter for first task request in first task
Chip processing).
In embodiments of the present invention, the first task that soft core array received CPU array is sent, it is by base that this, which states first task,
The task of band signal progress chip processing.
Further, the first task that CPU array is sent to soft core array can be a fixed task packet, at this moment,
Soft core array ends task as long as having handled the task in this task packet.If the first task that CPU array is sent is
Ceaselessly task always, then, soft core array is exactly the carrying out CPU array configuration always of the task.But soft core array executes
The method of task is all the process of signal processing provided in an embodiment of the present invention.
First task is configured at least one subtask by S202, soft core array, and being formed includes at least one subtask
Task list.
After the first task that soft core array received CPU array is sent, which configures first task at least
One subtask, and form the task list including at least one subtask.
Particularly, CPU array is to soft core array configuration basic task (first task).Soft core array will be divided at least one
A sub- task requests are fitted in the respective FIFO memory of soft core of soft core array, will an at least sub- task parameters be configured to it is soft
In the shared RAM of core.
It should be noted that baseband signal to be treated, i.e. aerial signal in the embodiment of the present invention, can be at least one
Section aerial signal, therefore, what CPU array was sent is the chip processing task of at least one section aerial signal；It is soft in soft core array
The chip processing task of every a kind of function of each section of aerial signal is divided into a subtask by core array, soft core array by pair
At least one corresponding subtask of at least one aerial signal is completed in the scheduling of hardware basic unit.
Specifically, soft core array reads at least one subtask request in FIFO memory, task list is then established,
The task list is the task list for including at least one subtask.
It optionally, include the respective subtask mark at least one subtask in above-mentioned task list.Specific subtask
The form and manifestation mode of mark, the embodiment of the present invention is with no restriction.
S203, soft core array according to task list, send it is corresponding at least one subtask move order to DMA,
Each subtask is executed respectively so that the DMA sends each subtask to hardware basic unit and the hardware basic unit, and
In memory by each subtask result storage, this, which is moved order and is used to indicate the DMA, sends at least one subtask
In each subtask to the hardware basic unit, and instruction the hardware basic unit handled each subtask it
Afterwards, DMA feedback is interrupted.
First task is configured at least one subtask by soft core array, forms the task including at least one subtask
After list, for the soft core array according to task list, transmission is corresponding at least one subtask to move order to DMA.
Specifically, soft core array, according to task list, transmission is corresponding with the mark of at least one subtask to move life
It enables to DMA.
It should be noted that DMA sends each subtask to hardware basic unit；Hardware basic unit executes each respectively
Subtask so that hardware basic unit carries out the processing of the core algorithm of chip-level, and each subtask result is stored in
In reservoir；It is when completing, to send to the processing status of subtask and the processing status that DMA, which detects hardware basic unit,
It interrupts to soft core array.
Further, as shown in figure 3, the hardware basic unit 12 includes: antenna interpolation 120, antenna descrambling 121, day
The submodules such as line despreading 122, frequency deviation compensation 123；Alternatively, as shown in figure 4, the hardware basic unit 12 includes: symbol mapping
124,125 are scrambled plus expands 126, multiply the submodules such as power 127.
It should be noted that will support the hard of the core algorithm processing of chip-level in baseband chip in the embodiment of the present invention
Part part is used as hardware basic unit.The core of the structural support uplink chip-level of hardware basic unit 12 shown in Fig. 3
Algorithm process, the core algorithm processing of the structural support downlink chip-level of hardware basic unit 12 shown in Fig. 4.Therefore, this hair
The baseband chip that bright embodiment provides can determine to use the structure of hardware basic unit according to the type of actual treatment signal.
It is understood that the hardware basic unit in the embodiment of the present invention is will be in hardware structure in the prior art
Chip core algorithm part is used by merging and integrating composition using hardware basic unit as hardware resource pool.
Illustratively, as shown in Figure 1, in existing hardware structure, respectively indicating five functional modules of needs by n1-n5 is needed
The tricks of A is used, C1-C5 respectively indicates the auxiliary function except five functional modules removing A, wherein A is exactly chip core
Algorithm；In the embodiment of the present invention, using A as hardware basic unit, realize different number A's using the method that soft core array calls
Scheduling, complete chip core algorithm, then in soft core array complete C1-C5 auxiliary function processing.
What S204, DMA detected hardware basic unit is to complete to the processing status of subtask and the processing status
When, the interruption of soft core array received DMA transmission.
Soft core array according to task list, send with this at least one subtask is corresponding move order to DMA after,
What DMA detected hardware basic unit is soft core array when completing to the processing status of subtask and the processing status
Receive the interruption of DMA transmission.
It should be noted that the function of DMA is exactly to be dispatched by soft core array, it is used to directly and hardware basic unit is interactive,
Move the task parameters that soft core array to be issued and data and parameter that hardware basic unit to be reported.
Specifically, DMA detect hardware basic unit can be with to the implementation of the processing status of a subtask are as follows: DMA
The value of the processing flag bit in hardware basic unit is detected to judge processing status, for example, in DMA detection hardware basic unit
Spacing wave is handled, when handling spacing wave is 1, a subtask is characterized and does not complete；When handling spacing wave is 0, one is characterized
It completes subtask.
It should be noted that DMA detect hardware basic unit can be with to the implementation of the processing status of a subtask
It is realized using the various ways of the prior art, the embodiment of the present invention is with no restriction.
S205, soft core array response interrupt, and the task result of a subtask are obtained from memory, and appoint to a son
The task result of business carries out auxiliary function processing, and auxiliary function processing result is stored to memory, so that DMA is by the storage
Auxiliary function processing result in device reports, to carry out symbol level or bit-level processing.
After the interruption that soft core array received DMA is sent, due to completing a subtask by hardware basic unit
Chip core algorithm, but the auxiliary function of a subtask is handled not yet, and therefore, soft core array response interrupts, from depositing
The task result of a subtask is obtained in reservoir, and auxiliary function processing is carried out to the task result of a subtask, and will
Auxiliary function processing result is stored to memory, so that DMA reports the auxiliary function processing result in the memory, to carry out
Symbol level or bit-level processing.
Further, a kind of signal processing method provided by the embodiment of the present invention, as shown in figure 9, after S202, S203
Before, this method can also include: S206.It specifically includes:
The buffer status of S206, soft core array detection hardware basic unit.
First task is configured at least one subtask by soft core array, forms the task including at least one subtask
After list, when available free due to the caching in hardware basic unit, which can just issue subtask, and therefore, this is soft
Core array first detects the buffer status of hardware basic unit.
It should be noted that the hardware basic unit in the embodiment of the present invention is used as hardware resource pool, hard
In the state that the caching of part basic unit is available free, soft core array issues subtask to hardware basic unit.For example, soft core battle array
First task is divided into 10 subtasks by column, and the buffer status of soft core array detection to hardware basic unit is available free, can
To support the implementation of 2 subtasks, therefore, soft core array just passes through DMA and issues 2 subtasks first to be handled to hardware basic unit,
Until the caching of the hardware basic unit is again the free time, then issue other subtasks.
Specifically, the buffer status implementation of soft core array detection hardware basic unit can be with are as follows: soft core array detection
The value of the cache tag position of hardware basic unit judges buffer status, for example, soft core array detection hardware basic unit is non-
Full signal, when non-full signal is 1, the caching of characterization hardware basic unit has been expired；When non-full signal is 0, hardware base is characterized
The caching of this unit is less than.
It should be noted that the buffer status implementation of soft core array detection hardware basic unit can use existing skill
The various ways of art realize that the embodiment of the present invention is with no restriction.
It is understood that for Base-Band Processing chip part design in the radio reception device of Code Division Multiple Access, this
Inventive embodiments devise a kind of based on CPU array+soft core array (simple processor array)+hardware basic unit (stone frame
Structure) baseband chip, it is original based on pure stone, pure soft core or CPU array+stone framework baseband chip to substitute, because
This, the power consumption and area of chip are greatly reduced, and chip design difficulty and development cycle are greatly reduced.Since soft core array can be simultaneously
Column issue subtask to hardware basic unit, and therefore, flow success rate greatly improves, and are also convenient for providing fast custom for user and open
Hair project provides quick upgrade expanding.
Further, the sequence that soft core array issues subtask and is is carried out according to task list, when soft core array is sentenced
It is disconnected go out when issuing subtask, by according to the sequence of task list, by the mark for needing the subtask issued and move order hair
DMA is given, which can identify corresponding subtask parameter for subtask and read out from RAM according to order is moved,
And the corresponding subtask request in subtask and subtask parameter are transmitted and give hardware basic unit, to carry out chip processing.
Further, the process that soft core array issues subtask can be what timing issued, therefore, when soft core array detection
Buffer status to hardware basic unit is the free time, and is reached when issuing the period, and soft core array, which just issues, moves order to DMA.
Specifically, S203 can be specific as follows after S206:
Buffer status when being idle of S203, soft core array detection to hardware basic unit, send and appoint at least one son
It is engaged in corresponding moving order to DMA.
After the buffer status of soft core array detection hardware basic unit, the soft core array detection to hardware basic unit
When buffer status is idle, which, which sends, corresponding at least one subtask moves order to DMA.
A kind of information processing method provided by the embodiment of the present invention, soft core array received CPU array are sent first
Business, the first task are that chip handles task；First task is sent to hardware basic unit by soft core array, for the hardware base
This unit executes first task.Using above-mentioned technic relization scheme, baseband chip is basic using CPU array+soft core array+hardware
The framework of unit realizes chip processing, due to only realizing chip core algorithm in a hardware basic unit, and by soft
Core array scheduling hardware basic unit realizes that chip handles task, and the design difficulty of the baseband chip designed in this way is low, just by base
The design area and power consumption of microarray strip greatly reduce, and then the development cycle of baseband chip just reduces.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program
Product.Therefore, the shape of hardware embodiment, software implementation or embodiment combining software and hardware aspects can be used in the present invention
Formula.Moreover, the present invention, which can be used, can use storage in the computer that one or more wherein includes computer usable program code
The form for the computer program product implemented on medium (including but not limited to magnetic disk storage and optical memory etc.).
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention.
Claims (10)
1. a kind of baseband chip, which is characterized in that the baseband chip includes: central processor CPU array, soft core array and hard
Part basic unit, the CPU array, the soft core array are connected with the hardware basic unit by bus；
The CPU array, for sending first task to the soft core array, the first task is that chip handles task；
The soft core array, for the first task to be sent to the hardware basic unit；
The hardware basic unit, for executing the first task, to realize the chip core algorithm of first task；
Wherein, the soft core array is also used to execute the hardware basic unit task result progress that first task obtains
Auxiliary function processing, to realize that the auxiliary function to the first task is handled；Wherein, the auxiliary function refers to except chip core
Function except algorithm.
2. baseband chip according to claim 1, which is characterized in that
The soft core array is also used to after the CPU array transmission first task, the first task is sent to described hard
Before part basic unit, at least one subtask is configured by the first task, being formed includes at least one described subtask
Task list.
3. baseband chip according to claim 2, which is characterized in that the baseband chip further include: direct memory access
DMA and memory；The DMA is connect with the hardware basic unit, and the DMA is connected by the bus and the soft core array
It connects, the memory is connect with the soft core array and the hardware basic unit respectively by the bus；
The soft core array is specifically used for sending move corresponding at least one described subtask according to the task list
It orders to the DMA, each subtask moving order and being used to indicate in described at least one described subtask of DMA transmission
The extremely hardware basic unit, and indicate the DMA after the hardware basic unit has handled each subtask
Feedback is interrupted to the soft core array；
The DMA, for sending each subtask to the hardware basic unit；
The hardware basic unit is deposited specifically for executing each subtask respectively, and by each subtask result
Storage is in memory；
The DMA is also used to detect the hardware basic unit to the processing status and the processing status of a subtask
When to complete, described interrupt to the soft core array is sent；
The soft core array, is also used to respond the interruption, and the task knot of one subtask is obtained from the memory
Fruit, and auxiliary function processing is carried out to the task result of one subtask, and auxiliary function processing result is stored to institute
State memory；
The DMA is also used to report the auxiliary function processing result in the memory, to carry out symbol level or bit
Grade processing.
4. baseband chip according to claim 3, which is characterized in that
The soft core array is also used to after the CPU array transmission first task, sends and at least one described subtask pair
Before that answers moves order to the DMA, the buffer status of the hardware basic unit is detected；
When the soft core array also particularly useful for the buffer status of the hardware basic unit is detected is idle, send and institute
State that at least one subtask is corresponding to move order to the DMA.
5. according to the described in any item baseband chips of claim 2 to 4, which is characterized in that include random in the soft core array
Access memory RAM and first-in-first-out queue FIFO memory；At least one described subtask includes that at least one described son is appointed
Business request and at least one described subtask parameter；
The FIFO memory, for storing at least one subtask request；
The RAM, for storing at least one described subtask parameter.
6. a kind of signal processing method, which is characterized in that the described method includes:
The first task that soft core array received central processor CPU array is sent, the first task are that chip handles task；
The first task is sent to hardware basic unit by the soft core array, for described in hardware basic unit execution
First task, to realize the chip core algorithm of subtask；
Wherein, the soft core array executes the task result that first task obtains to the hardware basic unit and carries out auxiliary function
Processing, to realize that the auxiliary function to the first task is handled；Wherein, the auxiliary function refers in addition to chip core algorithm
Function.
7. according to the method described in claim 6, it is characterized in that, the soft core array received CPU array send it is first
After business, before the first task is sent to hardware basic unit by the soft core array, the method also includes:
The first task is configured at least one subtask by the soft core array, and being formed includes at least one described subtask
Task list；
Correspondingly, the first task is sent to hardware basic unit by the soft core array, comprising:
The soft core array according to the task list, send it is corresponding at least one described subtask move order to DMA,
For the DMA send each subtask to the hardware basic unit and the hardware basic unit execute respectively it is described every
A subtask, and in memory by each subtask result storage, it is described move order and be used to indicate the DMA send
Each subtask at least one described subtask is to the hardware basic unit, and instruction is in the hardware basic unit
After having handled each subtask, the DMA feedback is interrupted.
8. the method according to the description of claim 7 is characterized in that described send remove corresponding at least one described subtask
It moves after order to the DMA, the method also includes:
The DMA detects the hardware basic unit to the processing status of subtask and the processing status to complete
When, the interruption that DMA described in the soft core array received is sent；
It is interrupted described in the soft core array response, the task result of one subtask is obtained from the memory, and right
The task result of one subtask carries out auxiliary function processing, and auxiliary function processing result is stored to the storage
Device, so that the DMA reports the auxiliary function processing result in the memory, to carry out at symbol level or bit-level
Reason.
9. method according to claim 7 or 8, which is characterized in that the first of the soft core array received CPU array transmission
After task, for the soft core array according to the task list, transmission is corresponding at least one described subtask to move order
Before to the DMA, the method also includes:
The buffer status of hardware basic unit described in the soft core array detection.
10. according to the method described in claim 9, it is characterized in that, the soft core array according to the task list, send with
At least one described subtask is corresponding to move order to the DMA, comprising:
When the buffer status of the soft core array detection to the hardware basic unit is idle, according to the task list, hair
It send and corresponding at least one described subtask moves order to the DMA.
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| CN201510515423.1A CN106470175B (en) | 2015-08-20 | 2015-08-20 | A kind of baseband chip and signal processing method |
| PCT/CN2016/080978 WO2017028557A1 (en) | 2015-08-20 | 2016-05-04 | Baseband chip and signal processing method |
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| DE10158774A1 (en) * | 2001-11-30 | 2003-06-18 | Infineon Technologies Ag | Baseband chip with integrated real-time operating system functionality and method for operating a baseband chip |
| EP1680686A1 (en) * | 2003-09-02 | 2006-07-19 | Sirf Technology, Inc. | Signal processing system for satellite positioning signals |
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| CN1777076A (en) * | 2004-11-16 | 2006-05-24 | 深圳安凯微电子技术有限公司 | Baseband chip with access of time-division synchronous CDMA |
| CN101047927A (en) * | 2007-04-23 | 2007-10-03 | 北京中星微电子有限公司 | System and method for implementing mobile terminal baseband SOC |
| CN101123597A (en) * | 2007-07-06 | 2008-02-13 | 北京天碁科技有限公司 | A base band processing device for terminal |
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