CN106469648B - epitaxial structure and method - Google Patents

epitaxial structure and method Download PDF

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Publication number
CN106469648B
CN106469648B CN201510548833.6A CN201510548833A CN106469648B CN 106469648 B CN106469648 B CN 106469648B CN 201510548833 A CN201510548833 A CN 201510548833A CN 106469648 B CN106469648 B CN 106469648B
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opening
mask layer
epitaxial
substrate
layer
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CN106469648A (en
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邓震
王桂磊
杨涛
李俊峰
刘洪刚
赵超
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention provides an epitaxial structure and a method, comprising the following steps: a substrate; a first mask layer over a surface of the substrate, the first mask layer having at least one first opening to expose the surface of the substrate; the second mask layer is positioned on the first mask layer and is provided with a second opening which is positioned on the first opening and has a certain width and is not overlapped with the center position of the first opening; the third mask layer is positioned on the second mask layer and provided with a third opening which is positioned on the second opening and does not overlap with the center of the first opening in a certain width, and the transverse distance between the third opening and the first opening is within a certain range; an epitaxial layer. The epitaxial structure provided by the invention can prepare a high-quality epitaxial layer on a substrate with the lattice mismatch degree exceeding 4%.

Description

Epitaxial structure and method
Technical Field
the invention relates to the field of semiconductor manufacturing, in particular to an epitaxial structure and a method.
Background
in the field of semiconductor manufacturing, epitaxy refers to growing a single crystal layer with a certain requirement and the same crystal orientation as a substrate on a single crystal substrate as if the original crystal extended outward by a section, which is also called epitaxial growth.
Epitaxial growth is an important component of the semiconductor fabrication field. The new single crystal layer grown by epitaxy can be different from the substrate in the aspects of conductivity type, resistivity and the like, and can also be used for growing multiple layers of single crystals with different thicknesses and different requirements, so that the flexibility of device design and the performance of the device are greatly improved. The epitaxial process is also widely used in large scale integrated circuits to improve material quality, for example, when a high quality single crystal substrate of the material of the epitaxial layer to be obtained is difficult to obtain, or when cost is to be reduced, another material single crystal substrate with low lattice mismatch may be used for epitaxy to obtain the desired high quality epitaxial layer.
However, when the lattice mismatch exceeds 2%, for example, gallium nitride (GaN) and silicon carbide (SiC) substrates have a mismatch of 3.5%, it is difficult to obtain a high-quality epitaxial layer by the conventional technique. The prior art solves the above problems by means of lateral epitaxial overgrowth LEO technology, which comprises: the substrate is masked with a mask having a pattern of openings and then an epitaxial layer is grown such that the epitaxial layer passes through the openings and grows laterally over the mask. Tests have found that the quality of the epitaxial layer grown laterally over the mask is higher than the quality of the epitaxial layer at the opening. However, LEO technology also has difficulty in obtaining high quality epitaxial layers when the degree of mismatch between the epitaxial layer and the substrate exceeds 4%.
Disclosure of Invention
The invention provides an epitaxial structure and a method, which aim to solve the problem that the existing epitaxial technology is difficult to prepare a high-quality epitaxial layer on a substrate with the mismatch degree exceeding 4%.
The present invention provides an epitaxial structure comprising:
A substrate;
a first mask layer over a surface of the substrate, the first mask layer having at least one first opening to expose the surface of the substrate;
the second mask layer is positioned on the first mask layer, the thickness of the first opening is less than or equal to 3 times of that of the first opening, the second mask layer is provided with a second opening which is positioned on the first opening and does not overlap with the center of the first opening, and the width of the second opening is greater than that of the first opening;
The third mask layer is positioned on the second mask layer and provided with a third opening which is positioned on the second opening and does not overlap with the center of the first opening, the transverse distance between the third opening and the first opening is less than or equal to 2 times the width of the first opening or 2 times the width of the third opening, and the width of the third opening is less than the width of the second opening;
an epitaxial layer including epitaxial layer portions in the first opening, the second opening, and the third opening and epitaxial layer portions over the third mask layer.
Preferably, the ratio of the width of the first opening to the width of the third opening ranges from 50% to 150%.
Preferably, the epitaxial layer part above the third mask layer is a protruding epitaxial layer above the third opening, and is used for manufacturing a FINFET MOS device.
preferably, the epitaxial layer part above the third mask layer is a flat epitaxial layer above the third mask layer, and is used for manufacturing a planar device.
Preferably, the aspect ratio of the first opening and the third opening is: the depth-to-width ratio is more than or equal to 8 and more than or equal to 1.
an epitaxy method, comprising:
Providing a substrate;
forming a first mask layer with a first opening on the substrate;
depositing a second mask layer, wherein the thickness of the first opening is less than or equal to 3 times of the thickness of the second mask layer;
forming a third mask layer with a third opening on the second mask layer, wherein the third opening is not overlapped with the center position of the first opening, and the transverse distance between the third opening and the center position of the first opening is less than or equal to 2 times of the width of the first opening or 2 times of the width of the third opening;
Etching until the substrate at the first opening is completely exposed;
And carrying out epitaxial growth.
Preferably, the selective etching ratio of the second mask layer to the first mask layer and the third mask layer is greater than or equal to 20, and the etching rate of the second mask layer is the maximum.
Preferably, the performing epitaxial growth further comprises:
And growing a buffer layer with a certain thickness at a high speed before carrying out epitaxial growth.
preferably, the etching until the substrate at the first opening is completely exposed further includes:
and etching the substrate to form a pattern substrate.
preferably, the lattice mismatch degree between the epitaxial layer for epitaxial growth and the substrate is more than or equal to 4%, and the lattice mismatch degree is less than or equal to 25%.
The invention provides an epitaxial structure and a method, wherein the epitaxial structure comprises a first mask layer positioned on a substrate, and the mask layer is provided with a first opening to expose the surface of the substrate; and a second mask layer located on the first mask layer and having a thickness between the width of the first opening and 3 times the width of the first opening, the second mask layer having a second opening located on the first opening and having a center not overlapping the center of the first opening, the second opening having a width greater than the first opening; the third mask layer is positioned above the second mask layer and provided with a third opening which is positioned above the second opening and is not overlapped with the center of the first opening, the width of the third opening is smaller than that of the second opening, and the transverse distance between the third opening and the first opening is less than or equal to 2 times of the width of the first opening or 2 times of the width of the third opening; and an epitaxial layer part located in the first opening, the second opening, the third opening and above the third mask layer. According to the technical principle of LEO, the epitaxial layer with the lattice quality better than that of the epitaxial layer at the first opening can be epitaxially grown at the non-overlapping part of the second opening and the first opening, the defects such as epitaxial dislocation and the like in the second opening can be limited to extend upwards by the third mask layer outside the third opening, and meanwhile, the epitaxial layer with the lattice quality better than that of the epitaxial layer at the third opening can be epitaxially grown on the third mask layer outside the third opening, so that the epitaxial structure provided by the invention can be used for preparing the high-quality epitaxial layer on the substrate with the lattice mismatch degree of more than 4%.
Drawings
In order to more clearly illustrate the embodiments of the present application or technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a schematic cross-sectional structure of a prior art LEO technology epitaxial structure;
fig. 2 is a schematic cross-sectional structure diagram of an epitaxial structure provided in accordance with an embodiment of the present invention;
FIG. 3 is a flow chart of an epitaxy method provided in accordance with an embodiment of the invention;
Fig. 4 is a schematic cross-sectional perspective view of an epitaxial structure according to an embodiment of the present invention;
Fig. 5 to 9 are schematic cross-sectional views of devices during an epitaxy process according to an embodiment of the invention;
Fig. 10 is a schematic cross-sectional view of an epitaxial structure provided in accordance with an embodiment of the present invention;
Fig. 11 is a schematic cross-sectional view of an epitaxial structure according to a second embodiment of the invention;
fig. 12 to fig. 13 are schematic cross-sectional views of devices during epitaxy according to an epitaxy method provided in the third embodiment of the present invention;
Fig. 14 is a flowchart of an epitaxy method according to a third embodiment of the present invention;
fig. 15 is an X-ray two-crystal diffraction curve of an epitaxial structure according to an embodiment of the present invention and an epitaxial structure of the prior art.
Detailed Description
reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the applicability of other processes and/or the use of other materials. In addition, the structure of a first feature described below as "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
for a better understanding of the invention, a brief description of the prior art method for obtaining high quality epitaxial layers on substrates with a mismatch of more than 2% is first given below. In order to solve the above problems in the prior art, an LEO technique is generally used to obtain a high-quality epitaxial layer, and an epitaxial structure obtained by using the LEO technique includes: a mask layer having an opening and an epitaxial layer thereon are formed on a substrate as shown in fig. 1. The method for forming the epitaxial structure comprises the following steps: and depositing a mask layer on the substrate in advance or depositing the mask layer on the buffer layer to form a patterned substrate, and then performing epitaxial thin film growth.
according to the epitaxial structure and the method provided by the invention, dislocation upward extension is restrained by utilizing the dislocation limiting effect of the patterned substrate twice, and a high-quality epitaxial layer is prepared on the second patterned substrate, as shown in fig. 2, and the process method is described in detail below with reference to specific embodiments.
example one
In this embodiment, the first opening 1101, the second opening 1201 and the third opening 1301 are in a trench pattern.
an epitaxial structure, comprising: a substrate 100; and a first mask layer 110 over the surface of the substrate, the first mask layer 110 having at least one first trench pattern to expose the surface of the substrate; the second mask layer 120 is located on the first mask layer 110, the thickness of the second mask layer 120 is 2 times of the width of the first groove pattern, the second mask layer 120 is provided with a second groove pattern which is located on the first groove pattern and does not overlap with the center of the first groove pattern, and the width of the second groove pattern is 3 times of the width of the first groove pattern; the third mask layer 130 is located on the second mask layer 120, the third mask layer 130 is provided with a third groove pattern which is located on the second groove pattern and does not overlap with the center position of the first groove pattern, the transverse distance between the third groove pattern and the first groove pattern is 2 times of the width of the first groove pattern, and the width of the third groove pattern is equal to the width of the first groove pattern; and an epitaxial layer 140 including an epitaxial layer portion among the first trench pattern, the second trench pattern, and the third trench pattern and an epitaxial layer portion protruded above the third trench pattern. The raised epitaxial layer can be used to make FINFET MOS devices as shown in fig. 9. It should be noted that the convex portion of the epitaxial layer 140 can be formed naturally through epitaxial growth, and no special treatment is needed, for example, when the iii-v family material is grown by MOCVD, the vertical growth speed of the iii-v family material is far faster than the lateral growth speed, and the convex portion can be formed; in addition, the protruding portion may be formed by a special process, for example, by using the epitaxial method provided by the present invention, when the epitaxial layer 140 just fills the third trench, an etching solution having a high selective etching ratio to the third mask layer is selected, and the third mask layer 130 having a certain thickness is etched to form the protruding portion. The first mask layer 110 is a silicon nitride film, the second mask layer 120 is a silicon dioxide film, and the third mask layer 130 is a silicon nitride film. A schematic cross-sectional perspective view of an epitaxial structure is shown in fig. 4.
a flow chart of an epitaxy method for implementing the epitaxy structure is shown in fig. 3, and the epitaxy method includes:
step S01, providing a substrate 100;
Step S02, forming a first mask layer 110 having a first trench pattern on the substrate 100, as shown in fig. 5;
Step S03, depositing a second mask layer 120, where the thickness of the second mask layer 120 is 2 times the width of the first trench pattern, as shown in fig. 6;
Step S04, forming a third mask layer 130 having a third trench pattern over the second mask layer 120, where the third trench pattern does not overlap with the center of the first trench pattern, and a lateral distance between the third trench pattern and the center of the first trench pattern is 2 times a width of the first trench pattern, as shown in fig. 7;
Step S05, etching until the substrate at the first trench pattern is completely exposed, as shown in fig. 8;
In step S06, epitaxial growth is performed, as shown with reference to fig. 9.
it should be emphasized that the material of the second mask layer 120 is different from the material of the first mask layer 110 and the third mask layer 130, and the first mask layer 110 is to be used as an etching stop layer of the second mask layer 120, and the third mask layer 130 is not damaged as much as possible when the second mask layer 120 is etched, that is, the etching rate of the second mask layer 120 is the maximum. Further, the etching solution of the second mask layer 120 has a cleaning effect on the substrate 100, and is used for removing a natural oxide layer or a contaminant on the surface of the substrate 100 to ensure the epitaxial quality. For example, the substrate 100 is a silicon substrate, the first mask layer 110 may be a silicon nitride film deposited by a PECVD method, the second mask layer 120 may be a silicon dioxide film deposited by a CVD method, and the third mask layer 130 may be a silicon nitride film deposited by a PECVD method. The epitaxial layer 140 is a III-V material layer, a germanium layer, a tin layer, or a germanium-tin alloy layer. The lattice mismatch between the epitaxial layer 140 and the substrate 100 may exceed 4%, and the existing epitaxial method cannot obtain the high-quality epitaxial layer 140.
In addition, the etching is isotropic etching and over-etching to ensure that the material of the second mask layer 120 filled in the first trench pattern is completely removed, and to ensure that a part of the second mask layer is remained to be used as a support part of the third mask layer 130. Meanwhile, the etching solution of the silicon dioxide contains hydrofluoric acid, so that a natural oxide layer on the surface of the silicon substrate can be removed, and a fresh silicon substrate surface can be obtained when the silicon dioxide in the first groove pattern is removed, thereby being beneficial to epitaxial growth on the surface of the substrate 100.
Further, in order to obtain a high quality epitaxial layer 140, the aspect ratio of the first trench pattern and/or the third trench pattern is greater than 1.
it should be noted that the three mask layers are guaranteed to be stable under epitaxial conditions, for example, the softening temperature of the three mask layers should be higher than the epitaxial temperature.
of course, the silicon substrate is not limited to a bulk silicon substrate, but may be a silicon-on-insulator SOI substrate, etc., and is not limited herein. In addition, since the first mask layer 110 has a pattern, the surface may be uneven when forming the second mask layer 120, and if the subsequent steps require high surface flatness on the substrate 100, the second mask layer 120 may be planarized by a chemical mechanical planarization CMP process, which will not be described in detail herein.
in addition, the epitaxial layer 140 may also be an epitaxial layer portion with a flat surface on the third mask layer 130 and an epitaxial layer portion in the first trench pattern, the second trench pattern and the third trench pattern, as shown in fig. 10, which is not limited herein.
Example two
an epitaxial structure, as described in the first embodiment, is different in that the first opening 1101, the second opening 1201, and the third opening 1301 are circular hole patterns; the epitaxial portion near the substrate 100 further includes a thickness of a high-speed grown buffer layer 1401; the third mask layer 130 has a surface-planarized epitaxial layer structure thereon. Specifically, an epitaxial structure includes: a substrate 100; and a first mask layer 110 over the surface of the substrate 100, the first mask layer 110 having at least one first circular hole pattern to expose the surface of the substrate 100; the second mask layer 120 is positioned on the first mask layer 110, the thickness of the second mask layer 120 is 2 times of the radius of the first round hole pattern, the second mask layer 120 is provided with a second round hole pattern which is positioned on the first round hole pattern and is not overlapped with the center position of the first round hole pattern, and the radius of the second round hole pattern is 2 times of the radius of the first round hole pattern; the third mask layer 130 is positioned on the second mask layer 120, the third mask layer 130 is provided with a third round hole pattern which is positioned on the second round hole pattern and is not overlapped with the center position of the first round hole pattern, the transverse distance between the third round hole pattern and the first round hole pattern is 2 times of the radius of the first round hole pattern, and the radius of the third round hole pattern is equal to the radius of the first round hole pattern; and an epitaxial layer 140 including an epitaxial layer portion in the first, second, and third circular hole patterns and an epitaxial layer portion on the third mask layer 130. The epitaxial layer 130 is a planar epitaxial layer and is used for fabricating planar devices, such as high electron mobility transistors or photovoltaic devices. The first mask layer 110 is a titanium oxide film, the second mask layer 120 is a silicon dioxide film, and the third mask layer 130 is a silicon nitride film. As shown in fig. 11.
the preparation steps are as follows:
Step S11, providing a substrate 100;
Step S12, forming a first mask layer 110 having a first circular hole pattern on the substrate 100;
step S13, depositing a second mask layer 120, wherein the thickness of the second mask layer 120 is 2 times of the radius of the first circular hole pattern;
step S14, forming a third mask layer having a third circular hole pattern on the second mask layer 120, where the third circular hole pattern does not overlap with the center position of the first circular hole pattern, and a lateral distance between the third circular hole pattern and the center position of the first circular hole pattern is 2 times a radius of the first circular hole pattern;
Step S15, etching is carried out until the substrate 100 at the first circular hole pattern is completely exposed;
Step S16, growing a buffer layer 1401 with a certain thickness at a high speed, as shown in fig. 11;
In step S17, epitaxial growth is performed.
For example, the substrate 100 is a silicon substrate, the first mask layer 110 may be a titanium oxide film deposited by a PVD method, the second mask layer 120 may be a silicon dioxide film deposited by a CVD method, and the third mask layer 130 may be a silicon nitride film deposited by a PECVD method. The epitaxial layer 140 is a gallium nitride layer, a gallium arsenide layer, an aluminum gallium arsenic layer, a gallium phosphide layer, an aluminum gallium indium phosphorus layer and the like epitaxially grown by a metal organic chemical vapor deposition method MOCVD or a molecular beam epitaxy method MBE, and is used for manufacturing photoelectric devices.
in addition, depending on the application scenario, the substrate 100 may also be: a sapphire substrate/silicon carbide substrate for manufacturing a blue Light Emitting Diode (LED), a silicon germanium substrate for manufacturing a high-speed device, a gallium arsenide substrate for manufacturing a red/yellow LED, and the like; the epitaxial layer part on the third mask layer 130 can form a flat surface through a Chemical Mechanical Planarization (CMP) process and the like; of course, the flat surface of the epitaxial layer 140 can also be achieved by epitaxially growing a thicker epitaxial layer. For example, a pseudo substrate with a large thickness is generally required for performing photoelectric integration, and when the thickness of an epitaxial layer is large, the surface generally becomes flat, for example, a thick gallium nitride layer grows on a sapphire pattern substrate, and the surface of the gallium nitride layer is relatively flat; the substrate can then be used to fabricate a blue LED.
The first opening 1101, the second opening 1201, and the third opening 1301 may be in a rectangular shape, a diamond shape, a triangular shape, an irregular shape, or the like, and are not limited herein.
In this embodiment, first, a buffer layer is grown in the first opening, where the buffer layer may include a seed layer and/or an initial buffer layer, so that when the buffer layer grows upward, the effect of filtering epitaxial dislocation by using the high aspect ratio characteristic of the first opening is utilized to improve the crystal quality; the growth speed of the epitaxial layer in the vertical direction is controlled in the later growth stage of the second opening, so that the epitaxial layer grows transversely as much as possible, and the upward extension of dislocation of the epitaxial layer is favorably inhibited; and the dislocation filtering effect can be furthest utilized by utilizing the high aspect ratio characteristic of the third opening in the process of growing the epitaxial layer in the third opening. Thereby obtaining higher quality epitaxial material on a large mismatched substrate.
EXAMPLE III
an epitaxial structure, as described in the second embodiment, except that the first opening 1101 is not the same as the second opening 1201 and the third opening 1301; the substrate is a patterned substrate 1001. Specifically, an epitaxial structure includes: a pattern substrate 1001; and a first mask layer 110 over the surface of the patterned substrate 1001, the first mask layer 110 having at least one square pattern to expose the surface of the patterned substrate 1001; the second mask layer 120 is located on the first mask layer 110, the thickness of the second mask layer 120 is 2 times of the side length of the square figure, the second mask layer 120 is provided with a second round hole figure which is located on the square figure and does not overlap with the center position of the square figure, and the diameter of the second round hole figure is 2 times of the side length of the square figure; the third mask layer 130 is positioned on the second mask layer 120, the third mask layer 130 is provided with a third round hole pattern which is positioned on the second round hole pattern and is not overlapped with the center position of the square pattern, the transverse distance between the third round hole pattern and the square pattern is 2 times of the side length of the square pattern, and the diameter of the third round hole pattern is equal to the side length of the square pattern; and an epitaxial layer 140 including an epitaxial layer portion in the square pattern, the second circular hole pattern, and the third circular hole pattern and an epitaxial layer portion on the third mask layer 130. The epitaxial layer 130 may be used to fabricate microelectronic or optoelectronic devices. The first mask layer 110 is a silicon dioxide film, the second mask layer 120 is a silicon nitride film, and the third mask layer 130 is a silicon dioxide film. As shown in fig. 13.
A flow chart of an epitaxy method of the epitaxial structure is shown in fig. 14, and the epitaxy method includes:
Step S21, providing a substrate;
Step S22, forming a first mask layer 110 having a square pattern on the substrate;
step S23, depositing a second mask layer 120, wherein the thickness of the second mask layer 120 is 2 times of the radius of the square pattern;
step S24, forming a third mask layer 130 having a third circular hole pattern on the second mask layer 120, where the third circular hole pattern does not overlap with the center of the square pattern, and a lateral distance between the third circular hole pattern and the center of the square pattern is 2 times a radius of the square pattern;
step S25, etching until the substrate of the square pattern is completely exposed;
Step S26, etching the substrate by a method capable of etching the substrate without damaging the mask to form a patterned substrate 1001, as shown in fig. 12;
in step S27, epitaxial growth is performed.
For example, the substrate may be a sapphire substrate, the first mask layer 110 may be a silicon dioxide film deposited by a PECVD method, the second mask layer 120 may be a silicon nitride film deposited by a CVD method, and the third mask layer 130 may be a silicon dioxide film deposited by a PECVD method. The epitaxial layer 140 is a germanium, tin or germanium-tin alloy layer.
the sapphire substrate is etched by using a mixed solution of sulfuric acid and phosphoric acid in a volume ratio of 10:1 to form a patterned substrate 1001. The pattern of the patterned substrate 1001 is determined according to the first opening pattern, and the cross section of the pattern may be V-shaped, trapezoidal, semicircular, etc., without limitation.
Of course, the step S01 may directly use the existing patterned substrate 1001, for example, a prepared patterned substrate, and accordingly, the position, shape, width, etc. of the first opening 1101 may be adjusted according to the pattern of the provided patterned substrate, where the specific adjustment may be determined according to experimental results or simulation results, and then proceed to steps S22 to S25 and step S27 to form the epitaxial structure, which will not be described in detail herein.
referring to fig. 15, an X-ray double-crystal diffraction curve of an epitaxial structure sample according to an embodiment of the present invention and an X-ray double-crystal diffraction curve of an epitaxial structure sample in the prior art are described, in which an abscissa represents a scanning angle in an ω direction, a unit is arc seconds, and an ordinate represents relative intensity, and the same substrate and an epitaxial process are used in a process of preparing an epitaxial structure. As can be seen from fig. 15, the FWHM of the X-ray two-crystal diffraction curve of the sample of the epitaxial structure provided in the first embodiment of the present invention is less than 300 arcsec, while the FWHM of the X-ray two-crystal diffraction curve of the epitaxial structure in the prior art exceeds 400 arcsec, which indicates that the crystal quality of the epitaxial layer provided in the first embodiment of the present invention is significantly better than that of the sample of the epitaxial structure in the prior art, and thus the device efficiency and the lifetime can be improved.
in the epitaxial structure provided by the embodiment of the invention, the epitaxial layer part with higher lattice quality is formed in the second opening through the LEO technical principle, the third mask layer can inhibit dislocation from extending upwards, and then the epitaxial layer part with higher lattice quality is formed on the third mask layer through the LEO technical principle, so that the problem that the high-quality epitaxial layer cannot be prepared on the large-mismatch substrate in the prior art is solved, and the corresponding simple and feasible epitaxial method is provided.
although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims (10)

1. An epitaxial structure, comprising:
A substrate;
A first mask layer over a surface of the substrate, the first mask layer having at least one first opening to expose the surface of the substrate;
the second mask layer is positioned on the first mask layer, the thickness of the first opening is less than or equal to 3 times of that of the first opening, the second mask layer is provided with a second opening which is positioned on the first opening and does not overlap with the center of the first opening, and the width of the second opening is greater than that of the first opening;
The third mask layer is positioned on the second mask layer and provided with a third opening which is positioned on the second opening and does not overlap with the center of the first opening, the transverse distance between the third opening and the first opening is less than or equal to 2 times the width of the first opening or 2 times the width of the third opening, and the width of the third opening is less than the width of the second opening; and the aspect ratio of the first opening and/or the third opening is larger than 1;
an epitaxial layer including epitaxial layer portions in the first opening, the second opening, and the third opening and epitaxial layer portions over the third mask layer.
2. the epitaxial structure of claim 1, wherein the ratio of the first opening width to the third opening width ranges from 50% to 150%.
3. the epitaxial structure of claim 1 wherein the portion of the epitaxial layer above the third mask layer is a raised epitaxial layer above the third opening for making a FINFET MOS device.
4. the epitaxial structure of claim 1, wherein the portion of the epitaxial layer above the third mask layer is a planar epitaxial layer above the third mask layer for fabricating a planar device.
5. The epitaxial structure of claim 1, wherein the first and third openings have an aspect ratio of: the depth-to-width ratio is more than or equal to 8 and more than or equal to 1.
6. An epitaxy method, comprising:
providing a substrate;
Forming a first mask layer with a first opening on the substrate;
depositing a second mask layer, wherein the thickness of the first opening is less than or equal to 3 times of the thickness of the second mask layer;
Forming a third mask layer with a third opening on the second mask layer, wherein the third opening is not overlapped with the center position of the first opening, and the transverse distance between the third opening and the center position of the first opening is less than or equal to 2 times of the width of the first opening or 2 times of the width of the third opening; and the aspect ratio of the first opening and/or the third opening is larger than 1;
Etching until the substrate at the first opening is completely exposed;
And carrying out epitaxial growth.
7. The epitaxy method of claim 6, wherein the selective etching ratio of the second mask layer to the first mask layer and the third mask layer is not less than 20, and the etching rate of the second mask layer is the maximum.
8. The method of claim 6, wherein the performing epitaxial growth further comprises:
And growing a buffer layer with a certain thickness at a high speed before carrying out epitaxial growth.
9. the method of claim 6, wherein etching until the substrate at the first opening is completely exposed further comprises:
And etching the substrate to form a pattern substrate.
10. The epitaxy method of claim 6, wherein the degree of lattice mismatch between the epitaxially grown epitaxial layer and the substrate is greater than or equal to 4% and less than or equal to 25%.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273929A (en) * 1990-08-24 1993-12-28 Thomson-Csf Method of manufacture transistor having gradient doping during lateral epitaxy
CN1205556A (en) * 1997-03-25 1999-01-20 三菱电线工业株式会社 Gan group crystal base member having low dislocation density, use thereof and manufacturing methods thereof
CN1292149A (en) * 1998-02-27 2001-04-18 北卡罗莱纳州立大学 Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth through masks, and gallium nitride semiconductor structures fabricated thereby
EP1244139A2 (en) * 2001-03-23 2002-09-25 Matsushita Electric Industrial Co., Ltd. Manufacturing method of semiconductor film
CN101853808A (en) * 2008-08-11 2010-10-06 台湾积体电路制造股份有限公司 Method of forming a circuit structure
CN101924021A (en) * 2010-07-02 2010-12-22 北京北方微电子基地设备工艺研究中心有限责任公司 Semiconductor device, as well as manufacture method and luminescent device thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1027936A (en) * 1996-07-10 1998-01-27 Oki Electric Ind Co Ltd Method of forming laser with modulator
US6500257B1 (en) * 1998-04-17 2002-12-31 Agilent Technologies, Inc. Epitaxial material grown laterally within a trench and method for producing same
JP2002280314A (en) * 2001-03-22 2002-09-27 Toyoda Gosei Co Ltd Manufacturing method of iii nitride compound semiconductor group, and the iii nitride compound semiconductor element based thereon
JP2006005044A (en) * 2004-06-16 2006-01-05 Rohm Co Ltd Nitride system semiconductor light emitting device and its manufacturing method
JP2009182010A (en) * 2008-01-29 2009-08-13 Kyocera Corp Manufacturing method of group iii nitride compound semiconductor, light emitting element, lighting device, and substrate for group iii nitride compound semiconductor growth
JP5678641B2 (en) * 2010-12-20 2015-03-04 富士通株式会社 Compound semiconductor device and manufacturing method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273929A (en) * 1990-08-24 1993-12-28 Thomson-Csf Method of manufacture transistor having gradient doping during lateral epitaxy
CN1205556A (en) * 1997-03-25 1999-01-20 三菱电线工业株式会社 Gan group crystal base member having low dislocation density, use thereof and manufacturing methods thereof
CN1292149A (en) * 1998-02-27 2001-04-18 北卡罗莱纳州立大学 Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth through masks, and gallium nitride semiconductor structures fabricated thereby
EP1244139A2 (en) * 2001-03-23 2002-09-25 Matsushita Electric Industrial Co., Ltd. Manufacturing method of semiconductor film
CN101853808A (en) * 2008-08-11 2010-10-06 台湾积体电路制造股份有限公司 Method of forming a circuit structure
CN101924021A (en) * 2010-07-02 2010-12-22 北京北方微电子基地设备工艺研究中心有限责任公司 Semiconductor device, as well as manufacture method and luminescent device thereof

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