CN106449764B - Flexible thin film bottom gate double-channel transistor - Google Patents

Flexible thin film bottom gate double-channel transistor Download PDF

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Publication number
CN106449764B
CN106449764B CN201611059419.XA CN201611059419A CN106449764B CN 106449764 B CN106449764 B CN 106449764B CN 201611059419 A CN201611059419 A CN 201611059419A CN 106449764 B CN106449764 B CN 106449764B
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thin film
single crystal
crystal silicon
silicon thin
substrate
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CN106449764A (en
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秦国轩
黄治塬
靳萌萌
刘昊
王亚楠
党孟娇
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Tianjin University
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Tianjin University
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

A flexible thin film bottom gate double channel transistor comprises a substrate, wherein the substrate is a flexible substrate, and an ITO conductive layer and an S are sequentially arranged on the substrate i O oxide layer, S i The O oxide layer is provided with a monocrystalline silicon film, a first source electrode, a second source electrode, a drain electrode and a grid electrode, wherein the monocrystalline silicon film is respectively connected with the first source electrode, the second source electrode and the drain electrode through metal interconnection wires, the grid electrode is connected with one end of a conductive column through the metal interconnection wires, and the other end of the conductive column is sequentially inserted into the S i The O oxide layer and the ITO conductive layer are connected to the substrate, so that the grid electrode is connected with the ITO conductive layer through a metal interconnection wire and a conductive column. The invention can be applied to the flexible radio frequency field, namely, the fields of active antennas, remote radio frequency identification, biomedical remote sensing, foldable phased array antennas and the like, and the manufacturing process is completely compatible with flexible capacitors, inductors, PIN diodes and the like. A high-performance thin film transistor can be realized by using a single crystal silicon thin film transfer process in combination.

Description

Flexible thin film bottom gate double-channel transistor
Technical Field
The present invention relates to a thin film transistor. And more particularly to a flexible thin film bottom gate double channel transistor.
Background
In the last decade, flexible electronics have evolved rapidly and many researchers have been devoted to their research. A wide variety of electronic products have been developed, including flexible displays, electronic tags, and some low cost integrated circuits. In addition to these, some electronic products need to operate properly at microwave radio frequencies, such as portable wireless devices, communication antennas, space remote sensing, and military applications. Flexible electronics are lighter and more impact resistant than hard-based circuits. That is, the conventional thin film transistor using hard silicon as a substrate is not flexible and is not compatible with a flexible system. By now, the demand for high-speed high-performance flexible thin film transistors is becoming more intense because the wireless application range is greatly widened when the frequency range reaches or exceeds gigahertz.
Disclosure of Invention
The invention aims to solve the technical problem of providing a flexible thin film bottom gate double-channel transistor applicable to the flexible radio frequency field.
The technical scheme adopted by the invention is as follows: a flexible thin film bottom gate double channel transistor comprises a substrate, wherein the substrate is a flexible substrate, and an ITO conductive layer and an S are sequentially arranged on the substrate i O oxide layer, S i The O oxide layer is provided with a monocrystalline silicon film, a first source electrode, a second source electrode, a drain electrode and a grid electrode, wherein the monocrystalline silicon film is respectively connected with the first source electrode, the second source electrode and the drain electrode through metal interconnection wires, the grid electrode is connected with one end of a conductive column through the metal interconnection wires, and the other end of the conductive column is sequentially inserted into the S i The O oxide layer and the ITO conductive layer are connected to the substrate, so that the grid electrode is connected with the ITO conductive layer through a metal interconnection wire and a conductive column.
The single crystal silicon thin film comprises a first single crystal silicon thin film, a second single crystal silicon thin film, a third single crystal silicon thin film, a fourth single crystal silicon thin film and a fifth single crystal silicon thin film which are sequentially connected side by side, wherein the first single crystal silicon thin film, the third single crystal silicon thin film and the fifth single crystal silicon thin film are N-type doped regions, the second single crystal silicon thin film and the fourth single crystal silicon thin film are undoped regions, one end of the first single crystal silicon thin film, which is far away from the second single crystal silicon thin film, is connected with the first source electrode through a metal interconnection line, one end of the fifth single crystal silicon thin film, which is far away from the fourth single crystal silicon thin film, is connected with the second source electrode through the metal interconnection line, and the third single crystal silicon thin film is connected with the drain electrode through the metal interconnection line.
The substrate is PET plastic or PEN plastic or PI plastic.
The metal interconnection line is formed by stacking titanium metal and gold metal.
The flexible thin film bottom gate double-channel transistor can be applied to the flexible radio frequency field, namely the fields of active antennas, remote radio frequency identification, biomedical remote sensing, foldable phased array antennas and the like, and the manufacturing process is completely compatible with flexible capacitors, inductors, PIN diodes and the like. A high-performance thin film transistor can be realized by using a single crystal silicon thin film transfer process in combination.
Drawings
FIG. 1 is a side view of a flexible thin film bottom gate double channel transistor of the present invention;
fig. 2 is a top view of a flexible thin film bottom gate double channel transistor of the present invention.
In the figure
1: substrate 2: ITO conductive layer
3:S i O oxide layer 4: first monocrystalline silicon thin film
5: second monocrystalline silicon thin film 6: third monocrystalline silicon thin film
7: fourth monocrystalline silicon thin film 8: fifth monocrystalline silicon thin film
9: conductive post 10: first source electrode
11: second source 12: drain electrode
13: gate 14: metal interconnection line
Detailed Description
A flexible thin film bottom gate double channel transistor according to the present invention will be described in detail with reference to the examples and drawings.
The invention discloses a flexible film bottom gate double-channel transistor, which aims to overcome the defect that a traditional film transistor taking hard silicon as a substrate is not easy to bend and is incompatible with a flexible system, and develops a double-channel film transistor with a bottom gate structure applicable to the flexible radio frequency field by combining a film transfer process.
As shown in fig. 1 and 2, the flexible thin film bottom gate double-channel transistor of the present invention comprises a substrate 1, wherein the substrate 1 is a flexible substrateThe bottom can be PET plastic, PEN plastic or PI plastic. The substrate 1 is sequentially provided with an ITO conductive layer 2 and an S i The O oxide layer 3, the substrate 1 and the ITO conductive layer 2 are used for supporting the main body part of the flexible thin film transistor. The S is i The O oxide layer 3 is provided with a monocrystalline silicon film, a first source electrode 10, a second source electrode 11, a drain electrode 12 and a grid electrode 13, wherein the monocrystalline silicon film is respectively connected with the first source electrode 10, the second source electrode 11 and the drain electrode 12 through metal interconnection wires 14, the grid electrode 13 is connected with one end of a conductive column 9 through the metal interconnection wires 14, and the other end of the conductive column 9 is sequentially inserted into the S i The O oxide layer 3 and the ITO conductive layer 2 are arranged on the substrate 1, so that the grid electrode 13 is connected with the ITO conductive layer 2 through the metal interconnection line 14 and the conductive column 9, and a bottom grid structure of the thin film transistor is realized.
For a multi-channel transistor, the body portion of the flexible thin film transistor is a partially doped and undoped single crystal silicon thin film region, and therefore, the single crystal silicon thin film comprises: the first monocrystalline silicon thin film 4, the second monocrystalline silicon thin film 5, the third monocrystalline silicon thin film 6, the fourth monocrystalline silicon thin film 7 and the fifth monocrystalline silicon thin film 8 are sequentially connected side by side, wherein the first monocrystalline silicon thin film 4, the third monocrystalline silicon thin film 6 and the fifth monocrystalline silicon thin film 8 are N-type doped regions, and the second monocrystalline silicon thin film 5 and the fourth monocrystalline silicon thin film 7 are undoped regions, namely channel regions. One end of the first monocrystalline silicon film 4 far away from the second monocrystalline silicon film 5 is connected with the first source electrode 10 through a metal interconnection line 14, one end of the fifth monocrystalline silicon film 8 far away from the fourth monocrystalline silicon film 7 is connected with the second source electrode 11 through a metal interconnection line 14, and the third monocrystalline silicon film 6 is connected with the drain electrode 12 through a metal interconnection line 14. The metal interconnection line 14 is formed by stacking titanium metal and gold metal.

Claims (4)

1. The flexible thin film bottom gate double-channel transistor comprises a substrate (1), and is characterized in that the substrate (1) is a flexible substrate, and an ITO conductive layer (2) and an S are sequentially arranged on the substrate (1) i An O oxide layer (3), said S i The O oxide layer (3) is provided with a monocrystalline silicon film, a first source electrode (10), a second source electrode (11) and a drain electrode (1)2) And a grid electrode (13), wherein the monocrystalline silicon film is respectively connected with the first source electrode (10), the second source electrode (11) and the drain electrode (12) through metal interconnection wires (14), the grid electrode (13) is connected with one end of a conductive column (9) through the metal interconnection wires (14), and the other end of the conductive column (9) is sequentially inserted into the S i The O oxide layer (3) and the ITO conductive layer (2) are arranged on the substrate (1), so that the grid electrode (13) is connected with the ITO conductive layer (2) through the metal interconnection line (14) and the conductive column (9).
2. The flexible thin film bottom gate double channel transistor according to claim 1, wherein the single crystal silicon thin film comprises a first single crystal silicon thin film (4), a second single crystal silicon thin film (5), a third single crystal silicon thin film (6), a fourth single crystal silicon thin film (7) and a fifth single crystal silicon thin film (8) which are sequentially connected side by side, wherein the first single crystal silicon thin film (4), the third single crystal silicon thin film (6) and the fifth single crystal silicon thin film (8) are N-type doped regions, the second single crystal silicon thin film (5) and the fourth single crystal silicon thin film (7) are undoped regions, one end of the first single crystal silicon thin film (4) far away from the second single crystal silicon thin film (5) is connected with the first source electrode (10) through a metal interconnection line (14), one end of the fifth single crystal silicon thin film (8) far away from the fourth single crystal silicon thin film (7) is connected with the second source electrode (11) through the metal interconnection line (14), and the third single crystal silicon thin film (6) is connected with the drain electrode (12) through the metal interconnection line (14).
3. A flexible thin film bottom gate double channel transistor according to claim 1, characterized in that the substrate (1) is PET plastic or PEN plastic or PI plastic.
4. A flexible thin film bottom gate double channel transistor according to claim 1, wherein said metal interconnect line (14) is formed by stacking titanium metal and gold metal.
CN201611059419.XA 2016-11-23 2016-11-23 Flexible thin film bottom gate double-channel transistor Active CN106449764B (en)

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Publication number Priority date Publication date Assignee Title
CN107658344A (en) * 2017-08-31 2018-02-02 天津大学 A kind of flexible and transparent type Double bottom gate transistor and manufacture method based on germanium nanometer film
CN107425078A (en) * 2017-08-31 2017-12-01 天津大学 A kind of flexible metal type Double bottom gate transistor and manufacture method based on silicon nanometer film
CN107611171A (en) * 2017-09-16 2018-01-19 天津大学 A kind of more channel transistors of flexible bottom gate based on silicon nanometer film and preparation method thereof
CN107611172A (en) * 2017-09-16 2018-01-19 天津大学 A kind of heterogeneous dielectric layer flexibility bottom-gate transistor and preparation method

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CN101562196A (en) * 2009-05-26 2009-10-21 上海大学 Multi-source common-drain thin-film transistor and preparation method thereof
CN203811124U (en) * 2014-03-12 2014-09-03 徐州集光电子科技有限公司 Flexible radio frequency monocrystalline silicon thin film bidirectional dynamic strain sensor
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CN105047567A (en) * 2015-08-19 2015-11-11 武汉华星光电技术有限公司 Film transistor and manufacturing method therefor
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CN203811124U (en) * 2014-03-12 2014-09-03 徐州集光电子科技有限公司 Flexible radio frequency monocrystalline silicon thin film bidirectional dynamic strain sensor
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