CN106449613B - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

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Publication number
CN106449613B
CN106449613B CN201610505374.8A CN201610505374A CN106449613B CN 106449613 B CN106449613 B CN 106449613B CN 201610505374 A CN201610505374 A CN 201610505374A CN 106449613 B CN106449613 B CN 106449613B
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terminal
surface portion
plate member
circuit board
semiconductor device
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CN201610505374.8A
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CN106449613A (en
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征矢野伸
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor device is provided, which can suppress the malfunction of the semiconductor device and can improve the reliability of the semiconductor device. In a semiconductor device (100), circuit boards (142a, 142b) are provided on an insulating substrate (141) of a laminated substrate (140), a semiconductor chip is provided on the circuit board (142a), and a semiconductor chip is provided on the circuit board (142 b). In addition, in the semiconductor device (100), a jumper terminal having a terminal portion connected to a semiconductor chip on a circuit board (142a) and a flat plate portion orthogonal to the terminal portion, and a jumper terminal having a terminal portion connected to a semiconductor chip on a circuit board (142b) and a flat plate portion orthogonal to the terminal portion are arranged on a laminated substrate (140) in a state where a plate portion of a resin plate having a positioning portion that defines a position of each semiconductor chip is sandwiched.

Description

Semiconductor device with a plurality of semiconductor chips
Technical Field
The present invention relates to a semiconductor device.
Background
Power Semiconductor modules (Semiconductor devices) include Semiconductor chips such as IGBTs (Insulated Gate Bipolar transistors), MOSFETs (Metal Oxide Semiconductor Field Effect transistors), and FWDs (Free Wheeling diodes), and are widely used as power conversion devices.
In such a semiconductor device, in a laminated substrate having an insulating substrate and a circuit pattern formed of a copper foil formed on the insulating substrate, the semiconductor chip is disposed on the copper foil, and the laminated substrate is housed in a case. Wiring is performed on the laminated substrate and the semiconductor chip in the case, and the electrodes of the semiconductor chip and the external electrode terminals are electrically connected by wires, respectively, and the structure in the case is sealed with a resin (see, for example, patent document 1).
Documents of the prior art
Patent document
Patent document 1: japanese patent application laid-open No. 2000-323646
However, in the semiconductor device, depending on the wiring electrically connected to the semiconductor chip, a magnetic field or the like generated by conduction through the wiring may affect the product characteristics, and may cause malfunction. Thus, the reliability of the semiconductor device may be reduced.
Disclosure of Invention
According to an aspect of the present invention, there is provided a semiconductor device including: a laminated substrate having an insulating substrate, a first circuit board and a second circuit board, wherein the first circuit board is disposed on a front surface of the insulating substrate, and the second circuit board and the first circuit board are disposed side by side on the front surface; a first semiconductor chip disposed on a first circuit board; the second semiconductor chip is configured on the second circuit board; a first crossover terminal having a first terminal portion electrically connected to a main electrode of a first semiconductor chip and a first plate member; a second jumper terminal having a second terminal portion electrically connected to a main electrode of a second semiconductor chip and a second plate member; and a resin plate having a first positioning portion that is placed on the front surface of the first circuit board and that defines a position of the first semiconductor chip on the first circuit board, a second positioning portion that is placed on the front surface of the second circuit board and that defines a position of the second semiconductor chip on the second circuit board, and a plate portion that is sandwiched between the first circuit board and the second circuit board by the first plate member and the second plate member.
According to the disclosed technology, malfunction of the semiconductor device can be suppressed, and reliability of the semiconductor device can be improved.
Drawings
Fig. 1 is a perspective view of a semiconductor device according to an embodiment.
Fig. 2 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment.
Fig. 3 is a perspective view of the semiconductor device according to the embodiment with components mounted on an insulating substrate.
Fig. 4 is a perspective view of a jumper terminal of the semiconductor device according to the embodiment.
Fig. 5 is a plan view of a laminated substrate on which a resin plate is mounted in the semiconductor device according to the embodiment.
Fig. 6 is a diagram showing a resin plate of a semiconductor device according to an embodiment.
Fig. 7 is a diagram (one of) showing an assembly process of a laminated substrate on which a resin plate is mounted in a semiconductor device according to an embodiment.
Fig. 8 is a diagram (two) showing an assembly process of the laminated substrate with the resin plate mounted thereon in the semiconductor device according to the embodiment.
Fig. 9 is a diagram (iii) showing an assembly process of a laminated substrate with a resin plate mounted thereon in the semiconductor device according to the embodiment.
Fig. 10 is a perspective view of a terminal block of the semiconductor device of the embodiment.
Fig. 11 is a perspective view (one of) the printed circuit board and the terminal block of the semiconductor device according to the embodiment.
Fig. 12 is a perspective view (two) of the printed circuit board and the terminal block of the semiconductor device according to the embodiment.
Fig. 13 is a plan view of a case of the semiconductor device of the embodiment.
Fig. 14 is a rear view of the housing of the semiconductor device of the embodiment.
Fig. 15 is a perspective view of a wiring terminal of the semiconductor device of the embodiment.
Fig. 16 is a sectional view of a wiring terminal and a laminated substrate of the semiconductor device according to the embodiment.
Fig. 17 is an enlarged view of a main portion of the semiconductor device of the embodiment.
Fig. 18 is a perspective view of a resin block of the semiconductor device of the embodiment.
Fig. 19 is a circuit diagram showing a circuit configuration formed in the semiconductor device of the embodiment.
(symbol description)
100 semiconductor device
110 casing
112a, 112b, 112c receiving parts
113a, 113b, 113c P terminal
114a, 114b, 114c N terminal
115a U terminal
115b V terminal
115c W terminal
116. 117, 118 wiring terminal
116a, 117a, 118a bottom surface portion
116b, 116c, 117b, 117c, 118b side face parts
119a, 119b printed circuit board
120. 130 terminal block
121. 131 control terminal
140 laminated substrate
141 insulating substrate
142a, 142b circuit board
143a, 143b conductive terminal
144a, 144b, 144c, 146a, 146b, 146c semiconductor chips (semiconductor elements)
145a, 145b cross-over terminal
145aa, 145ba flat plate portions
145ab, 145bb terminal portion
145ac, 145bc step
150 resin block
200. 210 clamp
201. 202, 203, 204, 205, 206 semiconductor chip housing parts
207. 208 conductive terminal receiving portion
210a terminal portion receiving portion
Detailed Description
Hereinafter, embodiments will be described with reference to the drawings.
[ embodiment ]
First, a semiconductor device according to an embodiment will be described with reference to fig. 1.
Fig. 1 is a perspective view of a semiconductor device according to an embodiment.
The semiconductor device 100 includes a case 110 and a laminated substrate 140, and the laminated substrate 140 is housed in housing portions 112a, 112b, and 112c of the case 110, respectively.
The semiconductor device 100 has positive electrodes connected to P terminals (second external terminals) 113a, 113b, and 113c, negative electrodes connected to N terminals (first external terminals) 114a, 114b, and 114c, and control signals are applied to the control terminals 121 and 131 to obtain outputs corresponding to the control signals from a U terminal (third external terminal) 115a, a V terminal (third external terminal) 115b, and a W terminal 115c (third external terminal).
In addition, details of the case 110 and the laminated substrate 140 housed in the case 110 constituting such a semiconductor device 100 will be described later.
Here, a method for manufacturing the semiconductor device 100 will be described with reference to fig. 2.
Fig. 2 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment.
Step S11 prepares the printed boards 119a and 119b and the terminal blocks 120 and 130 (step S11 a). Further, the laminated substrate 140 is prepared (step S11 b). In step S11a, the control terminals 121 and 131 of the terminal blocks 120 and 130 are press-fitted into the printed boards 119a and 119b, respectively, and the printed boards 119a and 119b are held on the lower surfaces of the terminal blocks 120 and 130.
Here, the laminated substrate 140 will be described with reference to fig. 3.
Fig. 3 is a perspective view of the semiconductor device according to the embodiment with components mounted on an insulating substrate.
The laminated substrate 140 has a heat sink (not shown) made of copper or the like disposed on the lower surface of the insulating substrate 141, and circuit boards 142a and 142b made of copper foil or the like disposed on the upper surface of the insulating substrate 141.
On the circuit board (first circuit board) 142a, conductive terminals 143a made of, for example, copper are arranged on the lower side in the drawing, and semiconductor chips (first semiconductor chips) 144a, 144b, and 144c (on the collector electrode side) are arranged in a row by soldering. Further, a jumper terminal (first jumper terminal) 145a is disposed by soldering on the emitter electrodes of the semiconductor chips 144a, 144b, and 144c arranged in a row so that the emitter electrodes of the semiconductor chips 144a, 144b, and 144c are electrically connected.
On the circuit board (second circuit board) 142b, conductive terminals 143b made of, for example, copper are arranged on the upper side in the drawing, that is, on the side opposite to the conductive terminals 143a, and semiconductor chips (second semiconductor chips) 146a, 146b, and 146c (on the collector electrode side) are arranged in a row by soldering. Further, a jumper terminal (second jumper terminal) 145b is disposed by soldering on the emitter electrodes of the semiconductor chips 146a, 146b, 146c arranged in a row so that the emitter electrodes of the semiconductor chips 146a, 146b, 146c are electrically connected.
In the illustrated example, the semiconductor chips 144a, 144b, and 144c are electrically connected in parallel, and the semiconductor chips 146a, 146b, and 146c are electrically connected in parallel. The number of semiconductor chips can be reduced according to the increase in the capacity of the semiconductor device.
Here, the jumper terminals 145a and 145b will be described with reference to fig. 3 and 4. Fig. 4 is a perspective view of a jumper terminal of the semiconductor device according to the embodiment.
The jumper terminal 145a (145b) has a terminal portion 145ab (145bb), a flat plate portion (plate member) 145aa (145ba), and a stepped portion 145ac (145bc) connecting the flat plate portion 145aa (145ba) and the terminal portion 145ab (145 bb).
The terminal portions 145ab (145bb) are prepared in accordance with the number of semiconductor chips to be connected, and are joined to the respective semiconductor chips by bonding material such as soldering, and are electrically and mechanically connected to the respective semiconductor chips. Terminal portion 145ab (145bb) has through hole 145ad (145bd) penetrating from the upper surface to the lower surface side (connection surface) in the drawing. In the semiconductor device 100, the through-hole 145ad (145bd) is provided in the terminal portion 145ab (145bb), so that when the semiconductor device is sealed with resin, the resin can enter the through-hole 145ad (145bd), the adhesion of the resin can be improved, and the resin is less likely to peel off.
The flat plate portion 145aa (145ba) is connected to terminal portions 145ab (145bb) electrically connected to the semiconductor chips via step portions 145ac (145 bc). The thickness of the flat plate portion 145aa (145ba) is, for example, 1mm to 1.5 mm. In the illustrated example, the front surface of the flat plate portion 145aa (145ba) and the front surface of the terminal portion 145ab (145bb) are substantially orthogonal to each other, the stepped portion 145ac (145bc) has a surface substantially parallel to the two front surfaces, and one cross section of the jumper terminal 145a (145b) has a zigzag shape.
The stepped portion 145ac (145bc) supports the wiring terminals 116(117) described later from below.
As shown in fig. 3, the flat plate portion 145aa of the jumper terminal 145a is disposed parallel to and opposite to the flat plate portion 145ba of the jumper terminal 145 b. As shown in fig. 3, jumper terminal 145a protrudes to a position higher than jumper terminal 145b in the drawing in a plan view. As shown in fig. 3, jumper terminal 145b protrudes to a position lower than jumper terminal 145a in the drawing in a plan view. The flat plate portion 145aa and the flat plate portion 145ba are arranged offset with respect to each other with the resin plate 147 interposed therebetween. One end portion of the flat plate portion 145aa is disposed in the vicinity of one end portion of the laminated substrate 140 with respect to one end portion of the flat plate portion 145ba, and the other end portion of the flat plate portion 145ba is disposed in the vicinity of the other end portion opposite to the one end portion of the laminated substrate 140 with respect to the other end portion of the flat plate portion 145 aa.
Resin sheet 147 is disposed between jumper terminal 145a and jumper terminal 145b, and jumper terminal 145a and jumper terminal 145b are supported by resin sheet 147.
Here, the resin plate 147 will be described with reference to fig. 3, 5, and 6. Fig. 5 is a plan view of the resin-plate-mounted laminated substrate of the semiconductor device according to the embodiment, which is a plan view of fig. 3 with the crossover terminals 145a and 145b removed. Fig. 6 is a diagram showing a resin plate of a semiconductor device according to an embodiment. Fig. 6(a) is a schematic cross-sectional view of the resin plate 147 and the flat plate portions 145aa and 145ba at the dashed-dotted line Y-Y in fig. 3. Fig. 6(b) is a perspective view of fig. 6(a) with the flat plate portions 145aa and 145ba removed.
The resin plate 147 has a plate portion 147a and a positioning portion 147 b. As shown in fig. 3, the plate portion 147a is disposed between the flat plate portion 145aa and the flat plate portion 145ba (between the circuit board 142b and the circuit board 142 a). As shown in fig. 3, the plate portion 147a projects upward in the drawing from the flat plate portion 145ba (for example, 1mm or more) and projects downward in the drawing from the flat plate portion 145aa (for example, 1mm or more). As shown in fig. 6(a), the plate portion 147a projects further toward the upper and lower sides in the figure than the flat plate portions 145aa and 145ba (for example, 1mm or more) in cross-sectional view. One end portions of the flat plate portion 145aa, the plate portion 147a, and the flat plate portion 145ba are arranged in order to be shifted, and two adjacent side surfaces of the one end portion of the plate portion 147a are exposed between the flat plate portions 145aa and 145 ba. The other end portions of the flat plate portion 145aa, the plate portion 147a, and the flat plate portion 145ba on the opposite side to the one end portion are similarly arranged in a staggered manner.
That is, the plate portion 147a is provided at a portion (overlapping region) where the flat plate portion 145aa and the flat plate portion 145ba face each other in parallel.
By disposing such plate portion 147a between the flat plate portion 145aa and the flat plate portion 145ba, the semiconductor device 100 can secure a creepage distance and a space distance between the jumper terminal 145a and the jumper terminal 145 b. That is, the semiconductor device 100 can ensure insulation between the jumper terminal 145a and the jumper terminal 145 b.
The positioning portions 147b are provided on the opposite surfaces of the plate portion 147a, i.e., on the circuit board 142a side and the circuit board 142b side, respectively, and are in close contact with the circuit boards 142a, 142 b. As shown in fig. 5, the positioning portion 147b has a convex shape or a T-shape (step shape) in plan view, and is located between the semiconductor chips 144a and 144b, between the semiconductor chips 144b and 144c, between the semiconductor chips 146a and 146b, and between the semiconductor chips 146b and 146 c. The positioning portion 147b is arranged such that a convex step portion is located at a portion corresponding to a corner portion of each semiconductor chip of a quadrangle, and the position of each semiconductor chip (the position of both sides) is defined (fixed) with both sides of the step portion. The positioning portions 147b are provided at positions shifted from each other on the circuit board 142a side and the circuit board 142b side, whereby the resin board 147 can be made less prone to toppling.
As shown in fig. 6a and 6b, the positioning portion 147b has a slit (insertion portion) 147c into which the jumper terminals 145a and 145b are inserted. The flat plate portion 145aa bridging the portion of the terminal 145a where the step portion 145ac is not provided is inserted into the slit 147 c. Further, the flat plate portion 145ba of the portion of the jumper terminal 145b where the step portion 145bc is not provided is inserted into the slit 147 c.
By inserting jumper terminals 145a and 145b into slit 147c in this manner, resin plate 147 can support jumper terminals 145a and 145b so that jumper terminals 145a and 145b do not fall over when assembled.
The slit 147c is sized to allow the inserted flat plate portion 145aa (145ba) to slide vertically.
As described later, the jumper terminal 145a is disposed on the laminated substrate 140 in a state where the flat plate portion 145aa is inserted into the slit 147c, but since the flat plate portion 145aa can be slid in the slit 147c, the terminal portion 145ab can be guided to an appropriate position while the insertion is maintained. Further, the jumper terminal 145b is disposed on the laminated substrate 140 in a state where the flat plate portion 145ba is inserted into the slit 147c, but since the flat plate portion 145ba can be slid in the slit 147c, the terminal portion 145bb can be guided to an appropriate position while keeping the insertion. That is, since the flat plate portion 145aa (145ba) slides within the slit 147c, the terminal portion 145ab (145bb) can be moved to an appropriate position in a state where the positioning portion 147b of the resin plate 147 is brought into close contact with the circuit boards 142a, 142 b.
Instead of the slit 147c of the positioning portion 147b, a holding mechanism for holding the jumper terminals 145a and 145b may be provided in the plate portion 147 a.
The shape of the positioning portion 147b is an example, and is not limited to a convex shape. The shape of the positioning portion 147b may be any shape that can define the position of the semiconductor chip. In addition, the resin board 147 may be formed without providing the positioning portion 147b by further increasing the thickness of the plate portion 147a shown in fig. 5 so that the plate portion 147a extends to the circuit boards 142a and 142b to be in close contact with the circuit boards 142a and 142b, and the position of each semiconductor chip (the position of one side) may be defined by the plate portion 147 a. As the material of the resin plate 147, a resin corresponding to soldering, such as Liquid Crystal Polymer (LCP) or polyphenylene sulfide (PPS), can be used.
IGBTs, MOSFETs, FWDs, or the like are used as the semiconductor chips 144a, 144b, 144c, 146a, 146b, 146 c. Fig. 3 shows an example in which an RC-IGBT (Reverse Conducting IGBT) is used as the semiconductor chip 144a and the like. Silicon carbide and gallium nitride can be used as substrates for semiconductor chips in addition to silicone. Each of the semiconductor chips 144a and the like includes a plurality of control electrodes 144ac, 144bc, 144cc, 146ac, 146bc, and 146cc connected to a gate terminal, a sense terminal, and a chip temperature measurement terminal, in addition to main electrodes (a transmitter electrode and a collector electrode).
Here, an assembly process of the laminated substrate with the resin plate mounted thereon will be described with reference to fig. 7 to 9. Fig. 7 to 9 are views showing an assembly process of the laminated substrate with the resin plate mounted thereon of the semiconductor device according to the embodiment.
First, as shown in fig. 7a, a laminated substrate 140 is prepared, in which a heat sink (not shown) made of copper or the like is disposed on the lower surface of an insulating substrate 141 of the laminated substrate 140, and circuit boards 142a and 142b made of copper foil or the like are disposed on the upper surface (front surface) of the insulating substrate 141.
Next, as shown in fig. 7(b), the jig 200 for positioning the electronic component (conductive terminal, semiconductor chip) disposed on the laminated substrate 140 is disposed on the laminated substrate 140. Semiconductor chip housing portions 201, 202, 203, 204, 205, 206 are provided at positions where the semiconductor chips are arranged in the jig 200, and the semiconductor chip housing portions 201, 202, 203, 204, 205, 206 expose the laminated substrate 140 ( circuit boards 142a, 142 b). Further, conductive terminal housing portions 207, 208 are provided at positions where the conductive terminals are arranged in the jig 200, and the conductive terminal housing portions 207, 208 expose the laminated substrate 140 ( circuit boards 142a, 142 b).
Next, as shown in fig. 8 and 9, the semiconductor chips 144a to 144c, 146a to 146c, the jumper terminals 145a, 145b, and the resin board 147 are disposed on the circuit boards 142a, 142b, the semiconductor chips 144a to 144c, 146a to 146c are positioned by the resin board 147, and the circuit boards 142a, 142b, the semiconductor chips 144a to 144c, 146a to 146c, and the jumper terminals 145a, 145b are joined by soldering.
Next, as shown in fig. 8(a), the electronic component is disposed on the laminate substrate 140 by soldering. The solder material and the semiconductor chips 144a, 144b, 144c, 146a, 146b, 146c are sequentially disposed on the circuit boards 142a, 142b in the semiconductor chip housing portions 201, 202, 203, 204, 205, 206. The solder and the conductive terminals 143a and 143b are sequentially disposed on the circuit boards 142a and 142b in the conductive terminal housing portions 207 and 208.
Next, as shown in fig. 8(b), the jig 210 for positioning the terminal portions 145ab and 145bb is disposed above the semiconductor chips already disposed in the semiconductor chip accommodation portions 201, 202, 203, 204, 205, and 206. Terminal receiving portions 210a are provided at positions where the terminal portions 145ab and 145bb of the jig 210 are arranged, and the terminal receiving portions 210a expose main electrodes (emitter electrodes) of the respective semiconductor chips.
Next, as shown in fig. 9, resin plate 147 into which flat plate portions 145aa and 145ba of jumper terminals 145a and 145b are inserted into slit 147c is disposed on laminated substrate 140. The solder material is disposed between the terminal portions 145ab and 145bb and the main electrodes of the semiconductor chips.
The thus assembled parts and jig are put into a furnace, and the soldering material is heated, melted, and cooled to solder and connect the members. Thus, the back surfaces (collector electrodes) of the semiconductor chips 144a, 144b, 144c, 146a, 146b, 146c are joined to the circuit boards 142a, 142b by soldering, the back surfaces of the conductive terminals 143a, 143b are joined to the circuit boards 142a, 142b by soldering, and the terminal portions 145ab, 145bb are joined to the front surfaces (emitter electrodes) of the semiconductor chips by soldering, and the soldering material is a board solder or a paste solder not containing lead.
In the above example, the components are collectively soldered in the assembled state before the state of fig. 9, but the soldering may be performed a plurality of times. For example, as shown in fig. 8(a), at the stage after the electronic component is disposed on the laminate substrate 140, the rear surfaces of the semiconductor chips 144a to 144c and 146a to 146c and the rear surfaces of the conductive terminals 143a and 143b may be joined to the circuit boards 142a and 142b by soldering, and then, as shown in fig. 9, at the stage when the resin plate 147 is disposed on the laminate substrate 140, the front surfaces of the semiconductor chips 144a to 144c and 146a to 146c may be joined to the terminal portions 145ab and 145bb by soldering.
The resin plate 147 is disposed on the laminate substrate 140 so that the positioning portions 147b are in close contact with the circuit boards 142a and 142b and the positions of the semiconductor chips 144a, 144b, 144c, 146a, 146b, and 146c are limited from the inner side (central side).
That is, in a state where the resin plate 147 is disposed on the laminate substrate 140, the positions of the semiconductor chips 144a, 144b, 144c, 146a, 146b, and 146c are defined from the outside by the jig 200, and the positioned portion 147b is defined from the inside.
In this state, the flat plate portions 145aa and 145ba inserted into the slit 147c are slid in the slit 147c, and the terminal portions 145ab and 145bb are moved to appropriate positions of the terminal portion receiving portion 210a of the jig 210. Next, the back surfaces of terminal portions 145ab and 145bb are soldered to the semiconductor chips, and terminal portions 145ab and 145bb are bonded to the semiconductor chips. The clamps 200, 210 are then removed. Thereby, the structure of the laminated substrate 140 as shown in fig. 3 can be obtained.
In this way, since terminal portions 145ab and 145bb are bonded in a state where the position of each semiconductor chip is defined from the outside by jig 200 and from the inside by positioning portion 147b, it is possible to suppress each semiconductor chip from moving away from an appropriate position due to heat or the like at the time of bonding.
Further, by positioning only the outer side of the semiconductor chip using the jig 200 and positioning the inner side using the resin plate 147 used for securing the insulation of the jumper terminals 145a and 145b, the jig 200 can be easily removed from the laminated substrate 140 after assembly.
Next, terminal blocks 120 and 130 will be described with reference to fig. 10 to 12.
Fig. 10 is a perspective view of a terminal block of the semiconductor device of the embodiment.
Fig. 11 and 12 are perspective views of a printed circuit board and a terminal block of the semiconductor device according to the embodiment. Fig. 11 and 12 show a case where the terminal blocks 120 and 130 are disposed on the printed board 119 a.
As shown in fig. 10, the terminal blocks 120 and 130 are formed of resin after the control terminals (external connection terminals) 121 and 131 are integrally molded, and have a substantially rectangular parallelepiped shape. Gaps 122 and 132 defined by two protrusions are formed on the lower surface (second surface) side of the terminal blocks 120 and 130, respectively. The lower surfaces of the terminal blocks 120 and 130 are surfaces to be provided on the printed board 119 a. The gaps 122 and 132 penetrate from the front side to the back side of the terminal blocks 120 and 130 in the drawing. Further, stepped portions 123, 133 are formed on the sides of the surfaces of the terminal blocks 120, 130 that face each other, respectively.
Such terminal blocks 120 and 130 hold a plurality of control terminals 121 and 131. The control terminals 121 and 131 are formed to have both end portions thicker than the body portion. The terminal blocks 120 and 130 hold the main body portions of the control terminals 121 and 131, and both end portions thicker than the main body portions are formed to protrude from the upper surface (first surface) and the lower surface (second surface) of the terminal blocks 120 and 130, respectively. As described later, the lower end portions of the control terminals 121 and 131 protruding from the lower surfaces of the terminal blocks 120 and 130 in the drawing are press-fitted (press-fitted) into through holes provided in the printed board 119 a. In fig. 10, the control terminals 121 and 131 are formed in two rows on the terminal blocks 120 and 130. Thereby, the number of control terminals 121, 131 held by the terminal blocks 120, 130 can be increased as compared with the case where the control terminals 121, 131 are formed in a single row. The terminal blocks 120 and 130 are not limited to the control terminals 121 and 131 formed in two rows, but the number of control terminals 121 and 131 to be held can be further increased by forming the control terminals in three or more rows. The terminal blocks 120 and 130 are disposed at one end of the printed circuit board 119 a.
A printed board (circuit wiring board) 119a used for forming the case 110 includes a wiring layer made of a conductive material and a board made of a material having high heat resistance, and a plurality of rows of electrodes 119a1 electrically connected to the wiring layer are arranged on the front surface. The structure of the wiring layer may be any of a single layer, a structure laminated on both surfaces, and a multilayer structure. The printed board 119a is formed with a plurality of through holes 119a2 that penetrate from the upper surface (first main surface) to the lower surface (second main surface). As described later, when printed circuit board 119a is integrally molded with case 110, resin of case 110 is inserted into through-hole 119a2, whereby printed circuit board 119a is easily fixed to case 110. Preferably, the through holes 119a2 are arranged to sandwich the aligned electrodes 119a 1. By fixing the periphery of the electrode 119a1 with the resin in the through-hole 119a2, the reliability of connection of the wire 148 in the subsequent step can be improved.
Further, a pattern made of copper may be formed on the back surface of the printed substrate 119a in advance, and the surface of the pattern may be intentionally provided with unevenness by blackening treatment. Thus, when the printed circuit board 119a is integrally molded with the housing 110, the printed circuit board 119a can be easily fixed to the housing 110 by attaching the concave and convex portions on the back surface to the housing 110. The whole mold (japanese: ベタパターン) of the wiring layer on the lower surface side can also be used as the protective cover. Preferably, no residue such as resist remains on the lower surface of the printed board 119 a.
The lower end portions of the control terminals 121 and 131 protruding from the lower surfaces of the terminal blocks 120 and 130 are connected to the printed board 119a by press fitting (press fitting) so that the terminal blocks 120 and 130 are arranged. Thereby, the printed board 119a is electrically connected to the control terminals 121 and 131. As shown in fig. 12, the ends of the control terminals 121 and 131 may be exposed or protruded on the lower surfaces of the printed boards 119a and 119 b.
When the lower end portions of the control terminals 121 and 131 have the same thickness as the main body portion, the control terminals may be connected to the printed circuit board 119a by soldering without press fitting. In this case, the lower ends of the control terminals 121 and 131 penetrating the printed board 119a are soldered to the back side of the printed board 119a (from the front side of the printed board 119 a). However, soldering melts with temperature, and thus molten soldering may enter into a resin. In order to prevent such molten solder from flowing into the resin, the solder connection portions of the control terminals 121 and 131 on the back surface side of the printed circuit board 119a may be covered with an epoxy resin, and the epoxy resin may be cured. Therefore, it is preferable to press-fit the control terminals 121 and 131 to the printed board 119a rather than to use soldering.
Further, a control circuit may be provided on the printed board 119a, and electronic components and the like electrically connected to the control terminals 121 and 131 may be mounted thereon. The printed board 119b described later has the same structure as the printed board 119a, and can be treated in the same manner.
The laminated substrate 140, the printed boards 119a and 119b, and the terminal blocks 120 and 130 are prepared.
Step S12 is to integrally mold the printed boards 119a and 119b on which the terminal blocks 120 and 130 are arranged, the wiring terminal (third wiring terminal) 118, the P terminals 113a, 113b, and 113c, the N terminals 114a, 114b, and 114c, the U terminal 115a, the V terminal 115b, and the W terminal 115c, and to form the case 110 with resin.
The case 110 formed in this manner will be described with reference to fig. 13 and 14.
Fig. 13 is a plan view of the housing of the semiconductor device of the embodiment, and fig. 14 is a rear view of the housing of the semiconductor device of the embodiment.
The housing 110 is formed by injection molding using resin, for example, and has a frame shape with a recess formed in the center. In the recess in the central portion, storage portions 112a, 112b, and 112c are formed, and the stacked substrate 140 is stored in the storage portions 112a, 112b, and 112c, respectively. Printed boards 119a and 119b are disposed on the peripheral edge of the housing 112a (along the short side direction of the case 110). A pair of printed boards 119a are disposed on the peripheral edge portions (along the short side direction of the housing 110) of the housing portion 112 b. Printed boards 119a and 119b are disposed on the peripheral edge of the housing 112c (along the short side direction of the case 110). The printed boards 119a and 119b are disposed in the housing 110 by integral molding.
The housing 112a of the case 110 is provided with a P terminal 113a and an N terminal 114a on one side (lower side in the figure) in the longitudinal direction of the case 110, and a U terminal 115a on the other side (upper side in the figure). Similarly, the housing section 112b is provided with a P terminal 113b and an N terminal 114b on one side (lower side in the figure) of the housing 110 in the longitudinal direction, and a V terminal 115b on the other side (upper side in the figure). The housing 112c is provided with a P terminal 113c and an N terminal 114c on one side (lower side in the figure) of the housing 110 in the longitudinal direction, and a W terminal 115c on the other side (upper side in the figure).
Wiring terminals 118 are disposed in the respective housing portions 112a, 112b, and 112c, and the wiring terminals 118 are electrically connected to the P terminals 113a, 113b, and 113c and protrude from the P terminals 113a, 113b, and 113 c. Wiring terminal 118 has a side surface portion 118b rising from bottom surface portion 118a (orthogonal to bottom surface portion 118 a) on the side facing wiring terminal (first wiring terminal) 117 described later. The thickness of the side surface portion 118b is, for example, 1.0mm to 1.5 mm.
Terminal blocks 120 and 130 are disposed on the printed boards 119a and 119b on the U terminal 115a side of the housing portion 112a, respectively, and the control terminals 121 and 131 are electrically connected to the printed boards 119a and 119 b. The terminal blocks 120 and 130 are disposed near the U terminal 115a, the V terminal 115b, and the W terminal 115c on the longitudinal side of the housing 110, respectively.
The terminal blocks 120 and 130 are integrated with the resin of the housing 110 by integral molding. In the secondary molding, the upper and lower surfaces of the terminal blocks 120 and 130 or a side surface (third surface) between the upper and lower surfaces are welded to the heated resin, whereby the terminal blocks 120 and 130 are joined to the housing 110. As the resin, for example, a thermoplastic resin such as polyphenylene sulfide (PPS) can be used.
Step S13 is to store the laminated substrate 140 prepared in step S11b in the case 110 formed in step S12. When stored, the conductive terminals 143a of the laminated substrate 140 are joined to (the rear surface side of) the bottom surface portions 118a of the wiring terminals 118 of the housing 110.
Specifically, the laminated substrate 140 illustrated in fig. 3 is provided to a copper plate or a cooler. The case 110 is joined so that the laminated substrate 140 provided on the copper plate or the cooler is housed in the housing portions 112a, 112b, and 112c of the case 110 described in fig. 13 and 14, respectively.
Step S14 is to connect the control electrodes such as the gate electrodes of the semiconductor chips 144a, 144b, 144c to the printed board 119a using the wires 148, and to connect the control electrodes such as the gate electrodes of the semiconductor chips 146a, 146b, 146c to the printed board 119b using the wires 148.
The semiconductor chips 144a, 144b, and 144c are preferably arranged such that the control electrodes are aligned along the printed board 119 a. The same is true for the semiconductor chips 146a, 146b, 146 c. With this arrangement, the connection with the wire 148 can be easily achieved. When the RC-IGBT is used as the semiconductor chip 144a or the like, alignment of the control electrodes can be facilitated as shown in fig. 3.
As shown in fig. 1, in step S15, the wiring terminal (second wiring terminal) 116 is joined to (the flat plate portion 145aa of) one end of the U terminal 115a, the V terminal 115b, and the W terminal 115c of the case 110, the conductive terminal 143b of the laminated substrate 140, and the jumper terminal 145a, respectively, by soldering. Thereby, the wiring terminal 116, the U terminal 115a, the V terminal 115b, and the W terminal 115c, the conductive terminal 143b of the laminated substrate 140, and the jumper terminal 145a are electrically connected.
As shown in fig. 1, wiring terminal 117 is joined to (flat plate portion 145ba of) one end of N terminals 114a, 114b, and 114c and jumper terminal 145b of case 110 by soldering, respectively. Thus, wiring terminal 117 is electrically connected to N terminals 114a, 114b, and 114c and jumper terminal 145 b.
Thereby, the structure of the semiconductor device 100 as shown in fig. 1 can be obtained.
Here, the wiring terminals 116 and 117 will be described with reference to fig. 1 and 15 to 17. Fig. 15 is a perspective view of a wiring terminal of the semiconductor device of the embodiment. Fig. 16 is a cross-sectional view of the wiring terminal and the laminated substrate of the semiconductor device according to the embodiment, which is a cross-sectional view taken along the chain line X-X in fig. 1. Fig. 17 is an enlarged view of a main portion of the semiconductor device of the embodiment.
The wiring terminal 116 has a bottom surface 116a, a side surface 116b, and a side surface 116 c. As shown in fig. 1 and 17, the bottom surface portion 116a is joined to one end of the U terminal 115a, the V terminal 115b, and the W terminal 115c and the conductive terminal 143b on the back surface side (lower surface in the drawing) of the one end, and the other end extends in parallel to the printed boards 119a and 119b to the front of the wiring terminal 118.
As shown in fig. 16, the lower side (lower surface in the drawing) of the bottom surface portion 116a is supported by a stepped portion 145ac of the jumper terminal 145 a. Further, bottom surface portion 116a protrudes from step portion 145ac, and a gap is provided between the protruding portion of bottom surface portion 116a and terminal portion 145 ab. In addition, a through hole 116d that penetrates from the upper surface to the lower surface side in the drawing as shown in fig. 15 is formed in the protruding portion of the bottom surface portion 116. By providing the through hole 116d in the protruding portion of the bottom surface portion 116a in this manner, when the semiconductor 100 is encapsulated with resin, the resin can enter the through hole 116d to improve the adhesion of the resin, and the resin can be made difficult to peel off.
As shown in fig. 1, 16, and 17, the side surface portion 116b is provided as a surface that rises in an L-shape from the bottom surface portion 116a (is orthogonal to the bottom surface portion 116 a) on the side of the bottom surface portion 116a that faces the wiring terminal 117. As shown in fig. 1, 16, and 17, the side surface portion 116b is arranged parallel to a side surface portion 117b described later, joined to (the flat portion 145aa of) the jumper terminal 145a, and electrically connected to the jumper terminal 145 a.
For example, the side surface portion 116b is joined to the flat plate portion 145aa at the upper end side of the flat plate portion 145aa (the side facing the laminated substrate 140). By bonding the side surface portions 116b to the upper end side of the flat plate portion 145aa in this way, the bonded portions can be separated from the respective semiconductor chips. Accordingly, the semiconductor device 100 can reduce the stress transmitted to each semiconductor chip and the laminated substrate 140 due to the expansion of the wiring terminal 116, and the like, and can suppress the breakage and breakage of each semiconductor chip and the laminated substrate 140, thereby improving the reliability of the semiconductor device 100.
As shown in fig. 1 and 17, the side surface portion 116c is provided so as to be L-shaped (perpendicular to the bottom surface portion 116 a) rising from the bottom surface portion 116a on the side of the bottom surface portion 116a facing the wiring terminal 117, and is arranged parallel to the side surface portion 117c of the wiring terminal 117. The thickness of the side portions 116b and 116c is, for example, 1.0mm to 1.5 mm.
The wiring terminal 117 has a bottom surface 117a, a side surface 117b, and a side surface 117 c. As shown in fig. 1 and 17, the bottom surface portion 117a is joined to one end of the N terminals 114a, 114b, and 114c on the back side (lower surface in the drawing) of the one end, and the other end extends in front of the wiring terminal 116 in parallel with the printed boards 119a and 119 b.
As shown in fig. 16, the lower side (lower surface in the figure) of the bottom surface portion 117a is supported by the step portion 145bc of the jumper terminal 145 b. Further, bottom surface portion 117a protrudes from step portion 145ac, and a gap is provided between the protruding portion of bottom surface portion 117a and terminal portion 145 bb. In addition, a through hole 117d that penetrates from the upper surface to the lower surface side in the drawing as shown in fig. 15 is formed in the protruding portion of the bottom surface portion 117. By providing the through hole 117d in the protruding portion of the bottom surface 117a in this manner, when the semiconductor 100 is sealed with resin, the resin can enter the through hole 117d to improve the adhesion of the resin, and the resin can be made difficult to peel off.
As shown in fig. 1, 16, and 17, the side surface portion 117b is provided as a surface that rises in an L-shape (perpendicular to the bottom surface portion 117 a) from the bottom surface portion 117a on the side of the bottom surface portion 117a that faces the wiring terminal 116 and the wiring terminal 118. As shown in fig. 1, 16, and 17, the side surface portion 117b is arranged parallel to the side surface portions 116b and 118b described later, joined to (the flat plate portion 145ba of) the jumper terminal 145b, and electrically connected to the jumper terminal 145 b.
For example, the side surface portion 117b is joined to the flat plate portion 145ba on the upper end side of the flat plate portion 145ba (the side opposite to the laminated substrate 140). By thus bonding the side surface portions 117b to the upper end side of the flat plate portion 145ba, the bonded portions can be separated from the respective semiconductor chips. Accordingly, the semiconductor device 100 can reduce the stress transmitted to each semiconductor chip and the laminated substrate 140 due to the expansion of the wiring terminal 117, and the like, and can suppress the breakage and breakage of each semiconductor chip and the laminated substrate 140, thereby improving the reliability of the semiconductor device 100.
As shown in fig. 1 and 17, the side surface portion 117c is provided so as to rise in an L-shape from the bottom surface portion 117a (orthogonal to the bottom surface portion 117 a) on the side of the bottom surface portion 117a facing the wiring terminal 116, and is arranged parallel to the side surface portion 116c of the wiring terminal 116. The thickness of the side portions 117b and 117c is, for example, 1.0mm to 1.5 mm.
Thus, the side surface portion 116b and the side surface portion 117b are arranged in parallel with the flat plate portion 145aa, the plate portion 147a, and the flat plate portion 145ba arranged in parallel interposed therebetween.
That is, in the semiconductor device 100, the electrically connected side surface portion 117b and flat plate portion 145ba are disposed in parallel with the electrically connected side surface portion 116b and flat plate portion 145aa across the plate portion 147 a. In the semiconductor device 100, the side surface portion 116c is arranged in parallel with the side surface portion 117 c. In the semiconductor device 100, the side surface portion 117b is arranged in parallel with the side surface portion 118 b.
Step S16 is to fit the resin block into the recess of the case 110. Here, the resin block will be described with reference to fig. 18. Fig. 18 is a perspective view of a resin block of the semiconductor device of the embodiment.
The resin block 150 is formed of resin, and has a structure in which a plurality of frames are assembled into a frame shape, for example, so as to be fitted into a recess in the center portion of the semiconductor device 100. Further, since the resin block 150 is included, the semiconductor device 100 can have an improved rigidity ratio and can be reduced in deformation due to bending or twisting caused by an impact from the outside. Therefore, the semiconductor chips 144a, 144b, and 144c and the semiconductor chips 146a, 146b, and 146c in the semiconductor device 100 can be prevented from being damaged or impacted.
Step S17 is to encapsulate the laminate substrate 140, the printed boards 119a and 119b, the wiring terminals 116, 117, and 118, the wires 148, and the like in the recess of the case 110 with an encapsulating resin, and cure the encapsulating resin. Thereby, the semiconductor device 100 is completed. As the encapsulating resin, for example, an epoxy resin can be used.
Next, a circuit configuration of the semiconductor device 100 will be described with reference to fig. 1, 3, and 19. Fig. 19 is a circuit diagram showing a circuit configuration formed in the semiconductor device of the embodiment.
In the laminated substrate 140 (fig. 1 and 3) of the housing portion 112a of the semiconductor 100, the conductive terminal 143a electrically connected to the P terminal 113a via the wiring terminal 118 is electrically connected to the collector electrodes of the semiconductor chips 144a, 144b, and 144c via the circuit board 142 a. The wiring terminal 116 is electrically connected to the jumper terminal 145a electrically connected to the transmitter electrodes of the semiconductor chips 144a, 144b, and 144c, and the wiring terminal 116 is electrically connected to the U terminal 115 a.
The conductive terminal 143b is electrically connected to the wiring terminal 116 electrically connected to the U terminal 115a, and is electrically connected to the collector electrodes of the semiconductor chips 146a, 146b, and 146c via the circuit board 142 b. A wiring terminal 117 is electrically connected to the jumper terminal 145b electrically connected to the transmitter electrodes of the semiconductor chips 146a, 146b, and 146c, and the wiring terminal 117 is electrically connected to the N terminal 114 a.
In the laminated substrate 140 (fig. 1 and 3) of the housing portion 112b of the semiconductor 100, the conductive terminal 143a electrically connected to the P terminal 113b via the wiring terminal 118 is electrically connected to the collector electrodes of the semiconductor chips 144a, 144b, and 144c via the circuit board 142 a. The wiring terminal 116 is electrically connected to the jumper terminal 145a electrically connected to the transmitter electrodes of the semiconductor chips 144a, 144b, and 144c, and the wiring terminal 116 is electrically connected to the V terminal 115 b.
The conductive terminal 143b is electrically connected to the wiring terminal 116 electrically connected to the V terminal 115b, and is electrically connected to the collector electrodes of the semiconductor chips 146a, 146b, and 146c via the circuit board 142 b. A wiring terminal 117 is electrically connected to the jumper terminal 145b electrically connected to the transmitter electrodes of the semiconductor chips 146a, 146b, and 146c, and the wiring terminal 117 is electrically connected to the N terminal 114 b.
In the laminated substrate 140 (fig. 1 and 3) of the housing 112c of the semiconductor device 100, the conductive terminal 143a electrically connected to the P terminal 113c via the wiring terminal 118 is electrically connected to the collector electrodes of the semiconductor chips 144a, 144b, and 144c via the circuit board 142 a. The wiring terminal 116 is electrically connected to the jumper terminal 145a electrically connected to the transmitter electrodes of the semiconductor chips 144a, 144b, and 144c, and the wiring terminal 116 is electrically connected to the W terminal 115 c.
The conductive terminal 143b is electrically connected to the wiring terminal 116 electrically connected to the W terminal 115c, and is electrically connected to the collector electrodes of the semiconductor chips 146a, 146b, and 146c via the circuit board 142 b. A wiring terminal 117 is electrically connected to the jumper terminal 145b electrically connected to the transmitter electrodes of the semiconductor chips 146a, 146b, and 146c, and the wiring terminal 117 is electrically connected to the N terminal 114 c.
With this configuration, the circuit shown in fig. 19 is configured inside the semiconductor device 100.
Therefore, in a state where the positive electrode of the power source is connected to the P terminal 113a and the negative electrode is connected to the N terminal 114a, a control signal is input/output to/from an external circuit via the control terminals 121 and 131 and the printed boards 119a and 119 b. The control signals are input to the gate electrodes of the semiconductor chips 144a, 144b, and 144c and the semiconductor chips 146a, 146b, and 146c via the printed boards 119a and 119b and the wires 148, and are output from the U terminal 115a in accordance with the control signals.
In a state where the positive electrode is connected to the P terminal 113b and the negative electrode is connected to the N terminal 114b, a control signal is input/output via the control terminals 121 and 131 and the printed boards 119a and 119 b. In response to the control signal, the control signal is input to the gate electrodes of the semiconductor chips 144a, 144b, and 144c and the semiconductor chips 146a, 146b, and 146c via the printed boards 119a and 119b and the wire 148, and is output from the V terminal 115b in response to the control signal.
In a state where the positive electrode is connected to the P terminal 113c and the negative electrode is connected to the N terminal 114c, a control signal is input/output via the control terminals 121 and 131 and the printed boards 119a and 119 b. The control signals are input to gate electrodes of the semiconductor chips 144a, 144b, and 144c and the semiconductor chips 146a, 146b, and 146c via the printed boards 119a and 119b and the wires 148, and are output from the W terminal 115c in accordance with the control signals.
However, as described above, in the semiconductor device 100, the electrically connected side surface portion 117b and the flat plate portion 145ba are disposed in parallel to and facing the electrically connected side surface portion 116b and the flat plate portion 145aa across the plate portion 147 a. In the semiconductor device 100, the side surface portion 116c and the side surface portion 117c are arranged in parallel to face each other. In the semiconductor device 100, the side surface portion 117b and the side surface portion 118b are arranged in parallel to face each other. The area of the jumper terminal 145a and the wiring terminals 116 and 118 arranged on the P terminal (upper arm) side facing the jumper terminal 145b and the wiring terminal 117 arranged on the N terminal (lower arm) side can be increased, and the impedance of the main circuit can be reduced.
Specifically, according to the circuit configuration and the configuration of the semiconductor device 100, the magnetic field generated by the current flowing through the side surface portion 117b and the flat plate portion 145ba arranged in parallel and the magnetic field generated by the current flowing through the side surface portion 116b and the flat plate portion 145aa cancel each other out.
Further, the magnetic field generated by the current flowing through the side surface portion 117c arranged in parallel and the magnetic field generated by the current flowing through the side surface portion 116b cancel each other out.
Further, the magnetic field generated by the current flowing through the side surface portion 117b arranged in parallel and the magnetic field generated by the current flowing through the side surface portion 118b cancel each other out.
That is, in the semiconductor device 100, the magnetic field can be weakened, and the malfunction of the semiconductor device 100 due to the magnetic field can be suppressed. Thereby, in the semiconductor device 100, the reliability of the semiconductor device 100 can be improved.
Further, since each semiconductor chip is positioned by resin plate 147 sandwiched by jumper terminals 145a and 145b, the assembly process of mounting each semiconductor chip and jumper terminals 145a and 145b on laminated substrate 140 can be facilitated, and semiconductor device 100 can be downsized.
The wiring terminals 116 and 117 may be integrally molded on the back surface side of the resin block 150 so as to correspond to the housing portions 112a, 112b, and 112 c. By integrally molding the resin block 150 and the wiring terminals 116 and 117 in this manner, the wiring terminals 116 and 117 can be arranged together, and the semiconductor device 100 can be improved in the assembling property of the semiconductor device 100. In this case, it is preferable that the resin block of the housing unit is formed of resin, and the pair of wiring terminals 116 and 117 are integrally molded on the back surface of the resin block of each housing unit. By integrally molding the resin block of the housing unit and the wiring terminals 116 and 117 in this manner, the wiring terminals 116 and 117 can be guided to appropriate positions of the jumper terminals 145a and 145b, and the wiring terminals 116 and 117 can be well joined.
The wiring terminals 116 and 117 may be integrally molded with the housing 110.
The semiconductor device 100 may be a power semiconductor module of one phase including a pair of the laminated substrate 140, the semiconductor chips 144a to 144c, 146a to 146c, the jumper terminals 145a and 145b, the resin plate 147, the input terminal (P terminal 113a, N terminal 114a), and the output terminal (U terminal 115 a).

Claims (17)

1. A semiconductor device, comprising:
a laminated substrate having an insulating substrate, a first circuit board and a second circuit board, wherein the first circuit board is disposed on a front surface of the insulating substrate, and the second circuit board is disposed on the front surface side by side with the first circuit board;
a first semiconductor chip disposed on the first circuit board;
a second semiconductor chip disposed on the second circuit board;
a first crossover terminal having a first terminal portion and a first plate member, wherein the first terminal portion is electrically connected to a main electrode of the first semiconductor chip;
a second bridge terminal having a second terminal portion electrically connected to a main electrode of the second semiconductor chip and a second plate member; and
a resin plate having a first positioning portion that is placed on a front surface of the first circuit board and that defines a position of the first semiconductor chip on the first circuit board, a second positioning portion that is placed on a front surface of the second circuit board and that defines a position of the second semiconductor chip on the second circuit board, and a plate portion that is sandwiched between the first circuit board and the second circuit board by the first plate member and the second plate member,
the resin board includes:
a first insertion portion that receives insertion of the first plate member; and
a second insertion portion that receives insertion of the second plate member.
2. The semiconductor device according to claim 1,
the first plate member and the second plate member are arranged in parallel,
the first plate member and the second plate member are configured to flow currents in opposite directions.
3. The semiconductor device according to claim 1,
the plate portion is a size including an area where the first plate member and the second plate member overlap.
4. The semiconductor device according to claim 1,
the first insertion portion is provided between the plate portion and the first positioning portion,
the second insertion portion is provided between the plate portion and the second positioning portion.
5. The semiconductor device according to claim 1,
the first positioning portion has a convex shape in plan view, and the position of the first semiconductor chip is defined by two sides constituting a step portion of the convex shape,
the second positioning portion is convex in plan view, and defines a position of the second semiconductor chip with two sides constituting a step portion of the convex shape.
6. The semiconductor device according to claim 1, comprising:
a case that houses the laminated substrate;
a first external terminal provided to the case and connecting an outside and an inside of the case;
a second external terminal provided to the case adjacent to the first external terminal and connecting an outside and an inside of the case;
a third external terminal that is provided on a side of the case opposite to a side on which the first external terminal is arranged and that connects an outside and an inside of the case;
a first wiring terminal having a first bottom surface portion parallel to the laminated substrate, connected at one end to the first external terminal, and extending at the other end to the front of the third external terminal, and a first side surface portion orthogonal to the first bottom surface portion and electrically connected to the second plate member; and
a second wiring terminal having a second bottom surface portion parallel to the laminated substrate, connected at one end to the third external terminal, and extending to the front of the second external terminal at the other end, and a second side surface portion orthogonal to the second bottom surface portion and electrically connected to the first plate member.
7. The semiconductor device according to claim 6,
the first side face portion is parallel to the second plate member,
the second side face portion is parallel to the first plate member,
the first plate member, the plate portion, and the second plate member are sandwiched by the first side surface portion and the second side surface portion.
8. The semiconductor device according to claim 6, further comprising:
a third wiring terminal having a third bottom surface portion parallel to the laminated substrate, connected at one end to the second external terminal, and extending to the front of the second bottom surface portion at the other end, and a third side surface portion orthogonal to the third bottom surface portion on a side of the third bottom surface portion opposite to the first bottom surface portion,
the first side surface portion extends to a position opposite to the third side surface portion.
9. The semiconductor device according to claim 6,
opposite to the second bottom surface portion at the other end of the first bottom surface portion,
the first wiring terminal has a second first side surface portion orthogonal to the first bottom surface portion on a side of the other end of the first bottom surface portion opposite to the second bottom surface portion,
the second wiring terminal has a second side surface portion orthogonal to the second bottom surface portion on a side of the second bottom surface portion opposite to the other end of the first bottom surface portion.
10. A semiconductor device, comprising:
a laminated substrate having an insulating substrate, a first circuit board and a second circuit board, wherein the first circuit board is disposed on a front surface of the insulating substrate, and the second circuit board is disposed on the front surface side by side with the first circuit board;
a first semiconductor chip disposed on the first circuit board;
a second semiconductor chip disposed on the second circuit board;
a first crossover terminal having a first terminal portion and a first plate member, wherein the first terminal portion is electrically connected to a main electrode of the first semiconductor chip;
a second bridge terminal having a second terminal portion electrically connected to a main electrode of the second semiconductor chip and a second plate member; and
a resin plate having a first positioning portion that is placed on a front surface of the first circuit board and that defines a position of the first semiconductor chip on the first circuit board, a second positioning portion that is placed on a front surface of the second circuit board and that defines a position of the second semiconductor chip on the second circuit board, and a plate portion that is sandwiched between the first circuit board and the second circuit board by the first plate member and the second plate member,
the first positioning portion has a convex shape in plan view, and the position of the first semiconductor chip is defined by two sides constituting a step portion of the convex shape,
the second positioning portion is convex in plan view, and defines a position of the second semiconductor chip with two sides constituting a step portion of the convex shape.
11. The semiconductor device according to claim 10,
the first plate member and the second plate member are arranged in parallel,
the first plate member and the second plate member are configured to flow currents in opposite directions.
12. The semiconductor device according to claim 10,
the plate portion is a size including an area where the first plate member and the second plate member overlap.
13. The semiconductor device according to claim 10,
the resin board includes:
a first insertion portion that receives insertion of the first plate member; and
a second insertion portion that receives insertion of the second plate member,
the first insertion portion is provided between the plate portion and the first positioning portion,
the second insertion portion is provided between the plate portion and the second positioning portion.
14. The semiconductor device according to claim 10,
a case that houses the laminated substrate;
a first external terminal provided to the case and connecting an outside and an inside of the case;
a second external terminal provided to the case adjacent to the first external terminal and connecting an outside and an inside of the case;
a third external terminal that is provided on a side of the case opposite to a side on which the first external terminal is arranged and that connects an outside and an inside of the case;
a first wiring terminal having a first bottom surface portion parallel to the laminated substrate, connected at one end to the first external terminal, and extending at the other end to the front of the third external terminal, and a first side surface portion orthogonal to the first bottom surface portion and electrically connected to the second plate member; and
a second wiring terminal having a second bottom surface portion parallel to the laminated substrate, connected at one end to the third external terminal, and extending to the front of the second external terminal at the other end, and a second side surface portion orthogonal to the second bottom surface portion and electrically connected to the first plate member.
15. The semiconductor device according to claim 14,
the first side face portion is parallel to the second plate member,
the second side face portion is parallel to the first plate member,
the first plate member, the plate portion, and the second plate member are sandwiched by the first side surface portion and the second side surface portion.
16. The semiconductor device according to claim 14, further comprising:
a third wiring terminal having a third bottom surface portion parallel to the laminated substrate, connected at one end to the second external terminal, and extending to the front of the second bottom surface portion at the other end, and a third side surface portion orthogonal to the third bottom surface portion on a side of the third bottom surface portion opposite to the first bottom surface portion,
the first side surface portion extends to a position opposite to the third side surface portion.
17. The semiconductor device according to claim 14,
opposite to the second bottom surface portion at the other end of the first bottom surface portion,
the first wiring terminal has a second first side surface portion orthogonal to the first bottom surface portion on a side of the other end of the first bottom surface portion opposite to the second bottom surface portion,
the second wiring terminal has a second side surface portion orthogonal to the second bottom surface portion on a side of the second bottom surface portion opposite to the other end of the first bottom surface portion.
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