CN106449604B - A kind of SCR with high maintenance voltage for ESD protection - Google Patents
A kind of SCR with high maintenance voltage for ESD protection Download PDFInfo
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Abstract
The invention belongs to Electronics Science and Technology fields, are mainly used for electrostatic leakage guard technology, particularly relate to a kind of SCR rates with high maintenance voltage for ESD protection.The present invention proposes that ESD of the SCR device for low pressure 5V techniques is protected; the positive feedback process inside SCR structure is weakened using additional NPN transistor; the positive current feedback of SCR is set to have the tendency that decrease; so that SCR maintenance voltages rise; the latch-up immunity of device is improved, in addition, even if noise jamming occurs for chip; noise voltage makes SCR open by mistake to open, which can still ensure the normal current potential and normal transmission of signal.
Description
Technical field
The invention belongs to Electronics Science and Technology fields, are mainly used for electrostatic leakage (Electro Static
Discharge, referred to as ESD) guard technology, particularly relate to it is a kind of for ESD protection with high maintenance voltage
SCR (Silicon Controlled Rectifier, silicon-controlled).
Background technology
ESD, that is, static discharge is phenomenon universal in nature.
As integrated circuit fabrication process is reformed, more tiny line width or even thinner oxide layer make the antistatic of chip
Ability substantially reduces, therefore influence of the electrostatic to circuit is more obvious.And the deep-submicron even development of nanometer technology with it is integrated
There is also contradictions for the anti-ESD abilities of chip, therefore designer must take in.
Can betide each pin of chip in static discharge, these pins have plenty of I/O mouthfuls, have plenty of power rail or
GND。
In chip operation, I/O mouthfuls can export different logical signals, thus be added in I/O mouthfuls ESD protection modules no matter
It is the signal transmission that must not interfere with chip under the state that is switched on or off.(low-voltage triggering is controllable by LVTSCR shown in FIG. 1
Silicon) it is that a kind of trigger voltage is low, the strong ESD device of relieving capacity, but such requirement is used in the LVTSCR devices of ESD protections
Part must take into consideration accidentally overturns (such as Fig. 2 by the false triggering of voltage noise or electrostatic hence into the signal caused by depth doubled-back region
It is shown), the maintenance voltage of the generation of such case in order to prevent, ESD structures must be by I/O mouthfuls to GND of voltage clamping in electricity
It is more than source voltage, though and LVTSCR structures have very much since its big current capacity becomes one kind with smaller chip area footprints
The electrostatic prevention structure of potentiality, but due to the lower maintenance voltage of LVTSCR structures so that its use has received restriction.Similarly
Esd event it can also happen that between VDD and GND, unlike, low maintenance voltage can directly result between VDD and GND
The generation of latch (latch-up).
Invention content
It is to be solved by this invention, aiming at the above problem, the maintenance voltage of LVTSCR devices is promoted, the present invention proposes
It is a kind of to improve the design of maintenance voltage while not changing trigger voltage using adding NPN pipes and reach, and can be by adjusting
The current amplification factor of tube-carrier adjusts the maintenance voltage of SCR.
The technical scheme is that：A kind of SCR with high maintenance voltage for ESD protection, including P type substrate 1,
First p-type epitaxial layer 201 and the second p-type epitaxial layer 202, the first p-type epitaxial layer 201 and the second p-type epitaxial layer 202 are located at
Same level；1 upper surface of the P type substrate and 202 lower surface of 201 lower surface of the first p-type epitaxial layer and the second p-type epitaxial layer
Between be isolated by the first soi layer 01, by the between 202 side of 201 side of the first p-type epitaxial layer and the second p-type epitaxial layer
Two soi layers 02 are isolated；First p-type epitaxial layer, 201 upper layer has the first areas P+ 21, the 2nd areas P+ 23, the first areas N+ 22, the
Two areas N+ 24 and the first N traps 31, the first N traps 31 are located at close to the side of the second p-type epitaxial layer 202, the side of the first N traps 31
Face is contacted with the second soi layer 02, and the 2nd areas N+ 24 are located in the first N traps 31；First areas N+ 22 are located at the first areas P+
21 and the 2nd between the areas P+ 23, and the 2nd areas P+ 23 are located at close to the side of the first N traps 31；The second p-type epitaxial layer 202
Upper layer has the 3rd areas P+ 25, the 4th areas P+ 27, the 5th areas P+ 29, the 3rd areas N+ 26, the 4th areas N+ 28 and the 2nd N traps 32；Institute
The 3rd areas N+ 26 are stated between the 3rd areas P+ 25 and the 4th areas P+ 27, and the 3rd areas P+ 25 are located at close to the first p-type epitaxial layer
201 side；The half in the 4th areas P+ 27 is located in the 2nd N traps 32；4th areas N+ 28 and the 5th areas P+ 29 are located at
In 2nd N traps 32, and the 5th areas P+ 29 are located at close to the side in the 4th areas P+ 27；4th areas P+ 27 and the 5th areas P+ 29 it
Between 202 upper surface of the second p-type epitaxial layer have polysilicon gate construction；The polysilicon gate construction is by polysilicon 04 and position
Gate oxide 05 between 202 upper surface of polysilicon 04 and the second p-type epitaxial layer is constituted；First areas P+ 21 and the first N+
Area 22 is connected to device cathodes；2nd areas P+ 23, the 3rd areas P+ 25, the 3rd areas N+ 26 are connected as SCR triggering NPN crystalline substances
The approach of body pipe；2nd areas N+ 24 are connected with the 4th areas P+ 27 bypasses the way of SCR positive feedback currents as NPN transistor
Diameter；4th areas N+ 28, the 5th areas P+ 29 are connected with polysilicon gate construction is used as device anode.
Said program is to complete device in p-type epitaxial layer, if P epitaxial layers are changed to N epitaxial layers, then corresponding processing
Mode is：2nd N traps 32 are removed, and form p-well in corresponding region, difference is by the 3rd areas P+ 25 and the 3rd areas N+ 26
It is placed in p-well, while the half in the 4th areas P+ 27 is located in p-well, the principle of the two schemes is similar.
Beneficial effects of the present invention are, the present invention proposes that ESD of the SCR device for low pressure 5V techniques is protected, using additional
NPN transistor the positive feedback process inside SCR structure is weakened, so that the positive current feedback of SCR is had the tendency that decrease, from
And so that SCR maintenance voltages rise, and improve the latch-up immunity of device, in addition, even if noise jamming, noise voltage occur for chip
Make SCR open by mistake to open, which can still ensure the normal current potential and normal transmission of signal.
Description of the drawings
Fig. 1 is tradition LVTSCR structures；
Fig. 2 is noise false triggering ESD device schematic diagram；
Fig. 3 is the equivalent circuit structure schematic diagram of SCR proposed by the present invention；
Fig. 4 is the structure chart of SCR proposed by the present invention；
Fig. 5 is another realization method structure chart of SCR proposed by the present invention；
Fig. 6 is the specific implementation of SCR proposed by the present invention；
Fig. 7 is transmission line pulse (TLP) simulation comparison figure of SCR proposed by the present invention and tradition LVTSCR；
The high maintenance voltage path that Fig. 8 is provided for the present invention when releasing different mode ESD.
Specific implementation mode
With reference to the accompanying drawings and examples, detailed description of the present invention technical solution：
Embodiment 1
As shown in figure 4, the SCR with high maintenance voltage for ESD protection of this example, including P type substrate 1, the first p-type
Epitaxial layer 201 and the second p-type epitaxial layer 202, the first p-type epitaxial layer 201 and the second p-type epitaxial layer 202 are located at same water
Plane；Lead between 202 lower surface of 1 upper surface of the P type substrate and 201 lower surface of the first p-type epitaxial layer and the second p-type epitaxial layer
The isolation of the first soi layer 01 is crossed, 201 side of the first p-type epitaxial layer and the second p-type epitaxial layer pass through the 2nd SOI between 202 side
Layer 02 is isolated；First p-type epitaxial layer, 201 upper layer has the first areas P+ 21, the 2nd areas P+ 23, the first areas N+ 22, the 2nd N+
Area 24 and the first N traps 31, the first N traps 31 be located at close to the second p-type epitaxial layer 202 side, the side of the first N traps 31 with
Second soi layer 02 contacts, and the 2nd areas N+ 24 are located in the first N traps 31；First areas N+ 22 are located at 21 He of the first areas P+
Between 2nd areas P+ 23, and the 2nd areas P+ 23 are located at close to the side of the first N traps 31；The upper layer of the second p-type epitaxial layer 202
With the 3rd areas P+ 25, the 4th areas P+ 27, the 5th areas P+ 29, the 3rd areas N+ 26, the 4th areas N+ 28 and the 2nd N traps 32；Described
Three areas N+ 26 are between the 3rd areas P+ 25 and the 4th areas P+ 27, and the 3rd areas P+ 25 are located at close to the first p-type epitaxial layer 201
Side；The half in the 4th areas P+ 27 is located in the 2nd N traps 32；4th areas N+ 28 and the 5th areas P+ 29 are located at the 2nd N
In trap 32, and the 5th areas P+ 29 are located at close to the side in the 4th areas P+ 27；Between 4th areas P+ 27 and the 5th areas P+ 29
Second p-type epitaxial layer, 202 upper surface has polysilicon gate construction；The polysilicon gate construction is by polysilicon 04 and positioned at more
Gate oxide 05 between 202 upper surface of crystal silicon 04 and the second p-type epitaxial layer is constituted；First areas P+ 21 and the first areas N+ 22
It is connected to device cathodes；2nd areas P+ 23, the 3rd areas P+ 25, the 3rd areas N+ 26 are connected triggers NPN transistor as SCR
Approach；2nd areas N+ 24 are connected with the 4th areas P+ 27 bypasses the approach of SCR positive feedback currents as NPN transistor；Institute
State the 4th areas N+ 28, the 5th areas P+ 29 are connected with polysilicon gate construction and are used as device anode.
The equivalent circuit diagram of this example is as shown in figure 3, include：PNP01, NPN02, resistance 11, resistance 12, resistance 13,
NPN03, connection type are that the base stage of PNP01 is connected with the collector of NPN02, and the base stage of NPN02 is connected with the collector of PNP01
Constitute free-running circuit.The anode that one end of resistance 11 is connected with the emitter of PNP01 as the structure, another its base stage of termination.
One end of resistance 12 is connected with the base stage of NPN02, and the other end is connected with its emitter is followed by the base stage of NPN03, the current collection of NPN03
Pole connects the base stage of NPN02.The base stage of one termination NPN03 of resistance 13, another its emitter of termination and the cathode as the structure.
This example is as shown in Figure 6 in specific application：Anode meets input port or VDD, and cathode meets GND.
The operation principle of this example is：
When noise pulse is when appearing on input port, which can make that snowslide occurs by the collector junction of PNP01, electric at this time
Stream can flow through resistance 11,12.When ohmically pressure drop reaches the cut-in voltage V of PN junctionFWhen, SCR structure is triggered.Due to electricity
Stream will pass through SCR and flow into ground by resistance 13, and when 13 both ends pressure drop of resistance reaches 0.7V or so, NPN03 is opened, at this moment
The collector current of NPN03 will take the base current of NPN02 away a part, therefore the base current of NPN02 at this moment
It will be by the I of scriptB2Become IB2-IC3, therefore positive feedback will weaken than traditional SCR.The maintenance voltage of the device will be raised to compared with
High level to prevent noise caused by interfere.
When esd pulse appears in VDD, which can also be clamped the current potential of power supply to ground due to identical operation principle
Position is more than supply voltage.At this point, working as ESD blackouts, since supply voltage is less than the maintenance voltage of the structure, the knot
Structure will automatic shutoff to reach the case where avoiding latch from damaging.
Embodiment 2
As shown in figure 5, the difference of this example and embodiment 1 is, the P epitaxial layers in embodiment 1 are changed to N epitaxial layers, N traps change
For p-well, the 2nd N traps 32 are removed, and form p-well in corresponding region, difference is by the 3rd areas P+ 25 and the 3rd areas N+ 26
It is placed in p-well, while the half in the 4th areas P+ 27 is located in p-well.
Its connection type, operation principle are same as Example 1 when this example is specifically used.
When design, it should the current gain of maintenance size of current adjustment NPN03 as needed, but cannot be unlimited
The increase maintenance voltage of system.If the current gain of NPN03 increases, the base current of NPN02 is on the one hand enabled to reduce more
It is more, more inhibit SCR positive feedback effects.But its excessively high current gain equally can also reduce NPN03 when releasing ESD electric currents
Maintenance voltage.
In order to illustrate the advantage of the present invention and tradition LVTSCR structures, transmission line pulse (TLP) simulation result is given with Fig. 7
Go out.By simulation result as can be seen that novel high maintenance voltage SCR structure proposed by the present invention not only significantly improves maintenance
The value of voltage, and its trigger voltage is almost the same with tradition LVTSCR devices, in 12-13V or so.It can be seen that should
The more traditional LVTSCR devices of device have apparent anti-latching feature, therefore in 5V chips, which can be used for ESD power supplys guarantor
Shield, I/O mouthfuls of protection.It is shown in solid in current drain channel such as Fig. 7 when the device is protected for input port PS patterns.
When path of the device for being provided when being protected to 5V power supplys is shown in dotted line.When the device is used for the PD of output port
What pattern was provided when protecting releases path as indicated by the dotted lines.Pass through the TLP simulation curves of the observation to Fig. 8 and the combination device
As can be seen that the PS patterns of either input terminal, the PD patterns or power clamp pattern of output end, what which was provided
Release path maintenance voltage in 5V or more.Therefore noise voltage failure shown in Fig. 2 will not occur, VDD to the door bolt between GND
Lock effect is also reduced or eliminated.Therefore the device is very suitable for the ESD protections of low-voltage integrated circuit.
In conclusion the present invention proposes a kind of SCR_NPN composite constructions for ESD protections.The structure is due to additional
NPN pipes have certain inhibiting effect to the positive feedback effect of SCR so that when SCR open release ESD electric currents when maintenance voltage
Rise, reaches the latch-up prevented under I/O mouthfuls of noise false triggering interference and power supply power clamp patterns.Also may be used simultaneously
The adjustment to integral device maintenance voltage is realized by adjusting the current amplification factor of additional NPN pipes, therefore the present invention is especially suitable
For chip I/O mouthfuls and the ESD protections of power rail.
Claims (1)
1. a kind of SCR with high maintenance voltage for ESD protection, including P type substrate (1), the first p-type epitaxial layer (201)
With the second p-type epitaxial layer (202), the first p-type epitaxial layer (201) and the second p-type epitaxial layer (202) are located at same level
Face；P type substrate (1) upper surface and the first p-type epitaxial layer (201) lower surface and second p-type epitaxial layer (202) lower surface it
Between by the first soi layer (01) be isolated, between the first p-type epitaxial layer (201) side and second p-type epitaxial layer (202) side lead to
Cross the second soi layer (02) isolation；First p-type epitaxial layer (201) upper layer have the first areas P+ (21), the 2nd areas P+ (23),
First areas N+ (22), the 2nd areas N+ (24) and the first N traps (31), the first N traps (31) are located at close to the second p-type epitaxial layer
(202) side of side, the first N traps (31) is contacted with the second soi layer (02), and the 2nd areas N+ (24) are located at the first N traps
(31) in；First areas N+ (22) are between the first areas P+ (21) and the 2nd areas P+ (23), and the 2nd areas P+ (23) are located at
Close to the side of the first N traps (31)；The upper layer of the second p-type epitaxial layer (202) has the 3rd areas P+ (25), the 4th areas P+
(27), the 5th areas P+ (29), the 3rd areas N+ (26), the 4th areas N+ (28) and the 2nd N traps (32)；3rd areas N+ (26) are located at
Between 3rd areas P+ (25) and the 4th areas P+ (27), and the 3rd areas P+ (25) are located at one close to the first p-type epitaxial layer (201)
Side；The half of 4th areas P+ (27) is located in the 2nd N traps (32)；4th areas N+ (28) and the 5th areas P+ (29) are located at
In 2nd N traps (32), and the 5th areas P+ (29) are located at close to the side in the 4th areas P+ (27)；4th areas P+ (27) and the 5th
Second p-type epitaxial layer (202) upper surface between the areas P+ (29) has polysilicon gate construction；The polysilicon gate construction by
Polysilicon (04) and the gate oxide (05) between polysilicon (04) and second p-type epitaxial layer (202) upper surface are constituted；Institute
It states the first areas P+ (21) and the first areas N+ (22) is connected to device cathodes；2nd areas P+ (23), the 3rd areas P+ (25),
Three areas N+ (26), which are connected, triggers the approach of NPN transistor as SCR；2nd areas N+ (24) and the 4th areas P+ (27) phase continuous cropping
The approach of SCR positive feedback currents is bypassed for NPN transistor；4th areas N+ (28), the 5th areas P+ (29) and polysilicon gate
Structure, which is connected, is used as device anode.
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| CN109119416B (en) * | 2018-08-24 | 2023-03-03 | 电子科技大学 | High holding current ESD protection device |
| CN114664815B (en) * | 2022-03-18 | 2023-10-24 | 电子科技大学 | High-maintenance-voltage TVS discrete device with embedded NPN structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1396662A (en) * | 2001-07-09 | 2003-02-12 | 联华电子股份有限公司 | Low voltage triggered SCR containing Si in insulating layer and protecting circuit for electrostatic discharge |
| CN201041806Y (en) * | 2007-03-05 | 2008-03-26 | 浙江大学 | An ESD protection part for enlarging valid pass area of static current |
| CN105609488A (en) * | 2015-12-23 | 2016-05-25 | 电子科技大学 | Low-trigger-voltage SCR (semiconductor control rectifier) device used for ESD (electro-static discharge) protection |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW473977B (en) * | 2000-10-27 | 2002-01-21 | Vanguard Int Semiconduct Corp | Low-voltage triggering electrostatic discharge protection device and the associated circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1396662A (en) * | 2001-07-09 | 2003-02-12 | 联华电子股份有限公司 | Low voltage triggered SCR containing Si in insulating layer and protecting circuit for electrostatic discharge |
| CN201041806Y (en) * | 2007-03-05 | 2008-03-26 | 浙江大学 | An ESD protection part for enlarging valid pass area of static current |
| CN105609488A (en) * | 2015-12-23 | 2016-05-25 | 电子科技大学 | Low-trigger-voltage SCR (semiconductor control rectifier) device used for ESD (electro-static discharge) protection |
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