CN106444352B - A kind of clock method for synchronously measuring and system based on double buffering - Google Patents
A kind of clock method for synchronously measuring and system based on double buffering Download PDFInfo
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- 230000003139 buffering effect Effects 0.000 title claims abstract description 105
- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000001360 synchronised effect Effects 0.000 claims description 22
- 238000005259 measurement Methods 0.000 claims description 20
- 238000005070 sampling Methods 0.000 claims description 12
- 238000004891 communication Methods 0.000 claims description 5
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- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R20/00—Setting the time according to the time information carried or implied by the radio signal
- G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
- G04R20/04—Tuning or receiving; Circuits therefor
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
- G05B19/0425—Safety, monitoring
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/26—Pc applications
- G05B2219/2604—Test of external equipment
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Abstract
The present invention provides a kind of clock method for synchronously measuring and system based on double buffering, system include the DSP and FPGA in measuring device, and DSP includes data receipt unit, Data Computation Unit, first buffering area and second buffering area；Data receipt unit receives the sampled data of the FPGA in same measuring device；Any time first buffering area and second buffering area one of both save current sampled data, when it is last packet in absolute time tag TPa that DSP, which receives sampled data, the switching of currently received sampled data is saved to another buffer area, and after the data length in another buffer area reaches survey calculation data length TPm, Data Computation Unit starts to read the data in the buffer area and carries out parameter calculating, continue to save sampled data and carry out parameter calculating in former buffer area, until after the sampled data length saved reaches TPm, former buffer area does not work, switching carries out, realize that synchro measure calculates.
Description
Technical field
The present invention relates to measuring instrument simultaneous techniques field, in particular to a kind of clock synchro measure based on double buffering
Method and system.
Background technique
Power analyzer, power quality analyzer, electric power online monitoring device etc. have the instrument instrument of electric measurement function
Table, in order to generated when guaranteeing two apparatus measures same signal it is identical as a result, same measuring system difference
When position is measured using more instruments, it is necessary to have the function of clock synchro measure.
Accurate clock synchro measure function is to measuring instrument in synchronized sampling, electric energy event detection, power fault analysis
Etc. have great influence.Current method for synchronously measuring mostly uses greatly the biggish timer timing of error；Some GPS timings
Method for synchronously measuring does not account for the sampling gap problem between synchronizing cycle then, or using the mechanism of frequent clock synchronization, reduces
The precision and efficiency of measurement.These method for synchronously measuring are not able to satisfy clock synchro measure and want to measurement accuracy and efficiency
It asks.
Summary of the invention
The purpose of the present invention is to provide a kind of clock method for synchronously measuring and system based on double buffering, it is existing to solve
Some measuring devices measurement accuracy when carrying out clock synchro measure is inadequate, the technical problem under frequent clock synchronization, efficiency.
To achieve the above object, the present invention provides a kind of clock method for synchronously measuring based on double buffering, including with
Lower step:
S1:DSP creates first buffering area and second buffering area；
S2: any one time for starting the enabling signal of clock synchro measure is being received, starting DSP reception comes from
The sampled data of FPGA；
S3: currently received sampled data is saved to first buffering area, when the data length in first buffering area reaches
After survey calculation data length TPm, DSP reads the data in first buffering area and carries out parameter calculating, and second buffering area is not at this time
Work；
S4: when it is last packet in absolute time tag TPa that DSP, which receives sampled data, by currently received sampling
Data are saved to second buffering area, and after the data length in second buffering area reaches survey calculation data length TPm, DSP is read
The data in second buffering area are taken to carry out parameter calculating, first buffering area continues to save sampled data and carries out parameter meter at this time
It calculates, until first buffering area does not work after the sampled data length saved reaches TPm；
S5: when it is last packet in absolute time tag TPa that DSP, which receives sampled data, by currently received sampling
Data are saved to first buffering area, and after the data length in first buffering area reaches survey calculation data length TPm, DSP is read
The data in first buffering area are taken to carry out parameter calculating, second buffering area continues to save sampled data and carries out parameter meter at this time
It calculates, until second buffering area does not work after the sampled data length saved reaches TPm；
S6: repeating step S4 to S6, until FPGA stops data sampling.
Preferably, starting storage when the first buffering area or second buffering area start to save sampled data every time
The integral point data that first data point is absolute time tag TPa.
Preferably, the sampled data length that the DSP is read every time is TPs.
Preferably, the survey calculation data length TPm is set as TPm=n*T, wherein T is the period of measuring signal, n
For positive integer.
Preferably, in the step S4 and S5, judge that DSP receives sampled data to be last in absolute time tag TPa
The condition of one packet are as follows:
It is next whether the absolute time tag TPa of first data point of data packet belonging to present sample data reaches
Within the scope of TPa, meanwhile, whether the absolute time tag TPa of the last one data point of data packet belonging to present sample data
It has been more than or has reached within the scope of next TPa.
The clock synchronized measurement system based on double buffering that the present invention also provides a kind of, including dsp system and FPGA system
System, the dsp system include the DSP that several are set in different measuring devices, the DSP include: data receipt unit,
Data Computation Unit, first buffering area and second buffering area；
The FPGA system includes the FPGA that several are set in different measuring devices, and the FPGA is for being counted
Sampled data is obtained according to sampling；
The data receipt unit is used to receive the sampled data of the FPGA in same measuring device；
The first buffering area and second buffering area are for saving the sampled data；Wherein, first described in any time
Buffer area and second buffering area one of both save current sampled data, are absolute time mark whenever DSP receives sampled data
When signing last packet in TPa, the switching of currently received sampled data is saved to another buffer area, and whenever another buffer area
After interior data length reaches survey calculation data length TPm, Data Computation Unit start to read the data in the buffer area into
Row parameter calculates, and former buffer area continues to save sampled data and carries out parameter calculating at this time, until the sampled data length saved
After reaching TPm, former buffer area does not work, and successively switching carries out.
Preferably, the DSP is connected with RTC clock, the RTC clock is used to provide reference to clock synchronized measurement system
Clock signal.
Preferably, the data communication mode between the DSP and FPGA is upp, and DSP is connected by network with host computer.
Preferably, the FPGA is provided with satellite signal reception module, for receiving satellite time transfer signal according to
Satellite time transfer signal carries out the synchronization of the FPGA between different measuring devices.
Preferably, the sampled data of FPGA includes voltage and current, the parameter that the Data Computation Unit of DSP calculates includes function
Rate parameter, power quality parameter.
By adopting the above-described technical solution, the beneficial effects of the present invention are:
1) calculating cycle of Data Computation Unit is continuous, without any gap and omission；
2) the synchronous RTC clock by measuring instrument of clock controls, and avoids the synchronous operation of frequent progress clock, and raising is set
Received shipment line efficiency；
3) mechanism for using double buffering improves clock synchronous efficiency and easily performs；
4) it realizes and the clock of the measuring instrument fields such as any power parameter, power quality, electric power monitoring is synchronized, to event
Detection, fault location have very great help；
5) clock method for synchronously measuring is suitable for any calculating cycle, the configuration of synchronizing cycle；
6) data communication mode of upp is used between DSP and FPGA, data transmission is quickly stablized；
7) a kind of synchronized measurement system is provided, realizes the synchro measure to more instruments of different location；
8) two different instruments are realized and obtain identical measurement result when measuring same signal, it is accurate to detect
To power events.
Detailed description of the invention
Fig. 1 is the clock synchronized measurement system composition schematic diagram based on double buffering of preferred embodiment；
Fig. 2 is the DSP composition schematic diagram of preferred embodiment；
Fig. 3 is the clock synchro measure sequence chart of preferred embodiment；
Fig. 4 is that the DSP double buffering working machine of preferred embodiment charts.
Specific embodiment
In order to better illustrate the present invention, hereby with a preferred embodiment, and attached drawing is cooperated to elaborate the present invention, specifically
It is as follows:
As shown in Figure 1, present embodiments providing a kind of clock synchronized measurement system based on double buffering, including DSP system
System and FPGA system, FPGA system include the FPGA that several are set in different measuring devices, and dsp system includes several
The DSP being set in different measuring devices.Wherein, FPGA obtains sampled data for carrying out data sampling；DSP is for receiving
Sampled data from FPGA simultaneously carries out data calculating.
As shown in Fig. 2, each DSP in the present embodiment includes: data receipt unit 201, Data Computation Unit 202,
One buffer area 203 and second buffering area 204.
Data receipt unit 201 is used to receive the sampled data of the FPGA in same measuring device；
First buffering area 203 and second buffering area 204 are for saving sampled data；Wherein, any time first buffering area
And second buffering area one of both saves current sampled data, and reaches survey calculation data length in the data length of preservation
After TPm, Data Computation Unit 202 starts to read the data in the buffer area and carries out parameter calculating.Whenever DSP receives sampled data
When for last packet in absolute time tag TPa, the switching of currently received sampled data is saved to another buffer area, and every
After the data length in another buffer area reaches survey calculation data length TPm, it is slow that Data Computation Unit 202 starts to read this
The data rushed in area carry out parameter calculating, and former buffer area continues to save sampled data and carries out parameter calculating at this time, until saving
Sampled data length reach TPm after, former buffer area does not work, successively switching carry out.
DSP in the present embodiment is connected with RTC clock, which is used to provide reference to clock synchronized measurement system
Clock signal.
For data are transmitted by the way of dual port RAM between DSP and FPGA in same measuring device, and DSP and FPGA
Between data communication mode be upp, and the DSP in each measuring device pass through network (in the present embodiment for Ethernet) with it is upper
Position machine is connected, and host computer can obtain the sampled data and calculating parameter of each measuring device by ethernet communication mode.
FPGA in each measuring device is provided with GPS receiver module, for receiving the GPS time service letter from GPS satellite
Number to carry out the synchronization of the FPGA between different measuring devices according to GPS time signal.
Wherein, the FPGA sampled data in the present embodiment includes but is not limited to voltage and current, and the parameter that DSP is calculated includes
It is not limited to power parameter, power quality parameter.
It is shown in Figure 3, a kind of clock method for synchronously measuring based on double buffering provided in this embodiment, including it is following
Step:
S1:DSP creates first buffering area and second buffering area；
S2: any one time for starting the enabling signal of clock synchro measure is being received, starting DSP reception comes from
The sampled data of FPGA；
S3: currently received sampled data is saved to first buffering area, when the data length in first buffering area reaches
After survey calculation data length TPm, DSP reads the data in first buffering area and carries out parameter calculating, and second buffering area is not at this time
Work；
S4: when it is last packet in absolute time tag TPa that DSP, which receives sampled data, by currently received sampling
Data are saved to second buffering area, and after the data length in second buffering area reaches survey calculation data length TPm, DSP is read
The data in second buffering area are taken to carry out parameter calculating, first buffering area continues to save sampled data and carries out parameter meter at this time
It calculates, until first buffering area does not work after the sampled data length saved reaches TPm；
S5: when it is last packet in absolute time tag TPa that DSP, which receives sampled data, by currently received sampling
Data are saved to first buffering area, and after the data length in first buffering area reaches survey calculation data length TPm, DSP is read
The data in first buffering area are taken to carry out parameter calculating, second buffering area continues to save sampled data and carries out parameter meter at this time
It calculates, until second buffering area does not work after the sampled data length saved reaches TPm；
S6: repeating step S4 to S6, until FPGA stops data sampling.
Wherein, when the first buffering area or second buffering area start to save sampled data every time, start the of storage
The integral point data that one data point is absolute time tag TPa.
The sampled data length that DSP is read every time in the present embodiment is TPs=20ms；When DSP measures calculating every time
Data length TPm be set as TPm=n*T, wherein T be measuring signal period, n is positive integer, n value in the present embodiment
It is 10；The absolute time tag TPa=10min (such as 01:10,01:20) that dsp system synchronizes every time, i.e., it is each absolute
The 10min moment restarts synchronous calculating.Here TPs, TPm and TPa is to execute before formal data save to preset
It completes, according to the of different sizes of pre-set three parameters, executes the control to subsequent processes.
In step S4 and S5, judge that DSP receives sampled data as the condition of last packet in absolute time tag TPa
Are as follows:
It is next whether the absolute time tag TPa of first data point of data packet belonging to present sample data reaches
Within the scope of TPa, meanwhile, whether the absolute time tag TPa of the last one data point of data packet belonging to present sample data
It has been more than or has reached within the scope of next TPa.
Shown in Figure 3, the clock synchro measure sequence chart is specific as follows:
Step 1:DSP system creation two an equal amount of sync buffering area BufA and BufB.Sync buffering area receives
The sampled data of FPGA, and when data memory length reaches TPm based on dsp system computing unit progress electric parameter
It calculates
Step 2:DSP system any time is started to work, and BufA is normal operating conditions, and BufB is standby mode, at this time
Sampled data is stored in BufA, and when BufA data length is TPm, dsp system computing unit reads BufA data and carries out all kinds of electricity
The operation of gas parameter；BufB does not save data and is not used for calculating yet
Step 3: step 2 be continued until the data that dsp system receives be absolute time tag be 10min last
Packet；
BufB jumps to normal operating conditions from standby mode at this time, i.e. BufB starts to save sampled data, starts to deposit
First data point of storage is 10min integral point data, and BufB dsp system computing unit when data length reaches TPm is read
BufB data are taken to carry out the operation of all kinds of electric parameters；
BufA keeps working condition at this time.
Step 4:BufA continues to sample at the time of step 3, until BufA storage sampled data length be TPm, and
After the completion of dsp system carries out the calculating of all kinds of electric parameters to the TPm length samples data, BufA from working condition jump to
Machine state；That is BufA stops saving sampled data and for calculating.
BufB keeps normal operating conditions at this time.
Step 5: step 4 be continued until the data that dsp system receives be absolute time tag be 10min last
Packet；
BufA jumps to normal operating conditions from standby mode at this time, i.e. BufA starts to save sampled data, starts to deposit
First data point of storage is 10min integral point data, and BufA dsp system computing unit when data length reaches TPm is read
BufB data are taken to carry out the operation of all kinds of electric parameters；
BufB keeps working condition at this time.
Step 6:BufB continues to sample at the time of step 5, until BufB storage sampled data length be TPm, and
After the completion of dsp system carries out the calculating of all kinds of electric parameters to the TPm length samples data, BufB from working condition jump to
Machine state；That is BufB stops saving sampled data and for calculating.
BufA keeps normal operating conditions at this time.
Step 7: repeating step 2~step 5, until FPGA system stops data sampling.
Specifically, shown in Figure 4, BufA is named as in first buffering area the present embodiment in double buffering, second is slow
It rushes area and is named as BufB, each buffer area can store the data of n data calculating cycle length.When step S4, S5 executes,
When carrying out the switching between double buffering BufA and double buffering BufB, for the data that the two saves there are a lap, this is heavy
Folded part is judged with absolute time tag TPa for the time point of 10min, when reaching the time point, that is, is started another
Buffer area carries out data preservation, simultaneously as data packet resolving is not yet completed in the buffer area of former work, need to continue to execute to working as
The preservation of the data of a preceding data calculating cycle length (TPm) and the calculating of measurement parameter, to guarantee the complete of data.And
Another buffer area of switching reaches TPm in its data saved and starts to carry out parameter calculating.This mode ensure that two bufferings
The synchronism that the integrality and parameter that interval censored data saves calculate.
The present invention program is described in further detail with a practical application example with reference to the accompanying drawing
In the example by taking power quality instrument as an example, whether calibrating is clock synchro measure state, and verification step is as follows:
1, power quality analyzer is in clock synchronous working state；
2, the voltage dip event of a setting duration is exported to electric energy by a synchronous signal generator
Mass-synchrometer is T1 at the beginning of the rapid drawdown event；
3, it checks that power quality analyzer detects the rapid drawdown event, and records the initial time for detecting rapid drawdown event
Tm1；
4, compare Tm and T1, | Tm-T1 | < 1 period (signal period detected)；
5, the synchronization time adjustment function for closing power quality analyzer, works at least 48 hours；
6, the voltage dip of a given duration is then exported by synchronous signal generator, which opens
Time beginning is T2；
7, it checks that power quality analyzer detects the rapid drawdown event, and records the initial time for detecting rapid drawdown event
Tm2；
8, following verifying is carried out:
|T2–Tm2|<|T2–T1|/(3600*24)。
It can illustrate through the above steps:
1, step 4 explanation is when instrument opens synchronous, less than one signal period of signal time difference；
2, the verifying explanation of step 8 does not synchronize lower signal time difference and is less than after instrument closing synchronizes after 48 hours
1S。
This can prove a kind of clock method for synchronously measuring and system based on double buffering of the invention with following
Feature:
1, accurate clock synchro measure mechanism；
2, convenient and simple, it can persistently automatically keep synchro measure function.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those skilled in the art in the technical scope disclosed by the present invention, to deformation or replacement that the present invention is done, should be covered
Within protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the scope of protection of the claims.
Claims (10)
1. a kind of clock method for synchronously measuring based on double buffering, which comprises the following steps:
S1:DSP creates first buffering area and second buffering area；
S2: any one time for starting the enabling signal of clock synchro measure is being received, starting DSP is received from FPGA's
Sampled data；
S3: currently received sampled data is saved to first buffering area, when the data length in first buffering area reaches measurement
After calculating data length TPm, DSP reads the data in first buffering area and carries out parameter calculating, and second buffering area does not work at this time；
S4: when it is last packet in absolute time tag TPa that DSP, which receives sampled data, by currently received sampled data
It saves to second buffering area, after the data length in second buffering area reaches survey calculation data length TPm, DSP reads the
Data in two buffer areas carry out parameter calculating, and first buffering area continues to save sampled data and carries out parameter calculating at this time, directly
After the sampled data length saved to first buffering area reaches TPm, first buffering area does not work；
S5: when it is last packet in absolute time tag TPa that DSP, which receives sampled data, by currently received sampled data
It saves to first buffering area, after the data length in first buffering area reaches survey calculation data length TPm, DSP reads the
Data in one buffer area carry out parameter calculating, and second buffering area continues to save sampled data and carries out parameter calculating at this time, directly
After the sampled data length saved to second buffering area reaches TPm, second buffering area does not work；
S6: repeating step S4 to S6, until FPGA stops data sampling.
2. the clock method for synchronously measuring according to claim 1 based on double buffering, which is characterized in that every time described the
When one buffer area or second buffering area start to save sampled data, first data point for starting storage is absolute time tag
The integral point data of TPa.
3. the clock method for synchronously measuring according to claim 1 based on double buffering, which is characterized in that the DSP is every
The sampled data length of secondary reading is TPs.
4. the clock method for synchronously measuring according to claim 1 based on double buffering, which is characterized in that the meter
It calculates data length TPm and is set as TPm=n*T, wherein T is the period of measuring signal, and n is positive integer.
5. the clock method for synchronously measuring according to claim 1 based on double buffering, which is characterized in that the step S4
And in S5, judge that DSP receives sampled data as the condition of last packet in absolute time tag TPa are as follows:
Whether the absolute time tag TPa of first data point of data packet belonging to present sample data reaches next TPa
In range, meanwhile, whether the absolute time tag TPa of the last one data point of data packet belonging to present sample data has surpassed
It crosses or reaches within the scope of next TPa.
6. a kind of clock synchronized measurement system based on double buffering, which is characterized in that including dsp system and FPGA system, institute
Stating dsp system includes the DSP that several are set in different measuring devices, and the DSP includes: data receipt unit, data
Computing unit, first buffering area and second buffering area；
The FPGA system includes the FPGA that several are set in different measuring devices, and the FPGA is adopted for carrying out data
Sample obtains sampled data；
The data receipt unit is used to receive the sampled data of the FPGA in same measuring device；
The first buffering area and second buffering area are for saving the sampled data；Wherein, the first buffering described in any time
A buffer area in area and second buffering area is normal operating conditions, and another buffer area is standby mode, normal operating conditions
Buffer area saves current sampled data, when it is last packet in absolute time tag TPa that DSP, which receives sampled data,
First buffering area and second buffering area switch operating state: the buffer area being in standby jumps to normal operating conditions, and
Buffer area in normal operating conditions jumps as standby mode, and the switching of currently received sampled data is saved to being currently at
The buffer area of normal operating conditions, and whenever the data length in the buffer area for being currently at normal operating conditions reaches meter
After calculating data length TPm, Data Computation Unit starts to read the data progress being currently in the buffer area of normal operating conditions
Parameter calculates, and the buffer area for being now in standby mode jumps to normal operating conditions and continues to save sampled data and carry out parameter
It calculates, until being in normal operating conditions after the sampled data length that the buffer of current normal operating conditions saves reaches TPm
Buffer area jump to standby mode, and the buffer area being in standby jumps to normal operating conditions, and successively switching carries out.
7. the clock synchronized measurement system according to claim 6 based on double buffering, which is characterized in that the DSP with
RTC clock is connected, and the RTC clock is used to provide reference clock signal to clock synchronized measurement system.
8. the clock synchronized measurement system according to claim 6 based on double buffering, which is characterized in that the DSP and
Data communication mode between FPGA is upp, and DSP is connected by network with host computer.
9. the clock synchronized measurement system according to claim 6 based on double buffering, which is characterized in that the FPGA is set
It is equipped with satellite signal reception module, is filled for receiving satellite time transfer signal with carrying out different measurements according to the satellite time transfer signal
The synchronization of FPGA between setting.
10. the clock synchronized measurement system according to claim 6 based on double buffering, which is characterized in that FPGA's adopts
Sample data include voltage and current, and the parameter that the Data Computation Unit of DSP calculates includes power parameter, power quality parameter.
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| CN203522547U (en) * | 2013-09-11 | 2014-04-02 | 上海交通大学 | AC-AC variable-frequency phase-control trigger |
| CN103592843A (en) * | 2013-11-07 | 2014-02-19 | 中国电子科技集团公司第四十一研究所 | Timestamp circuit and implement method |
| CN203673288U (en) * | 2013-11-27 | 2014-06-25 | 成都飞逸计算机服务有限公司 | Multipath data acquisition device |
| CN104597802A (en) * | 2014-11-28 | 2015-05-06 | 苏州工业职业技术学院 | Super-high sampling rate of reproducible data collection system |
| CN104407511A (en) * | 2014-12-11 | 2015-03-11 | 哈尔滨工程大学 | High-precision multipath timing module for navigation system and method for acquiring timing system signal without accumulated errors |
| CN105334774A (en) * | 2015-11-24 | 2016-02-17 | 深圳怡化电脑股份有限公司 | Magnetic data acquisition method and system |
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