CN106413196B

CN106413196B - LED drive device and control method and its line voltage compensation circuit and control method

Info

Publication number: CN106413196B
Application number: CN201610971424.1A
Authority: CN
Inventors: 贾有平; 程志强
Original assignee: Chipone Technology Beijing Co Ltd
Current assignee: Chipone Technology Beijing Co Ltd
Priority date: 2016-10-31
Filing date: 2016-10-31
Publication date: 2019-01-08
Anticipated expiration: 2036-10-31
Also published as: CN106413196A

Abstract

The invention discloses a kind of LED drive devices and control method and its line voltage compensation circuit and control method.Wherein, which includes: the first circuit unit, and the first end of the first circuit unit and the first pin of LED drive device connect, the crest voltage for sample rate current detection resistance；The first end of second circuit unit, second circuit unit accesses reference voltage, is used for sampled reference voltage；Voltage compensating circuit unit, the second end of the first end of voltage compensating circuit unit, the second end of the first circuit unit and second circuit unit is connected to first node, the second end of voltage compensating circuit unit and the first pin of LED drive device connect, and are used for voltage compensation.The system delay time that the present invention solves inside existing LED drive device is not fixed, and leads to the technical issues of causing compensation insufficient or overcompensation by system delay time variation occur.

Description

LED drive device and control method and its line voltage compensation circuit and control method

Technical field

The present invention relates to LED illuminations and circuit design field, in particular to a kind of LED drive device and controlling party Method and its line voltage compensation circuit and control method.

Background technique

Fig. 1 is LED illumination application system working principle rough schematic.Electric main AC passes through rectifier bridge, filtering in figure Capacitor C1 becomes constant DC input voltage, and R, C2 are the start-up circuits of system electrification, and C3 is load LED filter capacitor, and D is continuous Diode is flowed, L is inductance, and IC is LED lighting (LED illumination) drive control chip, and RCS is setting load LED current Resistance.The access of DRAIN pin to CS pin includes power switch MOS inside IC, here it is considered that when power switch MOS is closed, The conducting resistance of access of DRAIN pin to CS pin is zero, wherein the VCC pin of IC is power pins, is connected with DC power supply It connects, for the internal circuit power supply to IC；The GND pin of IC is grounding pin, is connect with ground wire；The DRAIN pin of IC is IC Power switch MOS drain pin, connect with LED, for controlling LED operation；The CS pin of IC is inspection stream input pin, is used LED current is loaded in limitation, is connect with resistance RCS.

The simple working principle explanation of Fig. 1 system: this application system work first is in critical current mode conduction mode, i.e., When inductive current is from peak-fall to zero, switch MOS is opened, inductive current starts linear rise, and voltage is also opened on resistance RCS Begin to rise, when voltage drop is equal to internal reference voltage VREF on RCS, turns off switch MOS, inductive current is begun to decline, to zero Shi Kaiqi switch MOS, always cycle operation.

When power switch MOS is closed in IC, pass through inductance L electric current are as follows:

i_L(t)=((VIN-VLED)/L) * t,

VLED is load LED voltage drop, and t is switch MOS turn-on time point, and VIN is D/C voltage value after rectifier bridge.Pass through electricity Sense peak inrush current is IL (peak)=VREF/RCS, and VREF is chip IC internal reference voltage.So flowing through load LED's Average current is ILED=VREF/ (2*RCS).

But in real work, even if the upper voltage of RCS reaches internal reference voltage VREF, due to internal circuit blocks The response time is needed, logic circuit needs signal transmission time, cannot immediately turn off switch MOS.It is generally acknowledged that circuit module is rung It with the sum of logic circuit signal transmission time is system delay time between seasonable.In system delay time, switch MOS is still opened It opens, inductive current continues growing, which results in initial set value VREF/RCS is higher than by the peak value of inductive current, by negative LED current is carried also above setting value.And the slope for flowing through inductive current is directly proportional to input voltage VIN, when VIN becomes larger from small When, it flows through inductive current slope and also becomes larger from small, in this way since system delay causes inductance peak point current as VIN becomes larger gradually Become larger, furtherly flows through load LED current and also become larger as VIN becomes larger.System performance in this way is with regard to poor, linearly Regulation is bad, cannot meet customer need.

For this problem, the solution of existing chip in the market: setting system delay time be fixed and invariable as 200nS is handled by internal circuit, and switch MOS advance system delay time is allowed to turn off, and is thus accomplished through load LED electricity Stream is equal to initial set value, has obtained very big optimization in performance.

This solution sets precondition: thinking that system delay is constant.And system delay time is by electricity Road module response time and logic circuit signal transmission time two parts form.Logic circuit signal transmission time is due to internal electricity Source is constant, it is believed that this is time-invariant.But the internal circuit blocks response time can be with the variation of system application environment And great changes will take place, this time is not constant.Therefore switch is adjusted according to fixed system delay time MOS turn-on time inevitably encounters the problem that adjustment is inadequate or adjustment is excessive.

The internal circuit blocks response time it is non-constant the reason is as follows that: general chip interior detects RCS electricity by comparator Whether pressure reaches the reference voltage value VREF of inner setting, since RCS voltage is risen with certain slope, for theoretical, when on RCS When voltage is slightly larger than reference voltage, comparator output carries out current potential overturning immediately, turns off switch MOS.But actual conditions due to Comparator is by own gain, and bias current, the reasons such as design mismatch influence, when voltage is slightly larger than reference voltage on RCS, than Current potential overturning can't be carried out immediately compared with device output.By certain response time, could effectively overturn.This response time and The RCS voltage rate of rise has direct relation, if RCS voltage rate of rise very little, comparator just need bigger sound Between seasonable, if the RCS voltage rate of rise is very big, the comparator response time is with regard to smaller.Therefore in entire electric main 176V~264V in input range, system delay time is not constant, and the comparator response time accounts for whole system and prolongs Slow time significant proportion.

It is not fixed for the system delay time inside existing LED drive device, causes to occur by system delay time The problem of variation causes compensation insufficient or overcompensation, currently no effective solution has been proposed.

Summary of the invention

The embodiment of the invention provides a kind of LED drive devices and control method and its line voltage compensation circuit and controlling party Method is not fixed at least solving the system delay time inside existing LED drive device, causes to occur by system delay time The technical issues of variation causes compensation insufficient or overcompensation.

According to an aspect of an embodiment of the present invention, a kind of line voltage compensation circuit of LED drive device is provided, is wrapped Include: the first circuit unit, the first end of the first circuit unit and the first pin of LED drive device connect, and are used for sample rate current The crest voltage of detection resistance；The first end of second circuit unit, second circuit unit accesses reference voltage, is used for sampled reference Voltage；Voltage compensating circuit unit, the first end of voltage compensating circuit unit, the second end of the first circuit unit and second circuit The second end of unit is connected to first node, and the second end of voltage compensating circuit unit and the first pin of LED drive device connect It connects, is used for voltage compensation；Wherein, the first end connection of the first pin and current sense resistor of LED drive device, current detecting The second end of resistance is grounded.

According to another aspect of an embodiment of the present invention, a kind of line voltage compensation circuit of LED drive device is additionally provided Control method, comprising: the crest voltage of sampled reference voltage and current detection resistance；Obtain the difference of crest voltage and reference voltage Value；Crest voltage according to difference and crest voltage, after being reduced.

According to another aspect of an embodiment of the present invention, a kind of LED drive device is additionally provided, comprising: in above-described embodiment LED drive device line voltage compensation circuit.

In embodiments of the present invention, second can be passed through by the crest voltage of the first circuit sampling current sense resistor Circuit sampling reference voltage, and voltage compensation is carried out by voltage compensating circuit, to reduce the peak value electricity of current sense resistor Pressure compensates the current deviation as caused by system delay, to solve the system delay time inside existing LED drive device It is not fixed, leads to the technical issues of causing compensation insufficient or overcompensation by system delay time variation occur.Therefore, pass through this Scheme provided by the above embodiment is invented, can achieve the turn-off time of adjustment LED drive device, proof load LED current etc. In initial set value, the performance of lighting system is improved, is met customer need.

Detailed description of the invention

The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, this hair Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:

Fig. 1 is a kind of schematic diagram of LED illumination application principle according to prior art；

Fig. 2 is a kind of schematic diagram of the line voltage compensation circuit of LED drive device according to an embodiment of the present invention；

Fig. 3 a is a kind of signal of the line voltage compensation circuit of optional LED drive device according to an embodiment of the present invention Figure；

Fig. 3 b is a kind of schematic diagram of the second control circuit of optional LED drive device according to an embodiment of the present invention；

Fig. 4 is that a kind of timing of the line voltage compensation circuit of optional LED drive device according to an embodiment of the present invention is shown It is intended to；And

Fig. 5 is a kind of stream of the control method of the line voltage compensation circuit of LED drive device according to an embodiment of the present invention Cheng Tu.

Specific embodiment

In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people The model that the present invention protects all should belong in member's every other embodiment obtained without making creative work It encloses.

It should be noted that description and claims of this specification and term " first " in above-mentioned attached drawing, " Two " etc. be to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that using in this way Data be interchangeable under appropriate circumstances, so as to the embodiment of the present invention described herein can in addition to illustrating herein or Sequence other than those of description is implemented.In addition, term " includes " and " having " and their any deformation, it is intended that cover Cover it is non-exclusive include, for example, the process, method, system, product or equipment for containing a series of steps or units are not necessarily limited to Step or unit those of is clearly listed, but may include be not clearly listed or for these process, methods, product Or other step or units that equipment is intrinsic.

Embodiment 1

According to embodiments of the present invention, a kind of circuit embodiments of the line voltage compensation circuit of LED drive device are provided.

Fig. 2 is a kind of schematic diagram of the line voltage compensation circuit of LED drive device according to an embodiment of the present invention, such as Fig. 2 Shown, which includes:

First circuit unit 21, the first end of the first circuit unit and the first pin of LED drive device connect, for adopting The crest voltage of sample current sense resistor.

The first end of second circuit unit 23, second circuit unit accesses reference voltage, is used for sampled reference voltage.

Voltage compensating circuit unit 25, the first end of voltage compensating circuit unit, the second end of the first circuit unit and The second end of two circuit units is connected to first node, and the first of the second end of voltage compensating circuit unit and LED drive device Pin connection, is used for voltage compensation.

Wherein, the first end connection of the first pin and current sense resistor of LED drive device, the of current sense resistor Two ends ground connection.

Specifically, above-mentioned LED drive device can be LED drive chip or LED driving mould group, the embodiment of the present invention In by taking LED drive chip as an example, be described in detail.First pin of above-mentioned LED drive chip can be CS pin, above-mentioned Current sense resistor can be the resistance RCS of setting load LED current, above-mentioned crest voltage can be the peak of resistance RCS Threshold voltage VCSP, above-mentioned reference voltage can be VREF, and above-mentioned first node can be Z1, as shown in Figure 3a.

In a kind of optional scheme, as shown in Figure 3a, line voltage compensation circuit may include: the first circuit unit, Two circuit units and voltage compensating circuit unit, as shown in the solid box in Fig. 3 a, one end of the first circuit unit and LED are driven Reference voltage VREF is accessed in the CS pin connection of dynamic chip, one end of second circuit unit, the other end of the first circuit unit, the The other end of two circuit units and one end of voltage compensating circuit unit are connected to node Z1, voltage compensating circuit unit it is another End is connect with the CS pin of LED drive chip.Can by the crest voltage VCSP of the first circuit unit sampling resistor RCS, and By second circuit unit sampling reference voltage VREF, the electric current for flowing through the first circuit unit, which is equal to flow through, flows through second circuit list The electric current of member with flow through the sum of the electric current of voltage compensating circuit unit, if the equivalent resistance of the first circuit unit is R1, second The equivalent resistance of circuit unit is R2, and the equivalent resistance of voltage compensating circuit unit is R3, then on voltage compensating circuit unit Voltage is V=(VCSP/R1-VREF/R2) * R3, and the total voltage of voltage compensating circuit unit and resistance RCS are VCSP, then resistance Virtual voltage VCS=VCSP- (VCSP/R1-VREF/R2) * R3 on RCS, i.e., by the crest voltage VCSP and benchmark of resistance RCS The difference of voltage VREF be superimposed upon on the voltage of current sense resistor after a certain proportion of amplification, to reduce resistance The crest voltage of RCS, to compensate the current deviation as caused by system delay.

Using the above embodiment of the present invention, can by the crest voltage of the first circuit unit sample rate current detection resistance, Voltage compensation is carried out by second circuit unit sampling reference voltage, and by voltage compensating circuit unit, to reduce electric current The crest voltage of detection resistance compensates the current deviation as caused by system delay, to solve existing LED driving device Internal system delay time is not fixed, and causes to occur being changed by system delay time to cause compensation insufficient or the skill of overcompensation Art problem.Therefore, scheme provided by the above embodiment through the invention, when can achieve the shutdown of adjustment LED driving device Between, proof load LED current is equal to initial set value, improves the performance of lighting system, meets customer need.

Optionally, in the above embodiment of the present invention, the first above-mentioned circuit unit further include:

Sample circuit, the first end of sample circuit are connect with the first end of the first circuit unit.

First feedback loop, the first end of the first feedback loop and the second end of sample circuit connect, and first is negative anti- The second end of feedback loop is connect with the second end of the first circuit unit, for crest voltage to be converted to peak point current.

First resistor, the first end of first resistor are connect with the third end of the first feedback loop, and the second of first resistor End ground connection.

Specifically, above-mentioned resistance can be R2, as shown in Figure 3a.

In a kind of optional scheme, as shown in Figure 3a, the first circuit unit may include sample circuit, the first negative-feedback Loop is connected, is adopted with resistance R2, one end of sample circuit and the CS pin of LED drive chip as shown in the dotted line frame in Fig. 3 a The other end of sample circuit is connect with an input terminal of the first feedback loop, another input terminal of the first feedback loop connects It is connected to node Z1, the output end of the first feedback loop is connect with one end of resistance R2, the other end ground connection of resistance R2.Sampling electricity Road can sample the crest voltage VCSP of resistance RCS, and the first feedback loop can keep the crest voltage of resistance RCS, and The crest voltage of resistance RCS is converted into electric current, obtains peak point current, peak point current is identical as the electric current for flowing through resistance R2, electricity Hinder the electric current I of R2_R2=VCSP/R2.

Optionally, in the above embodiment of the present invention, above-mentioned sample circuit includes:

First switch, the first end of first switch and the first end of sample circuit connect.

Specifically, above-mentioned first switch can be switch S1, as shown in Figure 3a.

First amplifier, the first input end of the first amplifier and the second end of first switch connect, the first amplifier Second input terminal is connect with the output end of the first amplifier, and the output end of the first amplifier and the second end of sample circuit connect.

Specifically, the first above-mentioned amplifier can be amplifier AMP2, as shown in Figure 3a.

The first input end of first capacitor, the first end of first capacitor, the second end of first switch and the first amplifier connects It is connected to second node, the second end ground connection of first capacitor.

Specifically, above-mentioned first capacitor can be capacitor C1, above-mentioned second node can be Z2, as shown in Figure 3a.

In a kind of optional scheme, as shown in Figure 3a, sample circuit may include switch S1, amplifier AMP2 and electricity Hold C1, the CS pin of one end of switch S1 and LED drive chip connects, and the other end of switch S1, one end of capacitor C1 and puts An input terminal of big device AMP2 is connected to node Z2, the other end ground connection of capacitor C1, another input terminal of amplifier AMP2 It is connect with the output end of amplifier AMP2.When first switch S1 closure, first capacitor is started to charge, the peak of sampling resistor RCS Threshold voltage, and sampling is carried out to the crest voltage sampled by amplifier and is followed, and the crest voltage after sampling is input to First feedback loop is kept.

Optionally, in the above embodiment of the present invention, the first above-mentioned feedback loop includes:

Second switch, the first end of second switch are connect with the first end of the first feedback loop.

Specifically, above-mentioned second switch can be switch S2, as shown in Figure 3a.

Second amplifier, the first input end of the second amplifier and the second end of second switch connect, the second amplifier Second input terminal is connect with the third end of the first feedback loop.

Specifically, the second above-mentioned amplifier can be amplifier AMP3, as shown in Figure 3a.

The first input end of second capacitor, the first end of the second capacitor, the second end of second switch and the second amplifier connects It is connected to third node, the second end ground connection of the second capacitor.

Specifically, the second above-mentioned capacitor can be capacitor C2, above-mentioned third node can be Z3, as shown in Figure 3a.

The drain electrode of first field-effect tube, the first field-effect tube is connect with the second end of the first feedback loop, first effect Should the grid of pipe connect with the output end of the second amplifier, the third end of the source electrode of the first field-effect tube and the first feedback loop Connection.

Specifically, the first above-mentioned field-effect tube can be NMOS tube (N-channel field effect transistor, Negative Channel-Mental-Oxide-Semiconductor's writes a Chinese character in simplified form) N2, as shown in Figure 3a.

In a kind of optional scheme, as shown in Figure 3a, the first feedback loop may include: switch S2, capacitor C2, The output end of the amplifier AMP2 of one end and sample circuit of amplifier AMP3 and NMOS tube N2, switch S2 connects, switch S2's One input terminal of the other end, one end of capacitor C2 and amplifier AMP3 is connected to node Z3, and the other end ground connection of capacitor C2 is put Another input terminal, one end of resistance R2 and the source S of NMOS pipe N2 of big device AMP3 is connected to a bit, the grid of NMOS tube N2 Pole G is connect with the output end of amplifier AMP3, and the drain D of NMOS tube N2 is connected to node Z1.When switch S2 closure, capacitor C2 charging, the input voltage of amplifier AMP3 are CSP, and after N2 conducting, the electric current for flowing through N2 is identical as the electric current of R2, I_N2 =I_R2=VCSP/R2.

Optionally, in the above embodiment of the present invention, above-mentioned second circuit unit includes:

The first end of second feedback loop, the second feedback loop is connect with the first end of second circuit unit, is used for Reference voltage is converted into reference current.

Second resistance, the first end of second resistance are connect with the second end of the second feedback loop, and the second of second resistance End ground connection.

Specifically, above-mentioned second resistance can be resistance R1, as shown in Figure 3a.

The source electrode of second field-effect tube, the second field-effect tube is connect with DC power supply, the drain electrode of the second field-effect tube, second The third end of the grid of field-effect tube and the second feedback loop is connected to fourth node.

Specifically, the second above-mentioned field-effect tube can be PMOS tube (P-channel field-effect transistor (PEFT) transistor, Positive Channel-Mental-Oxide-Semiconductor's writes a Chinese character in simplified form) P1, above-mentioned fourth node can be node Z4, such as Fig. 3 a It is shown.

Third field-effect tube, the grid of third field-effect tube are connect with the grid of the second field-effect tube, third field-effect tube Source electrode connect with DC power supply, the drain electrode of third field-effect tube is connect with the second end of second circuit unit.

Specifically, the second above-mentioned field-effect tube can be PMOS tube P2, above-mentioned DC power supply can be VCC, such as scheme Shown in 3a.

Wherein, the second field-effect tube is identical as the size of third field-effect tube.

Specifically, PMOS tube P1 and P2 form current mirror, and P1, P2 transistor size are identical, flow through P1, P2 electric current phase Deng as shown in Figure 3a.

In a kind of optional scheme, as shown in Figure 3a, second circuit unit may include: the second feedback loop (such as Shown in solid box in Fig. 3 a), resistance R1, PMOS tube P1 and P2, the source S of PMOS tube P1 and P2 is all connected with DC power supply VCC, The grid G of PMOS tube P1 and P2 link together, and constitute current mirror, the grid G of PMOS pipe P1, the drain D of PMOS tube P1 and the Another input terminal of two feedback loops is connected to node Z4, and the drain D of PMOS tube P2 is connect with node Z1, and second is negative anti- An input terminal for presenting loop accesses reference voltage VREF, and the output end of the second feedback loop is grounded by resistance R1.When When PMOS tube P1 and P2 are connected, the electric current for flowing through PMOS tube P1 is identical as the electric current for flowing through resistance R1, and flows through resistance R1's Electric current is identical as reference current, then I_P1=I_R1=VREF/R1 flows through the electric current I of PMOS tube P2_P2=I_P1=VREF/R1.

Optionally, in the above embodiment of the present invention, the second above-mentioned feedback loop includes:

Third amplifier, the first input end of third amplifier are connect with the first end of the second feedback loop, and third is put Second input terminal of big device is connect with the second end of the second feedback loop.

Specifically, above-mentioned third amplifier can be amplifier AMP1, as shown in Figure 3a.

The grid of 4th field-effect tube, the 4th field-effect tube is connect with the output end of third amplifier, the 4th field-effect tube Source electrode connect with the second end of the second feedback loop, drain electrode and the third end of the second feedback loop of the 4th field-effect tube Connection.

Specifically, the 4th above-mentioned field-effect tube can be NMOS tube N1, as shown in Figure 3a.

In a kind of optional scheme, as shown in Figure 3a, amplifier AMP1, NMOS tube N1 constitute the second feedback loop, An input terminal of amplifier AMP1 accesses reference voltage VREF, and the grid G of NMOS tube N1 and the output end of amplifier AMP1 connect It connects, the drain D of NMOS tube N1 is connect with node Z4, the source S of NMOS tube N1, another input terminal of amplifier AMP1 and electricity One end of resistance R1 is connected to a bit.When NMOS tube N1 is connected, and PMOS tube P1 and P2 are connected, electric current, the stream of PMOS tube P1 are flowed through Electric current through NMOS tube N1 and the electric current for flowing through resistance R1 are identical, and the electric current for flowing through resistance R1 is identical as reference current, Then I_P1=I_R1=VREF/R1 flows through the electric current I of PMOS tube P2_P2=I_P1=VREF/R1.

Optionally, in the above embodiment of the present invention, above-mentioned voltage compensating circuit unit includes:

The source electrode of 5th field-effect tube, the 5th field-effect tube is connect with DC power supply, the grid of the 5th field-effect tube and The drain electrode of five field-effect tube connects, and the drain electrode of the 5th field-effect tube is connect with the first end of voltage compensating circuit unit.

Specifically, the 5th above-mentioned field-effect tube can be PMOS tube P3, above-mentioned DC power supply can be VCC, such as scheme Shown in 3a.

The source electrode of 6th field-effect tube, the 6th field-effect tube is connect with DC power supply, the grid of the 6th field-effect tube and The grid of five field-effect tube connects.

Specifically, the 6th above-mentioned field-effect tube can be PMOS tube P4, as shown in Figure 3a.

3rd resistor, the first end of 3rd resistor are connect with the drain electrode of the 6th field-effect tube, the second end of 3rd resistor with The second end of voltage compensating circuit unit connects.

Specifically, above-mentioned 3rd resistor can be resistance R3, as shown in Figure 3a.

Wherein, the 5th field-effect tube is identical as the size of the 6th field-effect tube.

Specifically, PMOS tube P3 and P4 form current mirror, and P3, P4 transistor size are identical, flow through P3, P4 electric current phase Deng as shown in Figure 3a.

In a kind of optional scheme, as shown in Figure 3a, voltage compensating circuit unit may include: resistance R3, PMOS pipe One end of P3 and P4, resistance R3 and the CS pin of LED drive chip connect, and the other end of R3 and the drain D of PMOS pipe P4 connect It connecing, the source S of PMOS tube P3 and P4 are connect with VCC, and the grid G of PMOS tube P3 and P4 link together, current mirror is constituted, The grid G of PMOS tube P3 and the drain D of PMOS tube P3 link together, and connect with node Z1.When PMOS tube P3 and P4 are connected When, the electric current for flowing through P3 and P4 is equal, and the electric current due to flowing through P3, which is equal to, to be flowed through the electric current of N2 and flow through the difference between currents of P2, then The electric current for flowing through P4 is I_P4=I_P3=I_N2-I_P2=(VCSP/R2)-(VREF/R1), while the electric current for flowing through P4 also flows through resistance Voltage drop V on R3, resistance R3_R3=I_P4* R3=VCSP* (R3/R2)-VREF* (R3/R1).

Optionally, in the above embodiment of the present invention, above-mentioned line voltage compensation circuit further include:

First control circuit unit, the first end of first control circuit unit, the first end of 3rd resistor and the 6th effect Should the drain electrode of pipe be connected to the 5th node, the second end of first control circuit unit accesses reference voltage, first control circuit list The third end of member and the first pin of LED drive device connect, for controlling the shutdown of LED drive device.

Specifically, the 5th above-mentioned node can be node Z5, as shown in Figure 3a.

7th field-effect tube, the drain electrode of the 7th field-effect tube and the second pin of LED drive device connect, the 7th field-effect The grid of pipe and the third pin of LED drive device connect, and the of the source electrode of the 7th field-effect tube and first control circuit unit The connection of four ends.

Specifically, the 7th above-mentioned field-effect tube can be NMOS tube N4, NMOS tube N4 is the MOS of super-pressure 500V, on The third pin for the LED drive chip stated can be DRAIN pin, and the third pin of above-mentioned LED drive chip can be VCC Pin, as shown in Figure 3a.

In a kind of optional scheme, as shown in Figure 3a, line voltage compensation circuit can also include: first control circuit list The DRAIN connection of first (as shown in the solid box in Fig. 3 a) and the drain D and LED drive chip of NMOS tube N4, NMOS tube N4, The grid G of inductance connection in the end DRAIN and system, NMOS tube N4 is connect with the VCC of LED driving chip, first control circuit list First input terminal (first end of i.e. above-mentioned first control circuit unit) of member and one end of resistance R3 are connected to node Z5, Second input terminal (second end of i.e. above-mentioned first control circuit unit) of first control circuit unit accesses VREF, and first The source electrode at third input terminal (the 4th end of i.e. above-mentioned first control circuit unit) and NMOS tube N4 of control circuit unit S connection, the output end (the third end of i.e. above-mentioned first control circuit unit) and LED drive chip of first control circuit unit CS pin connection.When the input voltage of the first end of first control circuit unit is more than or equal to reference voltage, the first control Circuit unit shutdown, inductive current begins to decline, and when inductive current is from peak-fall to zero, first control circuit unit is led Logical, as NMOS tube N4 and the conducting of first control circuit unit, the inductive current of LED illumination application system starts linear rise.

Optionally, in the above embodiment of the present invention, above-mentioned first control circuit unit includes:

The first end of comparator, comparator is connect with the first end of first control circuit unit, the second end of comparator with The second end of first control circuit unit connects, defeated when the input voltage of the first end for being greater than comparator when reference voltage High level out exports low level when reference voltage is less than or equal to the input voltage of the first end of comparator.

Specifically, above-mentioned comparator can be comparator Comparator, as shown in Figure 3a.

Logic circuit, the input terminal of logic circuit and the output end of comparator connect.

Specifically, above-mentioned logic circuit can be low voltage logic circuit Logic, as shown in Figure 3a.

Driving circuit, the input terminal of driving circuit and the output end of logic circuit connect.

Specifically, above-mentioned driving circuit can be high drive Driver circuit, as shown in Figure 3a.

8th field-effect tube, the grid of the 8th field-effect tube and the output end of driving circuit connect, the 8th field-effect tube Source electrode is connect with the third end of first control circuit unit, the drain electrode of the 8th field-effect tube and the 4th of first control circuit unit End connection, for turning off when the grid input low level of the 8th field-effect tube.

Specifically, the 8th above-mentioned field-effect tube can be power switch NMOS tube N3, as shown in Figure 3a.

Herein it should be noted that above system delay time is mainly by comparator Comparator response time and low pressure Logic Logic, high pressure Driver signal transmission time composition.Comparator Comparator response time and current sense resistor The RCS voltage rate of rise has much relations, and the RCS voltage rate of rise is bigger, and the response time is shorter, otherwise longer.

In a kind of optional scheme, as shown in Figure 3a, comparator Comparator, low voltage logic circuit Logic, high pressure Driving Driver circuit and switch NMOS tube N3 can form drive control chip main signal path, i.e. first control circuit list Member, an input terminal of comparator Comparator access reference voltage VREF, another input of comparator Comparator The input terminal of end connection Z5, input voltage CS-IN, low voltage logic circuit Logic and the output end of comparator Comparator Connection, the output end of low voltage logic circuit Logic are connect with the input terminal of high drive Driver circuit, low voltage logic circuit The output voltage of Logic is LVG, and the output voltage of high drive Driver circuit is HVG, high drive Driver circuit it is defeated Outlet is connect with the grid G of NMOS tube N3, and the drain D of NMOS pipe N3 is connect with the source S of NMOS tube N4, the source of NMOS tube N3 Pole S and the CS pin of LED drive chip connect.When NMOS tube N3 is connected, comparator Comparator exports high level, Then the output voltage HVG of the output voltage LVG of low voltage logic circuit Logic and high drive Driver circuit is high level, Inductive current starts linear rise, and the voltage on resistance RCS is also begun to ramp up；When the input voltage of comparator Comparator When CS-IN is more than or equal to VREF, comparator Comparator exports low level, then the output voltage of low voltage logic circuit Logic The output voltage HVG of LVG and high drive Driver circuit is low level, then NMOS tube N3 is turned off, under inductive current starts Drop, when inductive current is from peak-fall to zero, NMOS tube N3 conducting.

Second control circuit unit, the input terminal of second control circuit unit and the output end of logic circuit connect, and second First output end of control circuit unit is connect with first switch, the second output terminal and second switch of second control circuit unit Connection, for generating the first control signal of control first switch closing or opening, and control second switch closing or opening Second control signal.

In a kind of optional scheme, as shown in Figure 3b, line voltage compensation circuit can also include: second control circuit list The input terminal of member, second control circuit unit is connect with the output end of low voltage logic circuit Logic, second control circuit unit First output end is connect with switch S1, and the second output terminal of second control circuit unit is connect with switch S2.When low voltage logic electricity When the output voltage LVG of road Logic is high level, switch control signal S1, S2 is generated, the first of second control circuit unit is defeated Outlet exports high level and is closed to switch S1, control switch S1, and the second output terminal of second control circuit unit exports low level It is disconnected to switch S2, control switch S2；When the output voltage LVG of low voltage logic circuit Logic becomes low level from high level When, switch control signal S1, S2 is generated, the first output end of second control circuit unit exports low level to switch S1, control Switch S1 is disconnected, and the second output terminal of second control circuit unit exports high level to switch S2, control switch S2 closure.

Optionally, in the above embodiment of the present invention, above-mentioned second control circuit unit includes:

The input terminal of delay cell, delay cell is connect with the input terminal of second control circuit unit, delay cell it is defeated Outlet is connect with the first output end of second control circuit unit, for the high electricity of input terminal input when second control circuit unit Usually, output high level pulse controls first switch closure, when the input terminal of second control circuit unit inputs to first switch When signal becomes low level from high level, output low level to first switch controls first switch and disconnects.

Specifically, above-mentioned delay cell can be delay cell Delay, as shown in Figure 3b, it is mainly used to offset driving Driver signal transmission time, when guaranteeing efficiently sampling RCS crest voltage, the Delay time is utmostly approached Driver signal transmission time.

The output end of first phase inverter, the first phase inverter and delay cell connects.

Specifically, the first above-mentioned phase inverter can be phase inverter INV1, as shown in Figure 3b.

The first end of 4th resistance, the 4th resistance is connect with the output end of the first phase inverter.

Specifically, above-mentioned 4th resistance can be resistance R4, as shown in Figure 3b.

Third capacitor, the first end of third capacitor are connect with the second end of the 4th resistance, the second end ground connection of third capacitor.

Specifically, above-mentioned third capacitor can be capacitor C4, as shown in Figure 3b.

Second phase inverter, the input terminal of the second phase inverter, the 4th resistance second end connected with the first end of third capacitor In the 6th node.

Specifically, the first above-mentioned phase inverter can be phase inverter INV2, the 6th above-mentioned node can be node Z6, such as Shown in Fig. 3 b.

Third phase inverter, the input terminal of third phase inverter are connect with the output end of the second phase inverter.

Specifically, the first above-mentioned phase inverter can be phase inverter INV3, as shown in Figure 3b.

The grid of 9th field-effect tube, the 9th field-effect tube is connect with the output end of third phase inverter, the 9th field-effect tube Source electrode connect with DC power supply.

Specifically, the 9th above-mentioned field-effect tube can be PMOS tube P5, as shown in Figure 3b.

Tenth field-effect tube, the grid of the grid of the tenth field-effect tube, the output end of third phase inverter and the 9th field-effect tube Pole is connected to the 7th node.

Specifically, the 9th above-mentioned field-effect tube can be NMOS tube N5, the 7th above-mentioned node can be node Z7, As shown in Figure 3b.

Reference current, the input terminal of reference current are connect with the source electrode of the tenth field-effect tube, the output termination of reference current Ground.

Specifically, above-mentioned reference current can be IREF, as shown in Figure 3b.

The drain electrode of 4th capacitor, the first end, the tenth field-effect tube of the 4th capacitor is connected with the drain electrode of the 9th field-effect tube It is grounded in the second end of the 8th node, the 4th capacitor.

Specifically, the 4th above-mentioned capacitor can be capacitor C3, the 7th above-mentioned node can be node Z8, such as Fig. 3 b It is shown.In order to which before switch N3 unlatching, the stable RCS crest voltage for maintaining this period of the first feedback loop is then opened The high level time for closing S2 is less than the minimum turn-off time for switching the N3 of NMOS tube, and therefore, the time of capacitor C3 electric discharge is less than Switch the minimum turn-off time of the N3 of NMOS tube.

Schmidt trigger, the input terminal of Schmidt trigger are connect with the 8th node.

Specifically, above-mentioned Schmidt trigger can be Schmidt trigger Schmitt, as shown in Figure 3b.

Nor gate, the first input end of nor gate and the output end of Schmidt trigger connect, the second input of nor gate End is connect with the output end of the second phase inverter, and the output end of nor gate is connect with the second output terminal of second control circuit unit, For when the input terminal input high level of second control circuit unit, output low level to second switch to control second switch It disconnects, when the input terminal input signal of second control circuit unit becomes low level from high level, output high level pulse is extremely Second switch, control second switch closure.

Specifically, above-mentioned nor gate can be nor gate Nor2, as shown in Figure 3b.

In a kind of optional scheme, as best shown in figures 3 a and 3b, second control circuit unit may include: delay cell Delay, phase inverter INV1, resistance R4, capacitor C4, phase inverter INV2, phase inverter INV3, PMOS tube P5, NMOS tube N5, IREF, Capacitor C3, Schmidt trigger Schmitt and nor gate Nor2, delay cell Delay, phase inverter INV1, resistance R4, reverse phase Device INV2, phase inverter INV3, Schmidt trigger Schmitt are cascaded, an input terminal and reverse phase of nor gate Nor2 The output end of device INV2 connects, and another input terminal of nor gate Nor2 and the output end of Schmidt trigger Schmitt connect It connecing, one end of capacitor C4 and the input terminal of resistance R4 and phase inverter INV2 are connected to node Z6, and the other end of capacitor C4 is grounded, The grid G of PMOS tube P5 and NMOS pipe N5 is connected to node Z7, and the output end of phase inverter INV3 is connect with node Z7, PMOS tube The drain D of P5 and NMOS tube N5 are connected to node Z8, and the source electrode of PMOS tube P5 is connect with VCC, and the source electrode of NMOS pipe N5 passes through IREF ground connection, one end of capacitor C3, the input terminal of Schmidt trigger Schmitt are connect with node Z8, the other end of capacitor C3 Ground connection.When the output voltage LVG of low voltage logic circuit Logic is high level, carry out postponing it by delay cell Delay Afterwards, output high level to switch S1, control switch S1 be closed, after phase inverter INV1, resistance R4, phase inverter INV2, instead Phase device INV2 exports high level, and after nor gate Nor2, nor gate Nor2 exports low level to switch S2, control switch S2 It disconnects；When the output voltage LVG of low voltage logic circuit Logic becomes low level from high level, by delay cell Delay into After row delay, output low level to switch S1, control switch S1 is disconnected, by phase inverter INV1, resistance R4, phase inverter INV2 Later, phase inverter INV2 exports low level, and phase inverter INV3 exports high level, PMOS tube P5 shutdown, NMOS pipe N5 conducting, electricity Hold C3 electric discharge, before capacitor C3 electric discharge terminates, Schmidt trigger Schmitt input high level, Schmidt trigger Schmitt exports low level, and after nor gate Nor2, nor gate Nor2 exports high level to switch S2, control switch S2 Closure, after capacitor C3 electric discharge terminates, Schmidt trigger Schmitt input low level, Schmidt trigger Schmitt High level is exported, after nor gate Nor2, nor gate Nor2 exports low level to switch S2, control switch S2 disconnection.

A kind of preferred embodiment of the present invention is described in detail below with reference to Fig. 3 a, Fig. 3 b and Fig. 4, such as Fig. 3 a institute Show, amplifier AMP1 in Fig. 3 a, NMOS N1 constitute feedback loop, obtain the reference current I for flowing through PMOS P1_P1=VREF/ R1.PMOS P1 and P2 form current mirror, and P1, P2 transistor size are identical, flow through P1, and P2 electric current is equal.PMOS P3 and P4 Current mirror is formed, and P3, P4 transistor size are identical, flow through P3, P4 electric current is equal.Switch switch1, amplifier AMP2 and Capacitor C1 constitutes resistance RCS crest voltage sample circuit.Switch switch2, capacitor C2, amplifier AMP3 and NMOS N2 are constituted Feedback loop circuit, to keep RCS crest voltage, while RCS crest voltage is converted into electric current, and flow through N2, I_N2= VCSP/R2, VCSP are the RCS crest voltage sampled.The electric current for flowing through PMOS P4 is I_P4=(VCSP/R2)-(VREF/ R1), while flowing through the electric current of P4 and also flow through resistance R3, the voltage drop V on resistance R3_R3=VCSP* (R3/R2)-VREF* (R3/ R1).Comparator Comparator, low voltage logic circuit Logic, high drive Driver circuit and switch NMOS N3, which are formed, to be driven Dynamic control chip main signal path.As shown in Figure 3b, circuit in fig 3b is for generating switch control signal S1, S2.Control Signal S1, S2 high level processed, switch switch1, switch2 closure, on the contrary it disconnects.Delay cell Delay is mainly used in figure Driving Driver signal transmission time is offset, when guaranteeing efficiently sampling RCS crest voltage, the Delay time is maximum Degree is close to Driver signal transmission time.NMOS N4 is the MOS of super-pressure 500V, and inductance connects in the end DRAIN and system It connects.The switch end NOMS N3Source is connected with the resistance RCS of detection load LED current.

The design principle of this compensation method is illustrated in conjunction with timing as shown in Figure 4: assuming that the first job period There is no offset voltage, resistance R3 does not have pressure drop, and mono- input terminal CS-IN voltage of comparator Comparator and resistance RCS are powered on Pressure is the same.When switch NMOS N3 closure, logic Logic output signal LVG, driving Driver output signal HVG are high Level.When resistance RCS voltage reaches VREF, by comparator Comparator response time, logic Logic transmission delay Afterwards, LVG signal is lower by height, and switch switch1 is generated after Delay and controls signal S1, is also lower by height, switch1 is disconnected It opens, completes the sampling of RCS crest voltage.HVG signal after following closely is also lower by height, turns off the switch NMOS N3.At this moment it samples To RCS crest voltage VCSP be greater than internal reference voltage VREF.When S1 is lower by height, by phase inverter INV3, PMOS The circuit that P5, NMOS N5, reference current IREF, capacitor C3, Schmidt trigger Schmitt and nor gate Nor2 are constituted generates The control signal S2 of switch switch2.S2 high level time is less than the switch NMOS N3 minimum turn-off time and (opens in order to prevent Pass frequency is too high, and such chip is typically designed the minimum turn-off time), it is therefore an objective to before switch N3 unlatching, stable is maintained The RCS crest voltage in this period.R3=2*R1=2*R2 (proportionality coefficient is fine-tuning) is designed herein, the pressure drop of such resistance R3 VR3=(VCSP-VREF) * 2 is equivalent to one offset voltage V of increase on the basis of resistance RCS voltage_R3, opened at adjacent two It closes in the period, due to busbar voltage V_INConstant, the resistance RCS voltage rate of rise is constant, i.e., system delay is constant.It is equivalent to CS- When IN crest voltage is equal to VCSP, N3 is just turned off.RCS superiors's threshold voltage VCS=VCSP-VR3=VREF- (VCSP- in this way VREF), upper period resistance RCS crest voltage VCS=VREF+ (VCSP-VREF).Simultaneously this periodic sampling, maintain R_CSCrest voltage is VREF- (VCSP-VREF), is less than VREF, and the electric current for flowing through P4 is zero, no pressure drop on resistance R3, CS-IN voltage is equal to CS voltage, and in next duty cycle just without offset voltage, the work recycled like this is gone down.In phase In the adjacent duty cycle, once there are 2 times of (VCSP-VREF) offset voltages, once without offset voltage, two neighboring duty cycle Interior, RCS peak averaging voltage can be approximately considered VREF.It is exactly that adjacent periods frequency is different that design, which brings another benefit, in this way Sample can play improvement result to a certain extent to system electromagnetic interference.

As shown in figure 4, VREF is internal reference voltage, CS is pressure drop waveform on resistance RCS, and S1, S2 are switch Switch1, switch2 switch control si anal waveforms, CSP are the RCS crest voltage that sampling maintains, maximum value VREF+ (VCSP-VREF), minimum value is VREF- (VCSP-VREF).

Calculate the average current that load LED is flowed through after line voltage compensation, in order to which calculation formula is succinctly clear, resistance The crest voltage of RCS and the difference of internal reference voltage are as follows:

Δ V=VCSP-VREF,

When switch MOS closure, according to inductance characteristic, the relationship for obtaining the electric current for flowing through inductance and its voltage drop is for example inferior Formula:

Wherein V_INIt is the D/C voltage after rectifier bridge, V_LEDFor the voltage drop for loading LED.It, can according to application system requirement Know that the peak point current for flowing through inductance is

Wherein, VREF is internal reference voltage, and RCS is the resistance that load LED current is flowed through in setting.It obtains in a cycle Switch MOS opening time t_ON, turn-off time t_OFFAnd switch periods, equation are as follows:

t_ON=(L*I_P)/(V_IN-V_LED), t_OFF=L*I_P/V_LED,

According to design philosophy described above, obtain adjacent periods flow through the sum of inductance peak point current, difference, the sum of period, Difference are as follows:

Obtaining the two neighboring period flows through the average current of inductance and is

And it is not compensated, the average electricity of inductance is flowed through since each periodic voltage current waveform is consistent, in a cycle Stream is

Due to Δ V < VREF, (Δ V/VREF)²< < Δ V/VREF, it is evident that adjust compensated electricity by line voltage Road flows through the electric current of load LED closer to preset current value VREF/ (2*RCS).

For example, V_IN=300V, V_LED=80V, I_LED=200mA, L=2.2mH, VREF=400mV.It is computed RCS=1 Ω, t_ON=4uS, t_OFF=11uS, T=15uS, F=1/T=66.7kHz, if system delay t_Delay=200nS, obtains

Δ V=20mV, Δ V/VREF=1/20, (Δ V/VREF)²=1/400,

Load LED current is flowed through after being compensated is

It is not compensated flow through load LED current be

It can be seen that performance has obtained very big optimization, but is not still fully compensated after line voltage compensation.The reason is that I In order to fairly set out design philosophy, and simplify and calculate, it is believed that the R3=2*R1=2*R2 in Fig. 3 a.It is now assumed that R3=(K+ 1) * R1=(K+1) * R2 obtains flowing through the following equation of average current of inductance:

See from equation, as long as accomplishing T₁=K*T₂, so that it may it realizes and is fully compensated.

If a=Δ V/VREF, equation can simplify are as follows:aK²- K+a+1=0.

If Δ V=20mV, VREF=400mV, a=1/20 obtain K ≈ 1.1.So working as R3=2.1*R1=2.1*R2, just It may be implemented to be fully compensated, flow through the average current of inductance

Embodiment 2

According to embodiments of the present invention, a kind of side of the control method of the line voltage compensation circuit of LED drive device is provided Method embodiment, it should be noted that step shown in the flowchart of the accompanying drawings can be in such as a group of computer-executable instructions Computer system in execute, although also, logical order is shown in flow charts, in some cases, can be with Shown or described step is executed different from sequence herein.

Fig. 5 is a kind of stream of the control method of the line voltage compensation circuit of LED drive device according to an embodiment of the present invention Cheng Tu, as shown in figure 5, this method comprises the following steps:

Step S502, the crest voltage of sampled reference voltage and current detection resistance.

Specifically, above-mentioned LED drive device can be LED drive chip or LED driving mould group, the embodiment of the present invention In by taking LED drive chip as an example, be described in detail.Above-mentioned current sense resistor can be the electricity of setting load LED current RCS is hindered, above-mentioned crest voltage can be the crest voltage VCSP of resistance RCS, and above-mentioned reference voltage can be VREF.

Step S504 obtains the difference of crest voltage and reference voltage.

Step S506, according to the crest voltage in difference and crest voltage, after being reduced.

In a kind of optional scheme, as shown in Figure 3a, line voltage compensation circuit may include: the first circuit unit, Two circuit units and voltage compensating circuit unit, as shown in the solid box in Fig. 3 a.Electricity can be sampled by the first circuit unit The crest voltage VCSP of RCS is hindered, and by second circuit unit sampling reference voltage VREF, flows through the electric current of the first circuit unit Equal to the sum of the electric current for flowing through the electric current for flowing through second circuit unit Yu flowing through voltage compensating circuit unit, if the first circuit list The equivalent resistance of member is R1, and the equivalent resistance of second circuit unit is R2, and the equivalent resistance of voltage compensating circuit unit is R3, then Voltage on voltage compensating circuit unit is V=(VCSP/R1-VREF/R2) * R3, voltage compensating circuit unit and resistance RCS Total voltage be VCSP, then the virtual voltage on resistance RCS be VCS=VCSP- (VCSP/R1-VREF/R2) * R3, i.e., according to peak The difference and crest voltage of threshold voltage and reference voltage, the crest voltage after being reduced, also i.e. by the peak value of resistance RCS The difference of voltage VCSP and reference voltage VREF carries out the voltage that a certain proportion of amplification is superimposed upon current sense resistor later On, so that the crest voltage of resistance RCS is reduced, to compensate the current deviation as caused by system delay.

Optionally, in the above embodiment of the present invention, when the conducting of the 8th field-effect tube, control first switch closure, and After first preset time that is delayed, control second switch is disconnected.

Specifically, the 8th above-mentioned field-effect tube can be power switch NMOS tube N3, above-mentioned first switch be can be Switch S1, when the first above-mentioned preset time can be the transmission of the control signal of second control circuit unit transmission second switch Between, above-mentioned second switch can be switch S2, as best shown in figures 3 a and 3b.

In a kind of optional scheme, as best shown in figures 3 a and 3b, comparator Comparator, low voltage logic circuit Logic, High drive Driver circuit and switch NMOS tube N3 can form drive control chip main signal path, and second control circuit can With include: delay cell Delay, phase inverter INV1, resistance R4, capacitor C4, phase inverter INV2, phase inverter INV3, PMOS tube P5, NMOS tube N5, IREF, capacitor C3, Schmidt trigger Schmitt and nor gate Nor2.When power switch NMOS tube N3 is connected When, low voltage logic circuit Logic exports high level, after delay cell, output high level to switch S1, control switch S1 Closure, and after phase inverter INV1, resistance R4, phase inverter INV2, phase inverter INV2 exports high level, by nor gate After Nor2, nor gate Nor2 exports low level to switch S2, control switch S2 disconnection.

Optionally, in the above embodiment of the present invention, after the conducting of the 8th field-effect tube, the above method further include:

Step S508, crest voltage and reference voltage are compared.

Specifically, above-mentioned crest voltage and reference voltage can be respectively input comparator input voltage CS-IN and Input voltage VREF, as shown in Figure 3a.

Step S510 if crest voltage is more than or equal to reference voltage, control the 8th field-effect tube shutdown, and controls the One switch disconnects.

Step S512, after second preset time that is delayed, control second switch closure.

Specifically, the second above-mentioned preset time can be the control signal of second control circuit unit transmission second switch Transmission time.

Step S114, after the third preset time that is delayed, control second switch is disconnected.

Specifically, above-mentioned third preset time can be the discharge time of the 4th capacitor.

In a kind of optional scheme, as best shown in figures 3 a and 3b, as the input voltage CS-IN of comparator Comparator When more than or equal to VREF, comparator Comparator export low level, then the output voltage LVG of low voltage logic circuit Logic and The output voltage HVG of high drive Driver circuit becomes low level from high level, then NMOS pipe N3 is turned off, inductive current It begins to decline, the output voltage LVG of low voltage logic circuit Logic is by after delay cell delay, and output low level is to opening S1 is closed, control switch S1 is disconnected, and after phase inverter INV1, resistance R4, phase inverter INV2, phase inverter INV2 exports low electricity Flat, phase inverter INV3 exports high level, PMOS tube P5 shutdown, and NMOS tube N5 is connected, capacitor C3 electric discharge, terminates in capacitor C3 electric discharge Before, Schmidt trigger Schmitt input high level, Schmidt trigger Schmitt exports low level, by nor gate After Nor2, nor gate Nor2 exports high level and is closed to switch S2, control switch S2, after capacitor C3 electric discharge terminates, applies Schmitt trigger Schmitt input low level, Schmidt trigger Schmitt exports high level, after nor gate Nor2, Nor gate Nor2 exports low level to switch S2, control switch S2 disconnection.

Embodiment 3

According to embodiments of the present invention, a kind of product embodiments of LED drive device are provided, comprising: any in embodiment 1 The line voltage compensation circuit of one LED drive device.

Specifically, above-mentioned LED drive device can be LED drive chip or LED driving mould group, the embodiment of the present invention In by taking LED drive chip as an example, be described in detail.

Embodiment 4

According to embodiments of the present invention, a kind of embodiment of the method for the control method of LED drive device is provided, comprising: real Apply the control method of the line voltage compensation circuit of the LED drive device of any one of example 2.

The serial number of the above embodiments of the invention is only for description, does not represent the advantages or disadvantages of the embodiments.

In the above embodiment of the invention, it all emphasizes particularly on different fields to the description of each embodiment, does not have in some embodiment The part of detailed description, reference can be made to the related descriptions of other embodiments.

In several embodiments provided herein, it should be understood that disclosed technology contents can pass through others Mode is realized.Wherein, the apparatus embodiments described above are merely exemplary, such as the division of the unit, Ke Yiwei A kind of logical function partition, there may be another division manner in actual implementation, for example, multiple units or components can combine or Person is desirably integrated into another system, or some features can be ignored or not executed.Another point, shown or discussed is mutual Between coupling, direct-coupling or communication connection can be through some interfaces, the INDIRECT COUPLING or communication link of unit or module It connects, can be electrical or other forms.

The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple On unit.It can some or all of the units may be selected to achieve the purpose of the solution of this embodiment according to the actual needs.

It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list Member both can take the form of hardware realization, can also realize in the form of software functional units.

If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product When, it can store in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words It embodies, which is stored in a storage medium, including some instructions are used so that a computer Equipment (can for personal computer, server or network equipment etc.) execute each embodiment the method for the present invention whole or Part steps.And storage medium above-mentioned includes: that USB flash disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited Reservoir (RAM, Random Access Memory), mobile hard disk, magnetic or disk etc. be various to can store program code Medium.

The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered It is considered as protection scope of the present invention.

Claims

1. a kind of line voltage compensation circuit of LED drive device characterized by comprising

First circuit unit, the first end of first circuit unit and the first pin of LED drive device connect, for sampling The crest voltage of current sense resistor；

The first end of second circuit unit, the second circuit unit accesses reference voltage, for sampling the reference voltage；

Voltage compensating circuit unit, the first end of the voltage compensating circuit unit, the second end of first circuit unit and The second end of the second circuit unit is connected to first node, the second end of the voltage compensating circuit unit and the LED First pin of driving device connects, and is used for voltage compensation, wherein by the crest voltage of the current sense resistor and the base The difference of quasi- voltage be superimposed upon on the voltage of the current sense resistor after a certain proportion of amplification, thus described in reducing The crest voltage of current sense resistor, to compensate the current deviation as caused by system delay；

Wherein, the first end connection of the first pin and current sense resistor of the LED drive device, the current sense resistor Second end ground connection.

2. line voltage compensation circuit according to claim 1, which is characterized in that first circuit unit further include:

Sample circuit, the first end of the sample circuit are connect with the first end of first circuit unit；

The first end of first feedback loop, first feedback loop is connect with the second end of the sample circuit, described The second end of first feedback loop is connect with the second end of first circuit unit, for being converted to the crest voltage Peak point current；

First resistor, the first end of the first resistor are connect with the third end of first feedback loop, first electricity The second end of resistance is grounded.

3. line voltage compensation circuit according to claim 2, which is characterized in that the sample circuit includes:

First switch, the first end of the first switch are connect with the first end of the sample circuit；

The first input end of first amplifier, first amplifier is connect with the second end of the first switch, and described first Second input terminal of amplifier is connect with the output end of first amplifier, and the output end of first amplifier is adopted with described The second end of sample circuit connects；

First capacitor, the first of the first end of the first capacitor, the second end of the first switch and first amplifier Input terminal is connected to second node, the second end ground connection of the first capacitor.

4. line voltage compensation circuit according to claim 2, which is characterized in that first feedback loop includes:

Second switch, the first end of the second switch are connect with the first end of the first feedback loop；

The first input end of second amplifier, second amplifier is connect with the second end of the second switch, and described second Second input terminal of amplifier is connect with the third end of first feedback loop；

Second capacitor, the first of the first end of second capacitor, the second end of the second switch and second amplifier Input terminal is connected to third node, the second end ground connection of second capacitor；

The drain electrode of first field-effect tube, first field-effect tube is connect with the second end of first feedback loop, described The grid of first field-effect tube is connect with the output end of second amplifier, the source electrode of first field-effect tube and described the The third end of one feedback loop connects.

5. line voltage compensation circuit according to claim 1, which is characterized in that the second circuit unit includes:

Second feedback loop, the first end of second feedback loop are connect with the first end of the second circuit unit, For the reference voltage to be converted to reference current；

Second resistance, the first end of the second resistance are connect with the second end of second feedback loop, second electricity The second end of resistance is grounded；

The source electrode of second field-effect tube, second field-effect tube is connect with DC power supply, the drain electrode of second field-effect tube, The third end of the grid of second field-effect tube and second feedback loop is connected to fourth node；

Third field-effect tube, the grid of the third field-effect tube are connect with the grid of second field-effect tube, the third The source electrode of field-effect tube is connect with the DC power supply, the drain electrode of the third field-effect tube and the of the second circuit unit The connection of two ends；

Wherein, second field-effect tube is identical as the size of the third field-effect tube.

6. line voltage compensation circuit according to claim 5, which is characterized in that second feedback loop includes:

Third amplifier, the first input end of the third amplifier are connect with the first end of second feedback loop, institute The second input terminal for stating third amplifier is connect with the second end of second feedback loop；

The grid of 4th field-effect tube, the 4th field-effect tube is connect with the output end of the third amplifier, and the described 4th The source electrode of field-effect tube is connect with the second end of second feedback loop, the drain electrode of the 4th field-effect tube and described the The third end of two feedback loops connects.

7. line voltage compensation circuit according to claim 1, which is characterized in that the voltage compensating circuit unit includes:

The source electrode of 5th field-effect tube, the 5th field-effect tube is connect with DC power supply, the grid of the 5th field-effect tube It is connect with the drain electrode of the 5th field-effect tube, the drain electrode of the 5th field-effect tube and the of the voltage compensating circuit unit One end connection；

The source electrode of 6th field-effect tube, the 6th field-effect tube is connect with the DC power supply, the 6th field-effect tube Grid is connect with the grid of the 5th field-effect tube；

3rd resistor, the first end of the 3rd resistor are connect with the drain electrode of the 6th field-effect tube, the 3rd resistor Second end is connect with the second end of the voltage compensating circuit unit；

8. line voltage compensation circuit according to claim 1, which is characterized in that the line voltage compensation circuit further include:

First control circuit unit, the first end of the first control circuit, the first end of 3rd resistor and the 6th field-effect tube Drain electrode be connected to the 5th node, the second end of the first control circuit accesses the reference voltage, the first control electricity The third end on road is connect with the first pin of the LED drive device, for controlling the shutdown of the LED drive device；

The drain electrode of 7th field-effect tube, the 7th field-effect tube is connect with the second pin of the LED drive device, and described The grid of seven field-effect tube is connect with the third pin of the LED drive device, the source electrode of the 7th field-effect tube with it is described 4th end of first control circuit connects.

9. line voltage compensation circuit according to claim 8, which is characterized in that the first control circuit unit includes:

Comparator, the first end of the comparator are connect with the first end of the first control circuit unit, the comparator Second end is connect with the second end of the first control circuit unit, for being greater than the of the comparator when the reference voltage When the input voltage of one end, high level is exported, when the reference voltage is less than or equal to the input electricity of the first end of the comparator When pressure, low level is exported；

Logic circuit, the input terminal of the logic circuit are connect with the output end of the comparator；

Driving circuit, the input terminal of the driving circuit are connect with the output end of the logic circuit；

The grid of 8th field-effect tube, the 8th field-effect tube is connect with the output end of the driving circuit, and described 8th The source electrode of effect pipe is connect with the third end of the first control circuit unit, the drain electrode of the 8th field-effect tube and described the 4th end of one control circuit unit connects, for turning off when the grid input low level of the 8th field-effect tube.

10. line voltage compensation circuit according to claim 1, which is characterized in that the line voltage compensation circuit further include:

Second control circuit unit, the input terminal of the second control circuit unit and the output end of logic circuit connect, described First output end of second control circuit unit is connect with first switch, the second output terminal of the second control circuit unit with Second switch connection for generating the first control signal for controlling the first switch closing or opening, and controls described the Two second control signals for closing the switch or disconnecting.

11. line voltage compensation circuit according to claim 10, which is characterized in that the second control circuit unit packet It includes:

Delay cell, the input terminal of the delay cell are connect with the input terminal of the second control circuit unit, the delay The output end of unit is connect with the first output end of the second control circuit unit, for working as the second control circuit unit Input terminal input high level when, output high level pulse controls the first switch closure, when described to the first switch When the input terminal input signal of second control circuit unit becomes low level from high level, output low level to described first is opened It closes, controls the first switch and disconnect；

First phase inverter, first phase inverter are connect with the output end of the delay cell；

The first end of 4th resistance, the 4th resistance is connect with the output end of first phase inverter；

Third capacitor, the first end of the third capacitor are connect with the second end of the 4th resistance, and the of the third capacitor Two ends ground connection；

Second phase inverter, the of the input terminal of second phase inverter, the second end of the 4th resistance and the third capacitor One end is connected to the 6th node；

Third phase inverter, the input terminal of the third phase inverter are connect with the output end of second phase inverter；

The grid of 9th field-effect tube, the 9th field-effect tube is connect with the output end of the third phase inverter, and the described 9th The source electrode of field-effect tube is connect with DC power supply；

Tenth field-effect tube, the output end and the 9th field-effect tube of the grid of the tenth field-effect tube, the third phase inverter Grid be connected to the 7th node；

Reference current, the input terminal of the reference current are connect with the source electrode of the tenth field-effect tube, the reference current Output end ground connection；

4th capacitor, the drain electrode of the first end, the tenth field-effect tube of the 4th capacitor and the 9th field-effect tube Drain electrode is connected to the 8th node, the second end ground connection of the 4th capacitor；

Schmidt trigger, the input terminal of the Schmidt trigger are connect with the 8th node；

Nor gate, the first input end of the nor gate are connect with the output end of the Schmidt trigger, the nor gate Second input terminal is connect with the output end of second phase inverter, the output end of the nor gate and the second control circuit list The second output terminal connection of member, for exporting low level when the input terminal input high level of the second control circuit unit To the second switch, control the second switch and disconnect, when the second control circuit unit input terminal input signal from When high level becomes low level, output high level pulse to the second switch controls the second switch closure.

12. a kind of control method of the line voltage compensation circuit of LED drive device characterized by comprising

Pass through the crest voltage of second circuit unit and the first circuit unit sampled reference voltage and current detection resistance respectively, In, the first end of first circuit unit and the first pin of LED drive device connect, and the first of the second circuit unit It terminates into reference voltage, the first pin of the LED drive device is connect with the first end of the current sense resistor, the electricity Flow the second end ground connection of detection resistance；

The difference of the crest voltage and the reference voltage is obtained by voltage compensating circuit unit, wherein the voltage is mended The second end for repaying the first end of circuit unit, the second end of first circuit unit and the second circuit unit is connected to One node, the second end of the voltage compensating circuit unit are connect with the first pin of the LED drive device；

By the voltage compensating circuit unit according to the difference and the crest voltage, crest voltage after being reduced, Wherein, the difference of the crest voltage of the current sense resistor and the reference voltage fold after a certain proportion of amplification It is added on the voltage of the current sense resistor, so that the crest voltage of the current sense resistor is reduced, to compensate by system Current deviation caused by delay.

13. according to the method for claim 12, which is characterized in that when the conducting of the 8th field-effect tube, control first switch Closure, and after first preset time that is delayed, control second switch disconnects.

14. according to the method for claim 13, which is characterized in that after the 8th field-effect tube conducting, the side Method further include:

The crest voltage and the reference voltage are compared；

If the crest voltage is more than or equal to the reference voltage, the 8th field-effect tube shutdown is controlled, and control institute State first switch disconnection；

After second preset time that is delayed, control second switch closure；

After the third preset time that is delayed, controls the second switch and disconnect.

15. a kind of LED drive device characterized by comprising the driving dress of LED described in any one of claim 1 to 11 The line voltage compensation circuit set.

16. a kind of control method of LED drive device characterized by comprising described in any one of claim 12 to 14 LED drive device line voltage compensation circuit control method.