CN106411316A - Technology mapping method for lookup table - Google Patents
Technology mapping method for lookup table Download PDFInfo
- Publication number
- CN106411316A CN106411316A CN201610805256.9A CN201610805256A CN106411316A CN 106411316 A CN106411316 A CN 106411316A CN 201610805256 A CN201610805256 A CN 201610805256A CN 106411316 A CN106411316 A CN 106411316A
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- China
- Prior art keywords
- logic
- gate
- ring
- combinational logic
- logic circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
Abstract
The invention discloses a technology mapping method for a lookup table. The method comprises the following steps of disconnecting a one-end circuit connection between a first logic gate and a second logic gate which form a combinational logic ring in a logic circuit when the logic circuit is determined to have the combinational logic ring; an external input is inserted into a disconnected first input end of the first logic gate, and an external output is inserted into a disconnected second output end of the second logic gate; carrying out lookup table mapping on the logic circuit after the combinational logic ring is disconnected; and recovering the combinational logic ring in the logic circuit and deleting the external input and the external output. When the logic circuit is determined to have the combinational logic ring, firstly, the one-end circuit connection between the first logic gate and the second logic gate which form the combinational logic ring is disconnected, and the external input and the external output are respectively inserted on the disconnection places, and then the lookup mapping is carried out on the logic circuit after the combinational logic ring is disconnected. Through the method, the lookup table mapping is carried out on the logic circuit comprising the combinational logic ring.
Description
Technical field
The present invention relates to electronic technology field, more particularly, to a kind of look-up table process mapping method.
Background technology
(it is rich that (Field-Programmable Gate Array, abbreviation FPGA) is that one kind has to field programmable gate array
The logical device of rich hardware resource, powerful parallel processing capability and flexible configurability.These features make FPGA in data
A lot of field such as process, communication, network has obtained increasingly being widely applied.Application with FPGA is more and more extensive, for
Requirement on devices on fpga chip also more and more higher.Design using fpga chip becomes increasingly complex, and combinational logic ring occurs
Frequency is also more and more frequent, therefore, requirement more and more higher to the complex optimum ability of FPGA.Traditional Technology Mapping flow process
In, premise that logic gates is mapped as look-up table is handled logic circuit can abstract be a directed acyclic graph.And
In real process, combinational logic ring is frequently present in logic circuit, concrete as shown in figure 1, the going out of these combinational logic rings
Existing, bring unnecessary trouble to look-up table mapping, therefore, find a kind of logic electricity that can process and comprise combinational logic ring
The method on road so as to can equivalent abstract for directed acyclic graph, be problem demanding prompt solution.
Content of the invention
In order to solve the above problems, the present invention provides a kind of look-up table process mapping method.
In a first aspect, the invention provides a kind of look-up table process mapping method, methods described includes：
When determining that logic circuit has combinational logic ring, disconnect the first logic constituting combinational logic ring in logic circuit
A terminal circuit between door and the second gate connects；
The first input end being disconnected in the first gate inserts outside input, and is disconnected in the second gate
It is first defeated that the outside output of the second output end insertion connecting, wherein outside input and outside output are all equivalent to the first gate
Enter the input at end, or the output of the second output end of the second gate；
Logic circuit after open combinations logic box is made a look up with table mapping；
Recover the combinational logic ring in logic circuit, and delete outside input and outside output.
Preferably, disconnect the one end constituting between the first gate of combinational logic ring and the second gate in logic circuit
Before circuit connects, the method also includes：Traversal logic circuit, searches the combinational logic ring in logic circuit.
The look-up table process mapping method that the present invention provides, when there is combinational logic ring in determining logic circuit, first
Disconnect and constitute one end connection between the first gate and the second gate in combinational logic ring, and disconnecting place, divide
Cha Ru not outside input and outside output.Then mapping is made a look up to the logic circuit after open combinations logic box.By this
Method it is achieved that make a look up table mapping to the logic circuit comprising combinational logic ring.
Brief description
Fig. 1 is the one of the prior art logic circuit structure schematic diagram that there is combinational logic ring；
A kind of Fig. 2 look-up table process mapping method schematic flow sheet provided in an embodiment of the present invention；
Fig. 3 is the combinational logic ring disconnecting in logic circuit provided in an embodiment of the present invention, and inserts outside input with outward
The logical construction schematic diagram of portion's output；
Fig. 4 is that the present invention implements to provide, on the basis of the logic circuit shown in Fig. 1, respectively in input/output port plus
Enter the logic circuit structure schematic diagram after buffer；
Fig. 5 is the look-up table result schematic diagram of acquisition after look-up table mapping provided in an embodiment of the present invention；
Fig. 6 is deletion outside input output provided in an embodiment of the present invention, recovers the look-up table result after combinational logic ring
Schematic diagram.
Specific embodiment
Below by drawings and Examples, technical scheme is described in further detail.
A kind of Fig. 2 look-up table process mapping method schematic flow sheet 200 provided in an embodiment of the present invention.As shown in the figure 2, should
Method includes：
Step 210, when determining that logic circuit has combinational logic ring, disconnects and constitutes combinational logic ring in logic circuit
A terminal circuit between first gate and the second gate connects.
Specifically, the as shown in Figure 1 one logic circuit structure schematic diagram that there is combinational logic ring, deposits when having determined
In combinational logic ring, the terminal circuit between the first gate and the second gate that will constitute in combinational logic ring connects disconnected
Open.
Step 220, the first input end being disconnected in the first gate inserts outside input, and in the second logic
The outside output of the second output end insertion that door is disconnected.
Specifically, the first input end being disconnected in the first gate inserts outside input PI_A, in the second logic
Door is disconnected the second output end insertion outside output PO_A of link, specifically as shown in Figure 3.
Reader should be understood that PI_A and PO_A here does not have any practical significance in fact, just hopes that explanation will be combined
A terminal circuit in logic box, i.e. connection electricity between the input b of "AND" gate A2 and the output end of "AND" gate A3
Road disconnects, then the b input of A2 needs to connect an input bus, and the output end of A3 needs also exist for always connecting an output
Line.And the output of the input of external input terminals PI_A and outside output end PO_A is exactly equivalent to the b input of gate A2
Input, or the output of the output end of gate A3.Now, logic box has been eliminated, and can complete the mapping process of look-up table
?.Specifically as described in step 230.
Step 230, makes a look up table mapping to the logic circuit after open combinations logic box.
Specifically, specifically as shown in figure 5, here gate A0 in Fig. 3 and A2 are mapped to look-up table (Look-Up-
Table, abbreviation LUT) on LUT1, and by gate A0, A1 and A3 is mapped on look-up table LUT2.
Detailed process includes：
Because gate A0 in Fig. 3 and A2 are mapped in the look-up table LUT1 in Fig. 5, gate A0 and A2 have altogether and include
Three inputs, input D and input C, and the 3rd input PI_A, three that are respectively mapped to look-up table LUT1 defeated
Enter end, and output end Q is mapped to the output end of LUT1；
Gate A0 in Fig. 3, A1 and A3 is mapped on look-up table LUT2, gate A0, the input included by A1 and A3
Hold as input D, input C and Q end, output end is NQ and PI_O.
Certainly, herein only for a specific example that logic circuit is mapped to look-up table, but logic
Circuit can be mapped as different look-up tables, other mapping modes are similar with this example, repeat no more according to different combinations.And
Specifically how the look-up table after mapping is determined according to a logic circuit, then the mask value according to look-up table determines, that is, first
According to the input value in logic circuit, obtain the truth table of a logic circuit output valve.And this truth table exactly look-up table
Corresponding mask value.When the input value of logic circuit is different it may be determined that different output valves.So according to this output valve
To determine corresponding look-up table.
Certainly, open combinations logic box is exactly to realize logic circuit to the mapping of look-up table, after completing mapping,
There is still a need for recovering combinational logic ring present in original logic circuit.Therefore, the method also includes step 240.
Step 240, recovers combinational logic ring, and deletes outside input and outside output.
Specifically as shown in fig. 6, recovering the combinational logic ring in logic circuit, and delete outside input and outside output.
Optionally, constitute between the first gate of combinational logic ring and the second gate in disconnecting logic circuit
Before terminal circuit connects, the method also includes：Step 205, travels through logic circuit, searches combinational logic ring.
Detailed process is：
In present specification, illustrate as a example the logic circuit shown in only by Fig. 1, other logic circuits are similar to, this
In repeat no more.
Firstly, it is necessary to explanation, the method for lookup combinational logic ring is the typical method in graph theory, each " logic device
Part " (hereinafter referring both to block or block unit) all one of corresponding diagram (figure in graph theory) nodes.Therefore for table
State conveniently, for the interface of input and output, we insert a buffer respectively, its meaning is exactly that interface is converted into one
Equivalent block, so that search is all block with the element of the team that joins the team out, you can is one by problem equivalent conversion and schemes
The problem of search.
Therefore, step a, distinguishes Buffer insertion bufferblock in the output port that initially enters of logic circuit.Specifically
As shown in Figure 4.Fig. 4 is provided in an embodiment of the present invention, on the basis of the logic circuit shown in Fig. 1, respectively in input/output terminal
Logic circuit structure schematic diagram after mouth addition buffer.
Firstly, because the thought in lookup combinational logic ring is that all of gate is all added to the queue of first in first out
In A, then look up the block unit of the input and output of each gate, when the logic determining that some block unit is located
Door, when being labeled twice in search procedure, then illustrates that the gate that this block unit is located may belong to composition combinational logic
One gate of ring.And find combinational logic ring in order to more preferable realization, insert respectively in input port D and C-terminal
Input buffer, for example, be respectively designated as IBUF0 and IBUF1, and inserts output caching respectively in output port Q and NQ end
Device, and it is named as OBUF0 and OBUF1.
Step b, OBUF0 and OBUF1 is added in fifo queue A, and IBUF0 is labeled as with IBUF1
checked.The thought searching combinational logic ring is to find input from output end, so needing first by IBUF0 and IBUF1
It is labeled as checked, in order to determine the terminal of lookup.
It should be understood that mentioned here be labeled as checked, represent this node, and this node fully enter node all
Complete to check and determination is not included in any combinations logic box, and when fully entering of a node all has been labeled as
During checked, then illustrate that this node can be marked as checked.
And hereinafter, it will make referrals to a certain node and be marked as checking, and checking represent this node (
Refer specifically to gate in Fig. 4) and this node fully enter node before be visited, but even can not
Enough determine this node whether in combinational logic ring.And the necessary and sufficient condition that there is combinational logic ring is, one is marked as
The node of checking is accessed again.
Step c, according to the principle of first in first out, takes out buffer OBUF0, wherein first from fifo queue A
The block unit of OBUF0 does not have any mark, including being accessed for marking Checking or checked
Mark checked.So, to determine whether the block unit of its input AND gate A2 has first labeled, determine A2's
Block unit also without any mark, so, temporarily not can determine that OBUF0 whether there is combinational logic ring it is impossible to enough by it
Block unit be labeled as checked, its block unit first can only be labeled as checking.And A2 is put into queue
In A.
Step d, takes out OBUF1, similar, the block unit of OBUF1 did not do any mark from queue A, and
The input of OBUF1 is AND gate A3, and the block unit of A3 was also without doing any mark, then temporarily can not determine
OBUF1 whether there is combinational logic ring, can only temporarily be marked as checking.And take out OBUF1 from queue A, and will
Its input A3 is added in queue A.
Step e, takes out A2 from queue A because A2 did not do any mark, determine its input as AND gate A0 and
AND gate A3.A0 and A3 did not equally do any process, so, temporarily A2 is labeled as checking, and takes out from queue A
A2, and A0 and A3 is added in queue.
Step f, because that now queue includes is A3, A0 and A3, here, in order to preferably distinguish, by queue
The A3 once adding is named as A3 (1), and the A3 of second addition is named as A3 (2).According to the order of FIFO, need to take
Go out A3 (1), because now A3 (1) did not equally do any process, determine that its input is respectively AND gate A1 and AND gate
A2, because A1 did not do any process, and A2 is also only labeled as checking, rather than checked, so, equally not
Can determine that whether A3 (1) belongs to one of composition combinational logic ring gate, temporarily can only be marked as checking, and
It is taken out from queue, A1 and A2 is added in queue.
Step g, according to first in first out order, takes out A0 from queue A, because A0 was never done any mark,
Determine that it inputs as IBUF0 and IBUF1 because distinguished before labeled IBUF0 and IBUF1 be checked it is possible to
Determine that A0 is not belonging to constitute one of combinational logic ring gate, checked can be marked as, it is taken from queue
Go out.
Step h, takes out A3 (2) from queue, because, before by its labeled checking, and now once more
It is removed, then explanation A3 (2) belongs to one of composition combinational logic ring gate.There is combinational logic in this logic circuit
Ring.Now, lookup finishes.
Understand in order to convenient reader, again A3 (1) and A3 (2) is made additional remarks here：In above-mentioned steps
In, A3 occurs twice in queue altogether, and A3 for the first time is in step d it is possible to be named as A3 (1), second
A3 is in step e, is designated as A3 (2).
So, reduce above all gates add the order in queue A should to be：
OBF01 and OBF02, A2, A3 (1), A0 and A3 (2).So, determine that A0 is not belonging to composition combination and patrols in step g
After collecting the gate of ring, then according to the order of first in first out, will take out the gate being processed should be A3 (2).
In step h, retrieve A3.And judge A3 marked checking in queue, and this time taken
Go out, then explanation A3 belongs to one of composition combinational logic ring gate.There is combinational logic ring in this logic circuit, need
Carry out the process of next step, that is, eliminate combinational logic ring, complete the mapping of look-up table.The concrete step eliminating combinational logic ring is
Through being discussed in detail in step 210～220.
In addition, reader should understand that, above-mentioned lifted lookup combinational logic ring in a specific logic circuit, eliminate
Combinational logic ring, completes look-up table mapping, and the process of recovery combinational logic ring, an only specific embodiment.
Search combinational logic ring in other logic circuits, elimination combinational logic ring completes look-up table mapping and recovers combinational logic ring
Process with above described in mode similar, repeat no more here.
In addition it is also necessary to explanation, the method above stating the lookup combinational logic ring of introduction, when it is applied to a tool
When in the logic circuit of body, a combinational logic ring can only be inquired every time.Corresponding, the method eliminating combinational logic ring is also same
Sample be every execution once, eliminate a combinational logic ring.Therefore, when there is multiple combinational logic ring in a logic circuit,
Then need to repeat above-mentioned steps.Till confirming not having the presence of combinational logic ring in logic circuit, and eliminating
After combinational logic ring, then IBUF and OBUF of insertion is removed from logic circuit.
The look-up table process mapping method that the present invention provides, when there is combinational logic ring in determining logic circuit, first
Constitute the terminal circuit between the first gate and the second gate in combinational logic ring in logic circuit to be disconnected to connect, and
Disconnect place, respectively insertion outside input and outside output.Then the logic circuit after open combinations logic box is looked into
Look for mapping.With it, achieve that the logic circuit comprising combinational logic ring is made a look up with table mapping.
Professional should further appreciate that, each example describing in conjunction with the embodiments described herein
Unit and algorithm steps, can be hard in order to clearly demonstrate with electronic hardware, computer software or the two be implemented in combination in
Part and the interchangeability of software, generally describe composition and the step of each example in the above description according to function.
These functions to be executed with hardware or software mode actually, the application-specific depending on technical scheme and design constraint.
Professional and technical personnel can use different methods to each specific application realize described function, but this realization
It is not considered that it is beyond the scope of this invention.
The step of the method in conjunction with the embodiments described herein description or algorithm can be with hardware, computing device
Software module, or the combination of the two is implementing.Software module can be placed in random access memory (RAM), internal memory, read-only storage
(ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field
In interior known any other form of storage medium.
Above-described specific embodiment, has been carried out to the purpose of the present invention, technical scheme and beneficial effect further
Describe in detail, be should be understood that the specific embodiment that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, all any modification, equivalent substitution and improvement within the spirit and principles in the present invention, done etc., all should comprise
Within protection scope of the present invention.
Claims (2)
1. a kind of look-up table process mapping method is it is characterised in that methods described includes：
When determining that logic circuit has combinational logic ring, disconnect in described logic circuit and constitute the first of described combinational logic ring
A terminal circuit between gate and the second gate connects；
The first input end being disconnected in described first gate inserts outside input, and in described second gate quilt
The outside output of the second output end insertion disconnecting, wherein said outside input and described outside output are all equivalent to described the
The input of the first input end of one gate, or the output of the second output end of described second gate；
Logic circuit after open combinations logic box is made a look up with table mapping；
Recover the combinational logic ring in described logic circuit, and delete described outside input and described outside output.
2. method according to claim 1 constitutes described combinational logic ring it is characterised in that disconnecting in described logic circuit
The first gate and the second gate between one terminal circuit connect before, methods described also includes：Travel through described logic electricity
Road, searches the combinational logic ring in described logic circuit.
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| CN201610805256.9A CN106411316B (en) | 2016-09-06 | 2016-09-06 | A kind of look-up table process mapping method |
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| CN201610805256.9A CN106411316B (en) | 2016-09-06 | 2016-09-06 | A kind of look-up table process mapping method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112784511A (en) * | 2019-11-11 | 2021-05-11 | 杭州起盈科技有限公司 | Automatic dismantling method for combined logic loop |
| CN117250480A (en) * | 2023-11-08 | 2023-12-19 | 英诺达(成都)电子科技有限公司 | Loop detection method, device, equipment and storage medium of combinational logic circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101771408A (en) * | 2010-01-05 | 2010-07-07 | 中国人民解放军信息工程大学 | FPGA hardware element generating method and device |
| US8896344B1 (en) * | 2013-01-04 | 2014-11-25 | Altera Corporation | Heterogeneous programmable device and configuration software adapted therefor |
-
2016
- 2016-09-06 CN CN201610805256.9A patent/CN106411316B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101771408A (en) * | 2010-01-05 | 2010-07-07 | 中国人民解放军信息工程大学 | FPGA hardware element generating method and device |
| US8896344B1 (en) * | 2013-01-04 | 2014-11-25 | Altera Corporation | Heterogeneous programmable device and configuration software adapted therefor |
Non-Patent Citations (2)
| Title |
|---|
| TAKAYUKI SUYAMA等: ""LUT-based FPGA technology mapping using permissible functions"", 《PROCEEDINGS OF 9TH INTERNATIONAL CONFERENCE ON VLSI DESIGN》 * |
| 谢小东: "可编程逻辑核关键技术研究", 《中国博士学位论文全文数据库 信息科技辑》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112784511A (en) * | 2019-11-11 | 2021-05-11 | 杭州起盈科技有限公司 | Automatic dismantling method for combined logic loop |
| CN112784511B (en) * | 2019-11-11 | 2023-09-22 | 杭州起盈科技有限公司 | Automatic dismantling method for combinational logic loop |
| CN117250480A (en) * | 2023-11-08 | 2023-12-19 | 英诺达(成都)电子科技有限公司 | Loop detection method, device, equipment and storage medium of combinational logic circuit |
| CN117250480B (en) * | 2023-11-08 | 2024-02-23 | 英诺达(成都)电子科技有限公司 | Loop detection method, device, equipment and storage medium of combinational logic circuit |
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| CN106411316B (en) | 2019-03-05 |
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