CN106411269A - Current feedback type instrument amplifier with low power consumption and low noise - Google Patents
Current feedback type instrument amplifier with low power consumption and low noise Download PDFInfo
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- CN106411269A CN106411269A CN201611115802.2A CN201611115802A CN106411269A CN 106411269 A CN106411269 A CN 106411269A CN 201611115802 A CN201611115802 A CN 201611115802A CN 106411269 A CN106411269 A CN 106411269A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
- H03F1/342—Negative-feedback-circuit arrangements with or without positive feedback in field-effect transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45376—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using junction FET transistors as the active amplifying circuit
- H03F3/45381—Long tailed pairs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/372—Noise reduction and elimination in amplifier
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Abstract
The invention discloses a current feedback type instrument amplifier with low power consumption and low noise. The amplifier is composed of an input preprocessing circuit I0, an operational transconductance amplification circuit I1 and a capacitive feed-back network I2, wherein the operational transconductance amplification circuit I1 comprises an input transconductance branch circuit and a feed-back transconductance branch circuit. Under the condition of same transistor length, the width to length ratio of an input transconductance difference transistor pair, namely a PMOS transistor PM10 and a PMOS transistor PM11, is N times of the width to length ratio of a feed-back transconductance difference transistor pair, namely a PMOS transistor PM12 and a PMOS transistor PM13, and the width to length ratio of a bias transistor pair, namely a PMOS transistor PM14 is N times of the width to length ratio of a PMOS transistor PM15, wherein N is greater than 1. By geometric scaling of the current of the feed-back transconductance branch circuit and the width to length ratio of the transistors of the feed-back transconductance branch circuit, the power consumption and noise of the current feedback type instrument amplifier are reduced.
Description
Technical field
The present invention relates to IC design technical field is and in particular to a kind of low-power consumption low-noise current feedback-type instrument
Amplifier.
Background technology
With fast developments such as biomedical sensing technology, integrated circuit techniques, portable worn using battery operated
Equipment of wearing gets more and more, and research and development low-power consumption, the integrated circuit of low noise are the portable electric subsystems realizing high-quality durable
System basis and in the urgent need to low-power consumption Low Noise Design is the important optimization design object of portable electric appts.
The problems such as the faced noise of the biomedical low frequency signal collection in wearable device and DC maladjustment, mesh
Front usual way is to carry out performance optimization using technology such as copped waves.And the imbalance of common mode present in processing of biomedical signals
Voltage can pre-process being suppressed every straight function of circuit using input, adopt current feedback instrument amplifier to improve simultaneously
Common-mode rejection ratio.But, in traditional current feedback instrument amplifier, due to input mutual conductance branch road and feedback mutual conductance branch road
Transistor breadth length ratio identical.Contrast current feedback instrument amplifier and common folded common source and common grid amplifier understand, by
In increased feedback mutual conductance branch road, its output noise and power consumption all can accordingly increase.Thus be highly desirable to biomedicine
In the integrated circuit of signal transacting front end, traditional noise of current feedback instrument amplifier and power consumption performance are designed optimizing.
Content of the invention
The technical problem to be solved is that noise present in existing current feedback instrument amplifier is larger
The problem higher with power consumption, provides a kind of low-power consumption low-noise current feedback-type instrument amplifier.
For solving the above problems, the present invention is achieved by the following technical solutions：
A kind of low-power consumption low-noise current feedback-type instrument amplifier, is amplified by input pretreatment circuit I 0, operation transconductance
Circuit I 1 and capacitive feedback network I2 composition；Described operation transconductance amplifying circuit I1 includes inputting mutual conductance branch road and feedback mutual conductance is propped up
Road；Input mutual conductance is propped up route PMOS transistor PM10, PMOS transistor PM11 and PMOS transistor PM14 and is constituted；Feedback mutual conductance is propped up
Route PMOS transistor PM12, PMOS transistor PM13 and PMOS transistor PM15 are constituted；In transistor length identical situation
Under, input mutual conductance difference transistor is feedback mutual conductance difference to the breadth length ratio of i.e. PMOS transistor PM10 and PMOS transistor PM11
To i.e. PMOS transistor PM12 and the breadth length ratio of PM13 N times of transistor, and bias transistor to i.e. PMOS transistor PM14 width
Long ratio is N times of the breadth length ratio of PMOS transistor PM15；Above-mentioned N is more than 1.
In such scheme, the span of described N is between 1～10.
In such scheme, the in-phase input end VIP0 of input pretreatment circuit I 0 forms the in-phase input end of this amplifier
VIP, the inverting input VIN0 of input pretreatment circuit I 0 forms the inverting input VIN of this amplifier；Input pretreatment electricity
Differential inphase output end VOUTP0 of road I0 meets the homophase differential input end VIP1 of operation transconductance amplifying circuit I1；Input pretreatment
The difference reversed-phase output VOUTN0 of circuit I 0 meets the anti-phase differential input end VIN1 of operation transconductance amplifying circuit I1；Operation transconductance
The homophase feedback input end VFBP of amplifying circuit I1 meets the in-phase output end VOUTP2 of capacitive feedback network I2；Operation transconductance amplifies
The inverting feedback input VFBN of circuit I 1 meets the reversed-phase output VOUTN2 of capacitive feedback network I2；Operation transconductance amplifying circuit
After the in-phase output end VOUTP1 of I1 is connected with the in-phase input end VIP2 of capacitive feedback network I2, form the homophase of this amplifier
Output end VOUTP；The inverting input of the reversed-phase output VOUTN1 of operation transconductance amplifying circuit I1 and capacitive feedback network I2
After VIN2 is connected, form the reversed-phase output VOUTN of this amplifier；The in-phase clock input CLK of input pretreatment circuit I 0,
The in-phase clock input CLK of the in-phase clock input CLK and operation transconductance amplifying circuit I1 of capacitive feedback network I2 is connected
Afterwards, form the in-phase clock input CLK of this amplifier；The inversion clock input CLK_N of input pretreatment circuit I 0, electric capacity
The inversion clock input CLK_N of the inversion clock input CLK_N of feedback network I2 and capacitive feedback network I2 and computing across
Lead amplifying circuit I1 inversion clock input CLK_N be connected after, form the inversion clock input CLK_N of this amplifier；Defeated
The input voltage reference edge VREF_IN entering to pre-process circuit I 0 forms the input voltage reference edge VREF_IN of this amplifier.
In such scheme, described operation transconductance amplifying circuit I1 comprises 14 PMOS transistor PM10～PM24,12
Nmos pass transistor NM12～NM21,2 electric capacity C10～C11, and 2 resistance R10～R11；The grid end of PMOS transistor PM10
Form the homophase differential input end VIP1 of this operation transconductance amplifying circuit I1；The grid end of PMOS transistor PM11 formed this computing across
Lead the anti-phase differential input end VIN1 of amplifying circuit I1；The grid end of PMOS transistor PM13 forms this operation transconductance amplifying circuit I1
Homophase feedback input end VFBP；The inverting feedback that the grid end of PMOS transistor PM12 forms this operation transconductance amplifying circuit I1 is defeated
Enter to hold VFBN；The source of PMOS transistor PM10, the source of PMOS transistor PM11, the trap contact at PMOS transistor PM10 end
End, the trap contact jaw of PMOS transistor PM11 are connected with the drain terminal of PMOS transistor PM14；The source of PMOS transistor PM12,
The source of PMOS transistor PM13, the trap contact jaw of PMOS transistor PM12, the trap contact jaw of PMOS transistor PM13 and PMOS
The drain terminal of transistor PM15 is connected；The grid end of PMOS transistor PM14, the grid end of PMOS transistor PM15, PMOS transistor
After the grid end of PM20 is connected, form the input offset side of this operation transconductance amplifying circuit I1 with the grid end of PMOS transistor PM21
VBP1；After the grid end of PMOS transistor PM18 is connected with the grid end of PMOS transistor PM19, form this operation transconductance amplifying circuit
The input offset side VBP2 of I1；The grid end of PMOS transistor PM24, the grid end of PMOS transistor PM27, nmos pass transistor NM15
After grid end is connected, form the in-phase clock input CLK of this operation transconductance amplifying circuit I1 with the grid end of nmos pass transistor NM16；
The grid end of PMOS transistor PM25, the grid end of PMOS transistor PM26, the grid end of nmos pass transistor NM14 and nmos pass transistor
After the grid end of NM16 is connected, form the inversion clock input CLK_N of this operation transconductance amplifying circuit I1；PMOS transistor PM24
Source, the source of PMOS transistor PM26 is connected with the drain terminal of PMOS transistor PM18；The source of PMOS transistor PM25,
The source of PMOS transistor PM27 is connected with the drain terminal of PMOS transistor PM19；The drain terminal of PMOS transistor PM24, PMOS are brilliant
The drain terminal of body pipe PM25 is connected with the source of PMOS transistor PM16；The grid end of PMOS transistor PM16 and PMOS transistor
After the grid end of PM17 is connected, form the input offset side VPBC of this operation transconductance amplifying circuit I1；The leakage of PMOS transistor PM26
End, the drain terminal of PMOS transistor PM27 are connected with the source of PMOS transistor PM17；The source of PMOS transistor PM22, PMOS
The source of transistor PM23, the drain terminal of PMOS transistor PM20 are connected with the drain terminal of PMOS transistor PM21；PMOS transistor
The grid end of PM22, one end of resistance R10, the drain terminal of PMOS transistor PM16 are connected with the drain terminal of nmos pass transistor NM12；
The grid end of PMOS transistor PM23, the drain terminal of one end of resistance R11, the drain terminal of PMOS transistor PM17 and nmos pass transistor NM13
It is connected；After the drain terminal of PMOS transistor PM22, the drain terminal of nmos pass transistor NM20 are connected with one end of electric capacity C10, being formed should
The in-phase output end VOUTP1 of operation transconductance amplifying circuit I1；The drain terminal of PMOS transistor PM23, the leakage of nmos pass transistor NM21
After end, one end of electric capacity C11 are connected, form the reversed-phase output VOUTN1 of this operation transconductance amplifying circuit I1；Nmos pass transistor
After the grid end of NM18 is connected, form the common-mode feedback input of this operation transconductance amplifying circuit I1 with the grid end of nmos pass transistor NM19
End VCMFB1；The drain terminal of PMOS transistor PM10, the drain terminal of PMOS transistor PM12, the source of nmos pass transistor NM14, NMOS
The source of transistor NM15 is connected with the drain terminal of nmos pass transistor NM18；The drain terminal of PMOS transistor PM11, PMOS transistor
The drain terminal of PM13, the drain terminal phase of the source of nmos pass transistor NM16, the source of nmos pass transistor NM17 and nmos pass transistor NM19
Connect；The drain terminal of nmos pass transistor NM14, the drain terminal of nmos pass transistor NM16 are connected with the source of nmos pass transistor NM12；
The drain terminal of nmos pass transistor NM15, the drain terminal of nmos pass transistor NM17 are connected with the source of nmos pass transistor NM13；NMOS is brilliant
After the grid end of body pipe NM12 is connected, form the input biasing of this operation transconductance amplifying circuit I1 with the grid end of nmos pass transistor NM13
End VBNC；After the grid end of nmos pass transistor NM20 is connected with the grid end of nmos pass transistor NM21, forms this operation transconductance and amplify electricity
The common-mode feedback input VCMFB2 of road I1；The other end of resistance R10 is connected with the other end of electric capacity C10, and resistance R11's is another
The other end of one end electric capacity C11 is connected；The trap contact jaw of PMOS transistor PM15～PM23, PMOS transistor PM14～PM15
Source and the source of PMOS transistor PM20～PM21 meet power end VDD simultaneously；The trap of nmos pass transistor NM12～NM21 connects
The source earth terminal GND simultaneously of contravention and nmos pass transistor NM18～NM21.
In such scheme, described input pretreatment circuit I 0 comprises 4 PMOS transistor PM0～PM3,2 on-off circuits
SW0～SW1, and 2 electric capacity C0～C1；The input IN of on-off circuit SW0 forms the homophase that this input pre-processes circuit I 0
Input VIP0；The input IN of on-off circuit SW1 forms the inverting input VIN0 that this input pre-processes circuit I 0；Switch electricity
After the in-phase clock input CLK of the in-phase clock input CLK and on-off circuit SW1 of road SW0 is connected, form this input pretreatment
The in-phase clock input CLK of circuit I 0；The inversion clock input CLK_N's of on-off circuit SW0 and on-off circuit SW1 is anti-phase
After input end of clock CLK_N is connected, form the inversion clock input CLK_N that this input pre-processes circuit I 0；On-off circuit SW0
In-phase output end VOP, the inverting input VON of on-off circuit SW1 be connected with one end of electric capacity C0；On-off circuit SW1's is same
Phase output terminal VOP, the reversed-phase output VON of on-off circuit SW0 are connected with one end of electric capacity C1；The drain terminal of PM0 pipe, PM1 pipe
Source, the grid end of the grid end PM1 pipe of PM0 pipe link together；The drain terminal of PM3 pipe, the source of PM2 pipe, the grid end of PM3 pipe and
The grid end of PM2 pipe links together；After the source of PMOS transistor PM0 is connected with the source of PMOS transistor PM3, form this defeated
Enter to pre-process the input voltage reference edge VREF_IN of circuit I 0；The other end of electric capacity C0 is connected with the drain terminal of PMOS transistor PM1
Afterwards, form the in-phase output end VOUTP0 that this input pre-processes circuit I 0；The other end of electric capacity C1 and the leakage of PMOS transistor PM2
After end is connected, form the reversed-phase output VOUTN0 that this input pre-processes circuit I 0.
In such scheme, described capacitive feedback network I2 comprises 4 PMOS transistor PM40～PM43, and 4 electric capacity C20～
C23, and 2 on-off circuit SW30～SW31；The input IN of on-off circuit SW30 forms the same of this capacitive feedback network I2
Phase input VIP2；The input IN of on-off circuit SW31 forms the inverting input VIN2 of this capacitive feedback network I2；Switch
The in-phase output end VOP of circuit SW30, the reversed-phase output VON of on-off circuit SW31, the source of PMOS transistor PM40 and electricity
The one end holding C20 connects；The reversed-phase output VON of on-off circuit SW30 pipe, the in-phase output end VOP of on-off circuit SW31 pipe,
The source of PM42 pipe is connected with one end of electric capacity C21；The in-phase clock input CLK of on-off circuit SW30 and on-off circuit SW31
In-phase clock input CLK be connected after, form the in-phase clock input CLK of this capacitive feedback network I2；On-off circuit SW30
Inversion clock input CLK_N be connected with the inversion clock input CLK_N of on-off circuit SW31 after, form this capacitive feedback
The inversion clock input CLK_N of network I2；The drain terminal of PMOS transistor PM40, the source of PMOS transistor PM41, PMOS are brilliant
The grid end of body pipe PM40 is connected with the grid end of PMOS transistor PM41；The drain terminal of PMOS transistor PM42, PMOS transistor
The source of PM43, the grid end of PMOS transistor PM41 are connected with the grid end of PMOS transistor PM43；PMOS transistor PM41
After drain terminal, the other end of electric capacity C20 are connected, form the in-phase output end of this capacitive feedback network I2 with one end of electric capacity C22
VOUTP2；After the drain terminal of PMOS transistor PM43, the other end of electric capacity C21, one end of electric capacity C23 are connected, form this electric capacity anti-
The reversed-phase output VOUTN2 of feedback network I2；The other end of the other end of electric capacity C22 and electric capacity C23 is grounded simultaneously.
In such scheme, described on-off circuit comprises nmos pass transistor NM0 and NM1；The source of nmos pass transistor NM0 and
After the source of nmos pass transistor NM1 is connected, form the input IN of this on-off circuit；The substrate contact end of nmos pass transistor NM0
Connect low level with the substrate contact end of nmos pass transistor NM1 simultaneously；The grid end of nmos pass transistor NM0 forms the same of this on-off circuit
The grid end of phase clock input CLK, nmos pass transistor NM1 forms the inversion clock input CLK_N of this on-off circuit；NMOS is brilliant
The drain terminal of body pipe NM0 forms the in-phase output end VOP of this on-off circuit, and the drain terminal of nmos pass transistor NM1 forms this on-off circuit
Inverse output terminal VON.
Compared with prior art, the present invention can feed back electric current and its crystalline substance of transconductance amplifier branch road by scaled down
The breadth length ratio of body pipe, to reduce power consumption and the noise of current feedback instrument amplifier.It is also possible to reduce tradition
The value of feedback capacity in current feedback instrument amplifier.Because system gain is by the ratio of feedback capacity, and input across
The product of the mutual conductance and the ratio of mutual conductance of feedback mutual conductance branch road of leading branch road together decides on.Improve input mutual conductance branch road differential pair
After the ratio of mutual conductance of the mutual conductance of transistor and feedback mutual conductance branch road differential pair transistors, the ratio of feedback capacity can obtain phase
The reduction answered.So, realize the chip area required for feedback capacity just can be reduced it is possible to realize less chip
Area and cost.
Brief description
Fig. 1 is the theory diagram of low-power consumption low-noise current feedback-type instrument amplifier.
Fig. 2 is the schematic diagram of input pretreatment circuit.
Fig. 3 feeds back the schematic diagram of the OTA circuit of mutual conductance for Scaling.
Fig. 4 is the schematic diagram of capacitive feedback network.
Fig. 5 is the schematic diagram of on-off circuit.
Fig. 6 be improve before and after chopper amplifier the PNOISE simulation result figure that obtains of emulation.
Specific embodiment
A kind of low-power consumption low-noise current feedback-type instrument amplifier, as shown in figure 1, inclusion input pretreatment circuit I 0,
Operation transconductance amplifies (OTA) circuit and capacitive feedback network I2.The in-phase input end VIP0 of input pretreatment circuit I 0 is formed should
The in-phase input end VIP of amplifier, the inverting input VIN0 of input pretreatment circuit I 0 forms the anti-phase input of this amplifier
End VIN.Differential inphase output end VOUTP0 of input pretreatment circuit I 0 meets the homophase differential input end VIP1 of OTA circuit I 1.
The difference reversed-phase output VOUTN0 of input pretreatment circuit I 0 meets the anti-phase differential input end VIN1 of OTA circuit I 1.OTA circuit
The homophase feedback input end VFBP of I1 meets the in-phase output end VOUTP2 of capacitive feedback network I2.The inverting feedback of OTA circuit I 1
Input VFBN meets the reversed-phase output VOUTN2 of capacitive feedback network I2.The in-phase output end VOUTP1 of OTA circuit I 1 and electricity
After the in-phase input end VIP2 of appearance feedback network I2 is connected, form the in-phase output end VOUTP of this amplifier.OTA circuit I 1
After reversed-phase output VOUTN1 is connected with the inverting input VIN2 of capacitive feedback network I2, form the anti-phase output of this amplifier
End VOUTN.In-phase clock input CLK, the in-phase clock input CLK of capacitive feedback network I2 of input pretreatment circuit I 0
After being connected, form the in-phase clock input CLK of this amplifier with the in-phase clock input CLK of OTA circuit I 1.Input is pre- to be located
Inversion clock input CLK_N, the inversion clock input CLK_N of capacitive feedback network I2 of reason circuit I 0 and capacitive feedback net
After the inversion clock input CLK_N of network I2 is connected with the inversion clock input CLK_N of OTA circuit I 1, form this amplifier
Inversion clock input CLK_N.The input voltage reference edge VREF_IN of input pretreatment circuit I 0 forms the defeated of this amplifier
Enter Voltage Reference end VREF_IN.
Above-mentioned input pre-processes circuit I 0 as shown in Fig. 2 comprising 4 PMOS transistor PM0～PM3,2 on-off circuits
SW0～SW1, and 2 electric capacity C0～C1.The input IN of on-off circuit SW0 forms the homophase that this input pre-processes circuit I 0
Input VIP0.The input IN of on-off circuit SW1 forms the inverting input VIN0 that this input pre-processes circuit I 0.Switch electricity
After the in-phase clock input CLK of the in-phase clock input CLK and on-off circuit SW1 of road SW0 is connected, form this input pretreatment
The in-phase clock input CLK of circuit I 0.The inversion clock input CLK_N's of on-off circuit SW0 and on-off circuit SW1 is anti-phase
After input end of clock CLK_N is connected, form the inversion clock input CLK_N that this input pre-processes circuit I 0.On-off circuit SW0
In-phase output end VOP, the inverting input VON of on-off circuit SW1 be connected with one end of electric capacity C0.On-off circuit SW1's is same
Phase output terminal VOP, the reversed-phase output VON of on-off circuit SW0 are connected with one end of electric capacity C1.The drain terminal of PM0 pipe, PM1 pipe
Source, the grid end of the grid end PM1 pipe of PM0 pipe link together.The drain terminal of PM3 pipe, the source of PM2 pipe, the grid end of PM3 pipe and
The grid end of PM2 pipe links together.After the source of PMOS transistor PM0 is connected with the source of PMOS transistor PM3, form this defeated
Enter to pre-process the input voltage reference edge VREF_IN of circuit I 0.The other end of electric capacity C0 is connected with the drain terminal of PMOS transistor PM1
Afterwards, form the in-phase output end VOUTP0 that this input pre-processes circuit I 0.The other end of electric capacity C1 and the leakage of PMOS transistor PM2
After end is connected, form the reversed-phase output VOUTN0 that this input pre-processes circuit I 0.Input pretreatment circuit I 0 comprises input and cuts
Ripple, every straight and biasing function.Input pretreatment circuit I 0 can reduce DC maladjustment in bioelectrical signals, prevents amplifier from exporting
Saturation.Meanwhile, input pretreatment circuit I 0 is also a high-pass filter in itself, can suppress under extremely low frequency to a certain extent
1/f noise, the input for OTA for its bias capability provides suitable DC offset voltage.
Above-mentioned OTA circuit I 1 as shown in figure 3, comprising 14 PMOS transistor PM10～PM24,12 nmos pass transistors
NM12～NM21,2 electric capacity C10～C11, and 2 resistance R10～R11.Wherein PMOS transistor PM10, PM11 and PM14
Constitute input mutual conductance branch road.PMOS transistor PM12, PM13 and PM15 constitute feedback mutual conductance branch road.
In the road of input mutual conductance, the grid end of PMOS transistor PM10 forms the homophase differential input end of this OTA circuit I 1
VIP1.The grid end of PMOS transistor PM11 forms the anti-phase differential input end VIN1 of this OTA circuit I 1.PMOS transistor PM10
Source, the source of PMOS transistor PM11, the trap contact jaw at PMOS transistor PM10 end, the trap contact jaw of PMOS transistor PM11
It is connected with the drain terminal of PMOS transistor PM14.
In feedback mutual conductance branch road, the grid end of PMOS transistor PM13 forms the homophase feedback input end of this OTA circuit I 1
VFBP.The grid end of PMOS transistor PM12 forms the inverting feedback input VFBN of this OTA circuit I 1.PMOS transistor PM12
Source, the source of PMOS transistor PM13, the trap contact jaw of PMOS transistor PM12, the trap contact jaw of PMOS transistor PM13 and
The drain terminal of PMOS transistor PM15 is connected.
In OTA first order output branch road, the grid end of PMOS transistor PM14, the grid end of PMOS transistor PM15, PMOS are brilliant
After the grid end of body pipe PM20 is connected, form the input offset side VBP1 of this OTA circuit I 1 with the grid end of PMOS transistor PM21.
After the grid end of PMOS transistor PM18 is connected, form the input offset side of this OTA circuit I 1 with the grid end of PMOS transistor PM19
VBP2.The grid end of PMOS transistor PM24, the grid end of PMOS transistor PM27, the grid end of nmos pass transistor NM15 and NMOS crystal
After the grid end of pipe NM16 is connected, form the in-phase clock input CLK of this OTA circuit I 1.The grid end of PMOS transistor PM25,
After the grid end of PMOS transistor PM26, the grid end of nmos pass transistor NM14 are connected with the grid end of nmos pass transistor NM16, being formed should
The inversion clock input CLK_N of OTA circuit I 1.The source of PMOS transistor PM24, the source of PMOS transistor PM26 and
The drain terminal of PMOS transistor PM18 is connected.The source of PMOS transistor PM25, the source of PMOS transistor PM27 and PMOS are brilliant
The drain terminal of body pipe PM19 is connected.The drain terminal of PMOS transistor PM24, the drain terminal of PMOS transistor PM25 and PMOS transistor
The source of PM16 is connected.After the grid end of PMOS transistor PM16 is connected with the grid end of PMOS transistor PM17, form this OTA electricity
The input offset side VPBC of road I1.The drain terminal of PMOS transistor PM26, the drain terminal of PMOS transistor PM27 and PMOS transistor
The source of PM17 is connected.The drain terminal of PMOS transistor PM10, the drain terminal of PMOS transistor PM12, the source of nmos pass transistor NM14
End, the source of nmos pass transistor NM15 are connected with the drain terminal of nmos pass transistor NM18.The drain terminal of PMOS transistor PM11, PMOS
The drain terminal of transistor PM13, the source of nmos pass transistor NM16, the source of nmos pass transistor NM17 and nmos pass transistor NM19's
Drain terminal is connected.The source phase of the drain terminal of nmos pass transistor NM14, the drain terminal of nmos pass transistor NM16 and nmos pass transistor NM12
Connect.The drain terminal of nmos pass transistor NM15, the drain terminal of nmos pass transistor NM17 are connected with the source of nmos pass transistor NM13.
After the grid end of nmos pass transistor NM12 is connected, form the input offset side of this OTA circuit I 1 with the grid end of nmos pass transistor NM13
VBNC.
In OTA circuit second stage circuit, the source of PMOS transistor PM22, the source of PMOS transistor PM23, PMOS are brilliant
The drain terminal of body pipe PM20 is connected with the drain terminal of PMOS transistor PM21.The grid end of PMOS transistor PM22, the one of resistance R10
End, the drain terminal of PMOS transistor PM16 are connected with the drain terminal of nmos pass transistor NM12.The grid end of PMOS transistor PM23, resistance
One end of R11, the drain terminal of PMOS transistor PM17 are connected with the drain terminal of nmos pass transistor NM13.The leakage of PMOS transistor PM22
After end, the drain terminal of nmos pass transistor NM20 are connected with one end of electric capacity C10, form the in-phase output end of this OTA circuit I 1
VOUTP1.After the drain terminal of PMOS transistor PM23, the drain terminal of nmos pass transistor NM21, one end of electric capacity C11 are connected, being formed should
The reversed-phase output VOUTN1 of OTA circuit I 1.After the grid end of nmos pass transistor NM20 is connected with the grid end of nmos pass transistor NM21,
Form the common-mode feedback input VCMFB2 of this OTA circuit I 1.The other end of resistance R10 is connected with the other end of electric capacity C10,
The other end of the other end electric capacity C11 of resistance R11 is connected.
The trap contact jaw of PMOS transistor PM15～PM23, the source of PMOS transistor PM14～PM15 and PMOS transistor
The source of PM20～PM21 meets power end VDD simultaneously.The trap contact jaw of nmos pass transistor NM12～NM21, nmos pass transistor NM18
The source of～NM21 earth terminal GND simultaneously.
The input difference of current feedback instrument amplifier is to the mutual conductance of transistor and feedback differential to transistor transconductance
Ratio is 1：1, the capacitance ratio of corresponding feedback network is particularly big.For example, if the gain realizing 40dB needs to realize
100：The ratio of 1 feedback capacity.Due to the restriction of least unit electric capacity, such design not only taken substantial amounts of chip area but also
The capacitance mismatch making feedback network can be larger.Therefore, the present invention, in the case of transistor length identical, inputs mutual conductance difference
Transistor is feedback mutual conductance difference transistor to the breadth length ratio of i.e. PMOS transistor PM10 and PMOS transistor PM11 to i.e. PMOS
N times of the breadth length ratio of transistor PM12 and PM13, and biasing transistor is PMOS crystal to i.e. PMOS transistor PM14 breadth length ratio
N times of the breadth length ratio of pipe PM15.Gain required by concrete application system for the N value, technological parameter and noise and power consumption requirements
Determine, above-mentioned N value should be greater than 1, and the value of N should not be too big simultaneously.In engineer applied, if N value is excessive, the presence of process deviation
Can make the gain of circuit and design load that larger deviation occurs, usual N value selects between 1～10.By scaled down
The feedback bias current of mutual conductance and the breadth length ratio of transistor, to reduce its noise and power consumption.Using improved current feedback instrument
Table amplifier, can realize lower circuit noise and power consumption in the case of realizing identical gain, also reduce circuit simultaneously
In feedback capacity device value, save chip area and cost.
Above-mentioned capacitive feedback network I2 as shown in figure 4, comprising 4 PMOS transistor PM40～PM43,4 electric capacity C20～
C23, and 2 on-off circuit SW30～SW31.The input IN of on-off circuit SW30 forms the same of this capacitive feedback network I2
Phase input VIP2.The input IN of on-off circuit SW31 forms the inverting input VIN2 of this capacitive feedback network I2.Switch
The in-phase output end VOP of circuit SW30, the reversed-phase output VON of on-off circuit SW31, the source of PMOS transistor PM40 and electricity
The one end holding C20 connects.The reversed-phase output VON of on-off circuit SW30 pipe, the in-phase output end VOP of on-off circuit SW31 pipe,
The source of PM42 pipe is connected with one end of electric capacity C21.The in-phase clock input CLK of on-off circuit SW30 and on-off circuit SW31
In-phase clock input CLK be connected after, form the in-phase clock input CLK of this capacitive feedback network I2.On-off circuit SW30
Inversion clock input CLK_N be connected with the inversion clock input CLK_N of on-off circuit SW31 after, form this capacitive feedback
The inversion clock input CLK_N of network I2.The drain terminal of PMOS transistor PM40, the source of PMOS transistor PM41, PMOS are brilliant
The grid end of body pipe PM40 is connected with the grid end of PMOS transistor PM41.The drain terminal of PMOS transistor PM42, PMOS transistor
The source of PM43, the grid end of PMOS transistor PM41 are connected with the grid end of PMOS transistor PM43.PMOS transistor PM41
After drain terminal, the other end of electric capacity C20 are connected, form the in-phase output end of this capacitive feedback network I2 with one end of electric capacity C22
VOUTP2.After the drain terminal of PMOS transistor PM43, the other end of electric capacity C21, one end of electric capacity C23 are connected, form this electric capacity anti-
The reversed-phase output VOUTN2 of feedback network I2.The other end of the other end of electric capacity C22 and electric capacity C23 is grounded simultaneously.
On-off circuit used in above-mentioned input pretreatment circuit I 0 and capacitive feedback network I2 is as shown in figure 5, comprise
Nmos pass transistor NM0 and NM1.After the source of nmos pass transistor NM0 is connected with the source of nmos pass transistor NM1, form this switch
The input IN of circuit.The substrate contact end of nmos pass transistor NM0 and the substrate contact end of nmos pass transistor NM1 connect low electricity simultaneously
Flat.The grid end of nmos pass transistor NM0 forms the in-phase clock input CLK of this on-off circuit, the grid end shape of nmos pass transistor NM1
Become the inversion clock input CLK_N of this on-off circuit.The drain terminal of nmos pass transistor NM0 forms the homophase output of this on-off circuit
End VOP, the drain terminal of nmos pass transistor NM1 forms the inverse output terminal VON of this on-off circuit.Wave chopping technology application (SW0 and
SW1 is chopping switch) flicker (1/f) noise can be greatly lowered, and 1/f noise is main in low-frequency signal processing circuit
Noise source.The rejection ability to common mode offset voltage for the circuit can be greatly improved using current feedback instrument amplifier,
This is extremely important for low frequency biomedicine signals.
The input mutual conductance branch road of current feedback instrument amplifier, feedback mutual conductance branch road and cascade branch road use equal
Bias current.
Wherein, gmp10For the mutual conductance of transistor MP10, gmp12For the mutual conductance of transistor MP12, gmp18For transistor MP18's
Mutual conductance, gmn18Mutual conductance for transistor MN18.
From formula 1：The input mutual conductance of current feedback instrument amplifier circuit, feedback mutual conductance and cascode structure
In the PMOS transistor of nearly power supply and the nmos pass transistor of near-earth in cascode structure be operational amplifier equivalent input noise
Main contributor.(mutual conductance branch road differential pair crystal is fed back by scaled down when mutual conductance is fed back using scaled down
The electric current of pipe simultaneously reduces the mode of its transistor breadth length ratio simultaneously and realizes), current mirror crystal in cascode structure can be reduced
The electric current of pipe and mutual conductance.After scaled down feedback mutual conductance, output noise is because mutual conductance gmp10、gmp12And gmp18Reduction and drop
Low, 1/f noise does not affect because the application of wave chopping technology is shifted to outside target bandwidth substantially on output noise.Therefore this
The improvement of sample can improve conventional current and feed back the larger deficiency of the power consumption of instrument amplifier, noise.Meanwhile, from formula 2,
In the case of fixing gain, feedback mutual conductance is that the reduction of the mutual conductance of transistor MP12 makes electric capacity C in feedback control loop22Absolute
It is worth to reduce, save chip area and cost.
Through the design of 0.18 μm of CMOS technology practical circuit simulation result as shown in Figure 6.Circuit before in figure improvement
Equivalent input noise in the case of 100Hz is 88nV/sqrt (Hz), and the circuit after improvement is equivalent defeated in the case of 100Hz
Entering noise is 62nV/sqrt (Hz), adjusts equivalent input noise according to noise power and reduces about 50%.The first order of amplifier
Reduce power consumption about 27%.Case verification shows：Improved circuit can effectively reduce noise and the power consumption of circuit.
It is emphasized that：The above is only presently preferred embodiments of the present invention, not any shape is made to patent of the present invention
Restriction in formula, any simple modification that every technical spirit according to patent of the present invention is made to above example, equivalent becomes
Change and modify, all still fall within the range of art solutions of the present invention.
Claims (7)
1. a kind of low-power consumption low-noise current feedback-type instrument amplifier, amplifies electricity by input pretreatment circuit I 0, operation transconductance
Road I1 and capacitive feedback network I2 composition；It is characterized in that：
Described operation transconductance amplifying circuit I1 includes inputting mutual conductance branch road and feedback mutual conductance branch road；It is brilliant that route PMOS is propped up in input mutual conductance
Body pipe PM10, PMOS transistor PM11 and PMOS transistor PM14 are constituted；Route PMOS transistor PM12, PMOS is propped up in feedback mutual conductance
Transistor PM13 and PMOS transistor PM15 are constituted；
In the case of transistor length identical, input mutual conductance difference transistor is to i.e. PMOS transistor PM10 and PMOS transistor
The breadth length ratio of PM11 is N times to i.e. PMOS transistor PM12 and the breadth length ratio of PM13 of feedback mutual conductance difference transistor, and biasing
Transistor is N times of the breadth length ratio of PMOS transistor PM15 to i.e. PMOS transistor PM14 breadth length ratio；Above-mentioned N is more than 1.
2. a kind of low-power consumption low-noise current feedback-type instrument amplifier according to claim 1 it is characterised in that：Described
The span of N is between 1～10.
3. a kind of low-power consumption low-noise current feedback-type instrument amplifier according to claim 1 and 2 it is characterised in that：
The in-phase input end VIP0 of input pretreatment circuit I 0 forms the in-phase input end VIP of this amplifier, input pretreatment circuit I 0
Inverting input VIN0 form the inverting input VIN of this amplifier；The differential inphase output end of input pretreatment circuit I 0
VOUTP0 meets the homophase differential input end VIP1 of operation transconductance amplifying circuit I1；The difference anti-phase output of input pretreatment circuit I 0
End VOUTN0 meets the anti-phase differential input end VIN1 of operation transconductance amplifying circuit I1；The homophase feedback of operation transconductance amplifying circuit I1
Input VFBP meets the in-phase output end VOUTP2 of capacitive feedback network I2；The inverting feedback input of operation transconductance amplifying circuit I1
End VFBN meets the reversed-phase output VOUTN2 of capacitive feedback network I2；The in-phase output end VOUTP1 of operation transconductance amplifying circuit I1
After being connected, form the in-phase output end VOUTP of this amplifier with the in-phase input end VIP2 of capacitive feedback network I2；Operation transconductance
After the reversed-phase output VOUTN1 of amplifying circuit I1 is connected with the inverting input VIN2 of capacitive feedback network I2, form this amplification
The reversed-phase output VOUTN of device；The in-phase clock input CLK of input pretreatment circuit I 0, the homophase of capacitive feedback network I2
After input end of clock CLK is connected with the in-phase clock input CLK of operation transconductance amplifying circuit I1, form the homophase of this amplifier
Input end of clock CLK；The inversion clock input CLK_N of input pretreatment circuit I 0, the inversion clock of capacitive feedback network I2
The inversion clock input CLK_N of input CLK_N and capacitive feedback network I2 and operation transconductance amplifying circuit I1 anti-phase when
After clock input CLK_N is connected, form the inversion clock input CLK_N of this amplifier；The input of input pretreatment circuit I 0
Voltage Reference end VREF_IN forms the input voltage reference edge VREF_IN of this amplifier.
4. a kind of low-power consumption low-noise current feedback-type instrument amplifier according to claim 1 it is characterised in that：Described
Operation transconductance amplifying circuit I1 comprises 14 PMOS transistor PM10～PM24,12 nmos pass transistor NM12～NM21,2 electricity
Hold C10～C11, and 2 resistance R10～R11；The grid end of PMOS transistor PM10 forms this operation transconductance amplifying circuit I1's
Homophase differential input end VIP1；The grid end of PMOS transistor PM11 forms the anti-phase Differential Input of this operation transconductance amplifying circuit I1
End VIN1；The grid end of PMOS transistor PM13 forms the homophase feedback input end VFBP of this operation transconductance amplifying circuit I1；PMOS
The grid end of transistor PM12 forms the inverting feedback input VFBN of this operation transconductance amplifying circuit I1；PMOS transistor PM10
Source, the source of PMOS transistor PM11, the trap contact jaw at PMOS transistor PM10 end, the trap contact jaw of PMOS transistor PM11
It is connected with the drain terminal of PMOS transistor PM14；The source of PMOS transistor PM12, the source of PMOS transistor PM13, PMOS are brilliant
The trap contact jaw of body pipe PM12, the trap contact jaw of PMOS transistor PM13 are connected with the drain terminal of PMOS transistor PM15；PMOS
The grid end of transistor PM14, the grid end of PMOS transistor PM15, the grid end of PMOS transistor PM20 and PMOS transistor PM21
After grid end is connected, form the input offset side VBP1 of this operation transconductance amplifying circuit I1；The grid end of PMOS transistor PM18 and
After the grid end of PMOS transistor PM19 is connected, form the input offset side VBP2 of this operation transconductance amplifying circuit I1；PMOS crystal
The grid end of pipe PM24, the grid end of the grid end of PMOS transistor PM27, the grid end of nmos pass transistor NM15 and nmos pass transistor NM16
After being connected, form the in-phase clock input CLK of this operation transconductance amplifying circuit I1；The grid end of PMOS transistor PM25, PMOS
After the grid end of transistor PM26, the grid end of nmos pass transistor NM14 are connected with the grid end of nmos pass transistor NM16, form this computing
The inversion clock input CLK_N of mutual conductance amplifying circuit I1；The source of PMOS transistor PM24, the source of PMOS transistor PM26
It is connected with the drain terminal of PMOS transistor PM18；The source of PMOS transistor PM25, the source of PMOS transistor PM27 and PMOS
The drain terminal of transistor PM19 is connected；The drain terminal of PMOS transistor PM24, the drain terminal of PMOS transistor PM25 and PMOS transistor
The source of PM16 is connected；After the grid end of PMOS transistor PM16 is connected with the grid end of PMOS transistor PM17, form this computing
The input offset side VPBC of mutual conductance amplifying circuit I1；The drain terminal of PMOS transistor PM26, the drain terminal of PMOS transistor PM27 and
The source of PMOS transistor PM17 is connected；The source of PMOS transistor PM22, the source of PMOS transistor PM23, PMOS crystal
The drain terminal of pipe PM20 is connected with the drain terminal of PMOS transistor PM21；The grid end of PMOS transistor PM22, one end of resistance R10,
The drain terminal of PMOS transistor PM16 is connected with the drain terminal of nmos pass transistor NM12；The grid end of PMOS transistor PM23, resistance R11
One end, the drain terminal of PMOS transistor PM17 is connected with the drain terminal of nmos pass transistor NM13；The drain terminal of PMOS transistor PM22,
After the drain terminal of nmos pass transistor NM20 is connected, form the homophase output of this operation transconductance amplifying circuit I1 with one end of electric capacity C10
End VOUTP1；After the drain terminal of PMOS transistor PM23, the drain terminal of nmos pass transistor NM21, one end of electric capacity C11 are connected, being formed should
The reversed-phase output VOUTN1 of operation transconductance amplifying circuit I1；The grid end of nmos pass transistor NM18 and the grid of nmos pass transistor NM19
After end is connected, form the common-mode feedback input VCMFB1 of this operation transconductance amplifying circuit I1；The drain terminal of PMOS transistor PM10,
The drain terminal of PMOS transistor PM12, the source of nmos pass transistor NM14, the source of nmos pass transistor NM15 and nmos pass transistor
The drain terminal of NM18 is connected；The drain terminal of PMOS transistor PM11, the drain terminal of PMOS transistor PM13, the source of nmos pass transistor NM16
End, the source of nmos pass transistor NM17 are connected with the drain terminal of nmos pass transistor NM19；The drain terminal of nmos pass transistor NM14, NMOS
The drain terminal of transistor NM16 is connected with the source of nmos pass transistor NM12；The drain terminal of nmos pass transistor NM15, nmos pass transistor
The drain terminal of NM17 is connected with the source of nmos pass transistor NM13；The grid end of nmos pass transistor NM12 and nmos pass transistor NM13's
After grid end is connected, form the input offset side VBNC of this operation transconductance amplifying circuit I1；The grid end of nmos pass transistor NM20 and
After the grid end of nmos pass transistor NM21 is connected, form the common-mode feedback input VCMFB2 of this operation transconductance amplifying circuit I1；Electricity
The other end of resistance R10 is connected with the other end of electric capacity C10, and the other end of the other end electric capacity C11 of resistance R11 is connected；
The trap contact jaw of PMOS transistor PM15～PM23, the source of PMOS transistor PM14～PM15 and PMOS transistor PM20～
The source of PM21 meets power end VDD simultaneously；The trap contact jaw of nmos pass transistor NM12～NM21 and nmos pass transistor NM18～
The source of NM21 earth terminal GND simultaneously.
5. a kind of low-power consumption low-noise current feedback-type instrument amplifier according to claim 1 it is characterised in that：Described
Input pretreatment circuit I 0 comprises 4 PMOS transistor PM0～PM3,2 on-off circuit SW0～SW1, and 2 electric capacity C0～
C1；The input IN of on-off circuit SW0 forms the in-phase input end VIP0 that this input pre-processes circuit I 0；On-off circuit SW1's
Input IN forms the inverting input VIN0 that this input pre-processes circuit I 0；The in-phase clock input CLK of on-off circuit SW0
After being connected with the in-phase clock input CLK of on-off circuit SW1, form the in-phase clock input that this input pre-processes circuit I 0
CLK；After the inversion clock input CLK_N of the inversion clock input CLK_N and on-off circuit SW1 of on-off circuit SW0 is connected,
Form the inversion clock input CLK_N that this input pre-processes circuit I 0；The in-phase output end VOP of on-off circuit SW0, switch electricity
The inverting input VON of road SW1 is connected with one end of electric capacity C0；The in-phase output end VOP of on-off circuit SW1, on-off circuit SW0
Reversed-phase output VON be connected with one end of electric capacity C1；The drain terminal of PM0 pipe, the source of PM1 pipe, the grid end PM1 pipe of PM0 pipe
Grid end links together；The drain terminal of PM3 pipe, the grid end of the source of PM2 pipe, the grid end of PM3 pipe and PM2 pipe link together；
After the source of PMOS transistor PM0 is connected with the source of PMOS transistor PM3, form the input electricity that this input pre-processes circuit I 0
Pressure reference edge VREF_IN；After the other end of electric capacity C0 is connected with the drain terminal of PMOS transistor PM1, form this input pretreatment electricity
The in-phase output end VOUTP0 of road I0；After the other end of electric capacity C1 is connected with the drain terminal of PMOS transistor PM2, form this input pre-
The reversed-phase output VOUTN0 of process circuit I0.
6. a kind of low-power consumption low-noise current feedback-type instrument amplifier according to claim 1 it is characterised in that：Described
Capacitive feedback network I2 comprises 4 PMOS transistor PM40～PM43,4 electric capacity C20～C23, and 2 on-off circuit SW30
～SW31；The input IN of on-off circuit SW30 forms the in-phase input end VIP2 of this capacitive feedback network I2；On-off circuit
The input IN of SW31 forms the inverting input VIN2 of this capacitive feedback network I2；The in-phase output end of on-off circuit SW30
VOP, the reversed-phase output VON of on-off circuit SW31, the source of PMOS transistor PM40 are connected with one end of electric capacity C20；Switch
The reversed-phase output VON of circuit SW30 pipe, the source of in-phase output end VOP, PM42 pipe of on-off circuit SW31 pipe and electric capacity C21
One end connect；The in-phase clock input CLK of the in-phase clock input CLK and on-off circuit SW31 of on-off circuit SW30 is connected
Afterwards, form the in-phase clock input CLK of this capacitive feedback network I2；The inversion clock input CLK_N of on-off circuit SW30
After being connected, form the inversion clock input of this capacitive feedback network I2 with the inversion clock input CLK_N of on-off circuit SW31
End CLK_N；The drain terminal of PMOS transistor PM40, the source of PMOS transistor PM41, the grid end of PMOS transistor PM40 and PMOS
The grid end of transistor PM41 is connected；The drain terminal of PMOS transistor PM42, the source of PMOS transistor PM43, PMOS transistor
The grid end of PM41 is connected with the grid end of PMOS transistor PM43；The drain terminal of PMOS transistor PM41, the other end of electric capacity C20 and
After one end of electric capacity C22 is connected, form the in-phase output end VOUTP2 of this capacitive feedback network I2；The leakage of PMOS transistor PM43
After end, one end of the other end of electric capacity C21, electric capacity C23 are connected, form the reversed-phase output of this capacitive feedback network I2
VOUTN2；The other end of the other end of electric capacity C22 and electric capacity C23 is grounded simultaneously.
7. a kind of low-power consumption low-noise current feedback-type instrument amplifier according to claim 5 or 6 it is characterised in that：
Described on-off circuit comprises nmos pass transistor NM0 and NM1；The source phase of the source of nmos pass transistor NM0 and nmos pass transistor NM1
Lian Hou, forms the input IN of this on-off circuit；The substrate contact end of nmos pass transistor NM0 and the substrate of nmos pass transistor NM1
Contact jaw connects low level simultaneously；The grid end of nmos pass transistor NM0 forms the in-phase clock input CLK, NMOS of this on-off circuit
The grid end of transistor NM1 forms the inversion clock input CLK_N of this on-off circuit；The drain terminal of nmos pass transistor NM0 is formed should
The drain terminal of the in-phase output end VOP of on-off circuit, nmos pass transistor NM1 forms the inverse output terminal VON of this on-off circuit.
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