CN106409213B - A kind of shifting deposit unit, gate driving circuit and display device - Google Patents
A kind of shifting deposit unit, gate driving circuit and display device Download PDFInfo
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- CN106409213B CN106409213B CN201611168533.6A CN201611168533A CN106409213B CN 106409213 B CN106409213 B CN 106409213B CN 201611168533 A CN201611168533 A CN 201611168533A CN 106409213 B CN106409213 B CN 106409213B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of shifting deposit unit, gate driving circuit and display devices, applied to gate driving circuit, comprising: input module, pull-up node, pull-up control module, the first pull-down node, the first pull-down control module, the first drop-down generation module, the second pull-down node, the second pull-down control module, the second drop-down generation module, scanning output module, scanning output end, cascaded-output module, cascaded-output end and capacitor；Wherein, by the mutual cooperation between modules, so that scanning output end exports scanning signal to grid line connected to it, meanwhile, so that cascaded-output end outputs signal to the superior and the subordinate's shifting deposit unit connected to it.Shifting deposit unit port connected to the gate line and the port connecting with the superior and the subordinate shifting deposit units are distinguished, i.e., using scanning output end as the port of connection grid line, and using cascaded-output end as the port of connection the superior and the subordinate's shifting deposit unit, meet the multifarious design of gate driving circuit.
Description
Technical field
The present invention relates to field of display technology, more specifically, are related to a kind of shifting deposit unit, gate driving circuit
And display device.
Background technique
With the development of electronic technology, display device has been widely used in each row field and various electronic products, at
A part indispensable with work for people's lives, such as TV, mobile phone, computer, personal digital assistant.Existing display dress
In setting, display device includes gate driving circuit, and gate driving circuit is mainly used for scanning multistage grid line, to pass through scanning
Grid line and the pixel array being electrically connected with grid line is scanned, and then cooperate All other routes structure and carry out the aobvious of picture
Show.Since people are to the multifarious demand of gate driving circuit, gate driving circuit is designed to developer now
One of main research tendency.
Summary of the invention
In view of this, displacement is posted the present invention provides a kind of shifting deposit unit, gate driving circuit and display device
Memory cell port connected to the gate line and the port connecting with the superior and the subordinate shifting deposit units are distinguished, that is, by scanning output end
As the port of connection grid line, and using cascaded-output end as the port of connection the superior and the subordinate's shifting deposit unit, meet grid
The multifarious design of driving circuit.
To achieve the above object, technical solution provided by the invention is as follows:
A kind of shifting deposit unit is applied to gate driving circuit, comprising: input module, pull-up node, pull-up control mould
Block, the first pull-down node, the first pull-down control module, the first drop-down generation module, the second pull-down node, the second drop-down control mould
Block, the second drop-down generation module, scanning output module, scanning output end, cascaded-output module, cascaded-output end and capacitor；
Wherein, the input module in response to the first control terminal current potential and control first voltage end and the pull-up node
On-state, and, in response to the second control terminal current potential and control the connection shape at second voltage end Yu the pull-up node
State, wherein the output level polarity at the first voltage end and the second voltage end is opposite；
The pull-up control module in response to the pull-up node current potential and control tertiary voltage end respectively with described the
The on-state of one pull-down node and second pull-down node；
First pull-down control module in response to first pull-down node current potential and control the 4th voltage end
With the on-state of the scanning output end, and, control the tertiary voltage end respectively with the pull-up node and the grade
Join the on-state of output end, wherein the tertiary voltage end is identical with the 4th voltage end output level, and the third
Voltage end output voltage is lower than the 4th voltage end output voltage；
It is described first drop-down generation module in response to the first signal end current potential and control the tertiary voltage end with it is described
The on-state of first pull-down node, and, in response to second signal end current potential and control the second signal end with it is described
The on-state of first pull-down node, wherein the output signal at first signal end and the second signal end is the mutual added time
Clock signal, and when the pull-up control module controls the tertiary voltage end and first pull-down node is connected, described the
The current potential of one pull-down node is the output current potential at the tertiary voltage end；
Second pull-down control module in response to second pull-down node current potential and control the 4th voltage end
With the on-state of the scanning output end, and, control the tertiary voltage end respectively with the pull-up node and the grade
Join the on-state of output end；
It is described second drop-down generation module in response to the second signal end current potential and control the tertiary voltage end with
The on-state of second pull-down node, and, in response to first signal end current potential and control first signal
The on-state at end and second pull-down node, wherein control the tertiary voltage end and institute in the pull-up control module
When stating the connection of the second pull-down node, the current potential of second pull-down node is the current potential at the tertiary voltage end；
It is described scanning output module in response to the pull-up node current potential and control clock signal terminal and scanning output end
On-state；
The cascaded-output module in response to the pull-up node current potential and control clock signal terminal and cascaded-output end
On-state；
And the capacitor is used for the ground of the scanning output end to the pull-up node.
Optionally, the input module includes: the first transistor and second transistor；
Wherein, the grid of the first transistor is connected to first control terminal, the first end of the first transistor
It is connected to the first voltage end, the second end of the first transistor is connected to the pull-up node；The second transistor
Grid be connected to second control terminal, the first end of the second transistor is connected to the second voltage end, described
The second end of two-transistor is connected to the pull-up node.
Optionally, the pull-up control module includes: third transistor and the 4th transistor；
Wherein, the grid of the third transistor and the 4th transistor is connected to the pull-up node, and the third is brilliant
The first end of body pipe and the 4th transistor is connected to the tertiary voltage end, and the second end of the third transistor is connected to institute
The first pull-down node is stated, the second end of the 4th transistor is connected to second pull-down node.
Optionally, first pull-down control module includes: the 5th transistor, the 6th transistor and the 7th transistor；
Wherein, the grid of the 5th transistor, the 6th transistor and the 7th transistor is connected to first drop-down
Node, the first end of the 5th transistor are connected to the 4th voltage end, and the second end of the 5th transistor is connected to
The scanning output end, the first end of the 6th transistor are connected to the tertiary voltage end, and the of the 6th transistor
Two ends are connected to the pull-up node, and the first end of the 7th transistor is connected to the tertiary voltage end, and the described 7th is brilliant
The second end of body pipe is connected to the cascaded-output end.
Optionally, the first drop-down generation module includes: the 8th transistor and the 9th transistor；
Wherein, the grid of the 8th transistor is connected to first signal end, the first end of the 8th transistor
It is connected to the tertiary voltage end, the second end of the 8th transistor is connected to first pull-down node, and the described 9th is brilliant
The grid of body pipe is connected to the second signal end, and the first end of the 9th transistor is connected to the second signal end, institute
The second end for stating the 9th transistor is connected to first pull-down node.
Optionally, second pull-down control module includes: the tenth transistor, the 11st transistor and the 12nd crystal
Pipe；
Wherein, the grid of the tenth transistor, the 11st transistor and the tenth two-transistor is connected to described second
Pull-down node, the first end of the tenth transistor are connected to the 4th voltage end, and the second end of the tenth transistor connects
It is connected to the scanning output end, the first end of the 11st transistor is connected to the tertiary voltage end, and the described 11st is brilliant
The second end of body pipe is connected to the pull-up node, and the first end of the tenth two-transistor is connected to the tertiary voltage end,
The second end of tenth two-transistor is connected to the cascaded-output end.
Optionally, the second drop-down generation module includes: the 13rd transistor and the 14th transistor；
Wherein, the grid of the 13rd transistor is connected to the second signal end, and the of the 13rd transistor
One end is connected to the tertiary voltage end, and the second end of the 13rd transistor is connected to second pull-down node, described
The grid of 14th transistor is connected to first signal end, and the first end of the 14th transistor is connected to described first
The second end of signal end, the 14th transistor is connected to second pull-down node.
Optionally, the scanning output module includes: the 15th transistor, and the grid of the 15th transistor is connected to
The pull-up node, the first end of the 15th transistor are connected to the clock signal terminal, the 15th transistor
Second end is connected to the scanning output end.
Optionally, the cascaded-output module includes: the 16th transistor, and the grid of the 16th transistor is connected to
The pull-up node, the first end of the 16th transistor are connected to the clock signal terminal, the 16th transistor
Second end is connected to the cascaded-output end.
Optionally, first signal end and when the level at second signal end identical as the level at the tertiary voltage end,
First signal end and second signal end output voltage are identical as tertiary voltage end output voltage.
Optionally, when the level of the clock signal terminal is identical as the level of the 4th voltage end, the clock signal
Hold output voltage identical as the 4th voltage end output voltage.
Optionally, when the gate driving circuit is scanned along first direction, first control terminal exports open signal；
And when the gate driving circuit scans in a second direction, second control terminal exports open signal,
In, the first direction and second direction are opposite.
Optionally, the output signal at first signal end and second signal end is frame reverse signal.
Correspondingly, the present invention also provides a kind of gate driving circuit, including N grades of shifting deposit units, every grade of shifting
Position deposit unit is above-mentioned shifting deposit unit.
Optionally, defining adjacent two-stage shifting deposit unit is i-stage shifting deposit unit and i+1 grade shift LD list
Member, wherein
The cascaded-output end of the i-stage shifting deposit unit is connected to the first of the i+1 grade shifting deposit unit
Control terminal, and, the cascaded-output end of the i+1 grade shifting deposit unit is connected to the i-stage shifting deposit unit
Second control terminal.
Correspondingly, the display device includes above-mentioned gate driving circuit the present invention also provides a kind of display device.
Compared to the prior art, technical solution provided by the invention has at least the following advantages:
The present invention provides a kind of shifting deposit unit, gate driving circuit and display devices, are applied to gate driving electricity
Road, comprising: input module, pull-up node, pull-up control module, the first pull-down node, the first pull-down control module, the first drop-down
Generation module, the second pull-down node, the second pull-down control module, the second drop-down generation module, scanning output module, scanning output
End, cascaded-output module, cascaded-output end and capacitor；Wherein, by the mutual cooperation between modules, so that scanning output
End output scanning signal to grid line connected to it, meanwhile, so that cascaded-output end output signal to it is connected to it up and down
Grade shifting deposit unit.As shown in the above, shifting deposit unit is connect by technical solution provided by the invention with grid line
Port and the port that is connect with the superior and the subordinate shifting deposit units distinguish, that is, using scanning output end as the end for connecting grid line
Mouthful, and using cascaded-output end as the port of connection the superior and the subordinate's shifting deposit unit, meet the multifarious of gate driving circuit
Design.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of structural schematic diagram of shifting deposit unit provided by the embodiments of the present application；
Fig. 2 is the structural schematic diagram of another shifting deposit unit provided by the embodiments of the present application；
Fig. 3 is a kind of timing diagram along first direction scanning provided by the embodiments of the present application；
Fig. 4 is the timing diagram that one kind provided by the embodiments of the present application scans in a second direction；
Fig. 5 is a kind of structural schematic diagram of gate driving circuit provided by the embodiments of the present application；
Fig. 6 is a kind of structural schematic diagram of display device provided by the embodiments of the present application.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As described in background, in existing display device, display device includes gate driving circuit, gate driving
Circuit is mainly used for scanning multistage grid line, to be swept by scanning grid line to the pixel array being electrically connected with grid line
It retouches, and then cooperates All other routes structure and carry out the display of picture.Since people are to the multifarious demand of gate driving circuit,
Therefore gate driving circuit is designed to developer's one of main research tendency now.
Based on this, the embodiment of the present application provides a kind of shifting deposit unit, gate driving circuit and display device, will move
Position deposit unit port connected to the gate line and port differentiation connect with the superior and the subordinate shifting deposit units, that is, will scan defeated
Port of the outlet as connection grid line, and using cascaded-output end as the port of connection the superior and the subordinate's shifting deposit unit, meet
The multifarious design of gate driving circuit.To achieve the above object, technical solution provided by the embodiments of the present application is as follows, specifically
In conjunction with shown in Fig. 1 to Fig. 6, technical solution provided by the embodiments of the present application is described in detail.
Refering to what is shown in Fig. 1, being a kind of structural schematic diagram of shifting deposit unit provided by the embodiments of the present application, wherein move
Position deposit unit is applied to gate driving circuit, and shifting deposit unit includes:
Input module 100, pull-up node P, pull-up control module 200, the first pull-down node Q1, the first pull-down control module
301, the first drop-down generation module 401, the second pull-down node Q2, the second pull-down control module 302, second pull down generation module
402, output module 500, scanning output end Gout, cascaded-output module 600, cascaded-output end Gout_sub and capacitor C are scanned；
Wherein, the input module 100 in response to the first control terminal SET current potential and control first voltage end DIR1 and institute
State the on-state of pull-up node P, and, in response to the second control terminal RESET current potential and control second voltage end DIR2 with
The on-state of the pull-up node P, wherein the output level of the first voltage end DIR1 and the second voltage end DIR2
Polarity is opposite；
It is described pull-up control module 200 in response to the pull-up node P current potential and control tertiary voltage end V3 respectively with
The on-state of the first pull-down node Q1 and the second pull-down node Q2；
First pull-down control module 301 in response to the first pull-down node Q1 current potential and control it is described 4th electricity
The on-state of pressure side V4 and the scanning output end Gout, and, control the tertiary voltage end V3 respectively with the pull-up
The on-state of node P and the cascaded-output end Gout_sub, wherein the tertiary voltage end V3 and the 4th voltage end
V4 output level is identical, and the tertiary voltage end V3 output voltage is lower than the 4th voltage end V4 output voltage；It needs
Bright, tertiary voltage end V3 and the 4th voltage end V4 output level are identical, refer to and meanwhile output phase than reference voltage be positivity
Voltage or negativity voltage, i.e. the phase of voltage is identical.
Described first, which pulls down generation module 401, controls the tertiary voltage in response to the current potential of the first signal end Clock1
Hold V3 and the first pull-down node Q1 on-state, and, in response to second signal end Clock2 current potential and control institute
State the on-state of second signal end Clock2 Yu the first pull-down node Q1, wherein the first signal end Clock1 and
The output signal of the second signal end Clock2 is complementary clock signal, and described in controlling in the pull-up control module 200
When tertiary voltage end V3 and the first pull-down node Q1 is connected, the current potential of the first pull-down node Q1 is the tertiary voltage
Hold the output current potential of V3；
Second pull-down control module 302 in response to the second pull-down node Q2 current potential and control it is described 4th electricity
The on-state of pressure side V4 and the scanning output end Gout, and, control the tertiary voltage end V3 respectively with the pull-up
The on-state of node P and the cascaded-output end Gout_sub；
Described second, which pulls down generation module 402, controls the third in response to the current potential of the second signal end Clock2
The on-state of voltage end V3 and the second pull-down node Q2, and, in response to the current potential of the first signal end Clock1
And control the on-state of the first signal end Clock1 Yu the second pull-down node Q2, wherein control in the pull-up
When module 200 controls the tertiary voltage end V3 and the second pull-down node Q2 connection, the electricity of the second pull-down node Q2
Position is the current potential of the tertiary voltage end V3；
The output module 500 that scans controls clock signal terminal CK and scanning in response to the current potential of the pull-up node P
The on-state of output end Gout；
The cascaded-output module 600 in response to the pull-up node P current potential and control clock signal terminal CK and cascade
The on-state of output end Gout_sub；
And the capacitor C is used for the ground of the scanning output end Gout to the pull-up node P.
Technical solution provided by the embodiments of the present application, by the mutual cooperation between modules, so that scanning output end
Scanning signal is exported to grid line connected to it, meanwhile, so that cascaded-output end outputs signal to the superior and the subordinate connected to it
Shifting deposit unit, wherein connect by shifting deposit unit port connected to the gate line and with the superior and the subordinate shifting deposit units
Port distinguish, that is, using scanning output end as connection grid line port, and using cascaded-output end as connect the superior and the subordinate shifting
The port of position deposit unit, meets the multifarious design of gate driving circuit.
As shown in connection with fig. 2, detailed to a kind of structure progress of specific shifting deposit unit provided by the embodiments of the present application
Explanation.Wherein, Fig. 2 is the structural schematic diagram of another shifting deposit unit provided by the embodiments of the present application.
In conjunction with referring to fig. 1 and fig. 2, in one embodiment of the application, the input module 100 includes: first crystal
Pipe M1 and second transistor M2；
Wherein, the grid of the first transistor M1 is connected to the first control terminal SET, the first transistor M1's
First end is connected to the first voltage end DIR1, and the second end of the first transistor M1 is connected to the pull-up node P；Institute
The grid for stating second transistor M2 is connected to the second control terminal RESET, and the first end of the second transistor M2 is connected to
The second voltage end DIR2, the second end of the second transistor M2 are connected to the pull-up node P.
It should be noted that conducting class of the embodiment of the present application for the first transistor M1 and second transistor M2 of offer
Type is identical, can be N-type transistor, can also be P-type transistor, is specifically designed according to practical application this needs；
The first transistor M1 that the embodiment of the present application preferably provides is identical with the conductivity type of second transistor M2.In addition, due to needing
The current potential of pull-up node P is defined, thus, for input module 100, the first control terminal SET control pull-up node P with
When connecting between the DIR1 of first voltage end, the second control terminal RESET not can control between pull-up node P and second voltage end DIR2
It connects；And when being connected between the second control terminal RESET control pull-up node P and second voltage end DIR2, the first control terminal
SET not can control to be connected between pull-up node P and first voltage end DIR1；That is, the first transistor M1 and the second crystal
Pipe M2 cannot be simultaneously turned on.
In conjunction with referring to fig. 1 and fig. 2, in one embodiment of the application, the pull-up control module 200 includes: third
Transistor M3 and the 4th transistor M4；
Wherein, the grid of the third transistor M3 and the 4th transistor M4 is connected to the pull-up node P, and described
The first end of three transistor M3 and the 4th transistor M4 is connected to the tertiary voltage end V3, and the of the third transistor M3
Two ends are connected to the first pull-down node Q1, and the second end of the 4th transistor M4 is connected to second pull-down node
Q2。
It should be noted that the conductivity type phase of third transistor M3 and the 4th transistor M4 provided by the embodiments of the present application
Together, and the application is not particularly limited the conductivity type of the two, all can be N-type transistor, can also be P-type crystal
Pipe is designed this needs according to effective current potential of pull-up node P in practical application.
In addition, the level signal of tertiary voltage end V3 provided by the embodiments of the present application and the 4th voltage end V4 output is identical,
It can be high level signal, can also be low level signal, specifically be designed according to practical application this needs；Wherein,
The level signal of tertiary voltage end V3 output meets when output is to cascaded-output end Gout_sub, cannot be on connected to it
Junior's shifting deposit unit is scanned (i.e. the signal cannot make transistor turns in the superior and the subordinate's shifting deposit unit), with
And the 4th the level signal of voltage end V4 output meet when output is to scanning output end Gout, cannot to scanning output end
The grid line of Gout connection is scanned (i.e. the signal cannot be scanned pixel array connected to the gate line).
In conjunction with referring to fig. 1 and fig. 2, in one embodiment of the application, first pull-down control module 301 includes:
5th transistor M5, the 6th transistor M6 and the 7th transistor M7；
Wherein, the grid of the 5th transistor M5, the 6th transistor M6 and the 7th transistor M7 are connected to described
One pull-down node Q1, the first end of the 5th transistor M5 are connected to the 4th voltage end V4, the 5th transistor M5
Second end be connected to the scanning output end Gout, the first end of the 6th transistor M6 is connected to the tertiary voltage end
V3, the second end of the 6th transistor M6 are connected to the pull-up node P, and the first end of the 7th transistor M7 is connected to
The second end of the tertiary voltage end V3, the 7th transistor M7 are connected to the cascaded-output end Gout_sub.
In one embodiment of the application, the circuit structure of the first pull-down control module 301 and the second pull-down control module 302
It is identical, that is, second pull-down control module 302 includes: the tenth transistor M10, the 11st transistor M11 and the 12nd crystal
Pipe M12；
Wherein, the grid of the tenth transistor M10, the 11st transistor M11 and the tenth two-transistor M12 are connected to
The second pull-down node Q2, the first end of the tenth transistor M10 are connected to the 4th voltage end V4, and the described tenth is brilliant
The second end of body pipe M10 is connected to the scanning output end Gout, and the first end of the 11st transistor M11 is connected to described
Tertiary voltage end V3, the second end of the 11st transistor M11 are connected to the pull-up node P, the tenth two-transistor
The first end of M12 is connected to the tertiary voltage end V3, and it is defeated that the second end of the tenth two-transistor M12 is connected to the cascade
Outlet Gout_sub.
It should be noted that in the application other embodiments, the first pull-down control module 301 and the second drop-down control mould
The circuit structure of block 302 is also designed to difference, is not particularly limited to this application.And the embodiment of the present application provides
The 5th transistor M5, the 6th transistor M6 and the 7th transistor M7 conductivity type it is identical, all can be P-type transistor,
It can also be N-type transistor, this needs is specifically designed according to effective current potential of the first pull-down node Q1；And this Shen
Please embodiment provide the tenth transistor M10, the 11st transistor M11 and the tenth two-transistor M12 conductivity type it is identical,
All can be P-type transistor, can also be N-type transistor, to this needs according to effective current potential of the second pull-down node Q1 carry out
Specific design.
In conjunction with referring to fig. 1 and fig. 2, in one embodiment of the application, the first drop-down generation module 401 includes:
8th transistor M8 and the 9th transistor M9；
Wherein, the grid of the 8th transistor M8 is connected to the first signal end Clock1, the 8th transistor
The first end of M8 is connected to the tertiary voltage end V3, and the second end of the 8th transistor M8 is connected to the first drop-down section
Point Q1, the grid of the 9th transistor M9 are connected to the second signal end Clock2, and the first of the 9th transistor M9
End is connected to the second signal end Clock2, and the second end of the 9th transistor M9 is connected to first pull-down node
Q1。
In one embodiment of the application, the circuit structure of the first drop-down generation module 401 and the second drop-down generation module 402
It is identical and opposite for the connection relationship of the first signal end Clock1 and second signal end Clock2, that is, the second drop-down life
It include: the 13rd transistor M13 and the 14th transistor M14 at module 402；
Wherein, the grid of the 13rd transistor M13 is connected to the second signal end Clock2, and the described 13rd is brilliant
The first end of body pipe M13 is connected to the tertiary voltage end V3, and the second end of the 13rd transistor M13 is connected to described
Two pull-down node Q2, the grid of the 14th transistor M14 are connected to the first signal end Clock1, and the described 14th is brilliant
The first end of body pipe M14 is connected to the first signal end Clock1, and the second end of the 14th transistor M14 is connected to institute
State the second pull-down node Q2.
It should be noted that the conductivity type phase of the 8th transistor M8 and the 9th transistor M9 provided by the embodiments of the present application
Together, it can be N-type transistor, can also be P-type transistor, to this needs according to the first signal end Clock1 and second signal
The significant level of end Clock2 is specifically designed；And the 13rd transistor M13 and the 14th provided by the embodiments of the present application
The conductivity type of transistor M14 is identical, can be N-type transistor, can also be P-type transistor, to this needs according to first
The significant level of signal end Clock1 and second signal end Clock2 are specifically designed.
In conjunction with referring to fig. 1 and fig. 2, in one embodiment of the application, the scanning output module 500 includes: the tenth
Five transistor M15；
Wherein, the grid of the 15th transistor M15 is connected to the pull-up node P, the 15th transistor M15
First end be connected to the clock signal terminal CK, the second end of the 15th transistor M15 is connected to the scanning output
Hold Gout.
And in conjunction with referring to fig. 1 and fig. 2, the cascaded-output module 600 includes: the 16th transistor M16；
Wherein, the grid of the 16th transistor M16 is connected to the pull-up node P, the 16th transistor M16
First end be connected to the clock signal terminal CK, the second end of the 16th transistor M16 is connected to the cascaded-output
Hold Gout_sub.
It should be noted that the conducting of the 15th transistor M15 and the 16th transistor M16 provided by the embodiments of the present application
Type is identical, can be N-type transistor, can also be P-type transistor, to this needs according to effective current potential of pull-up node P
Specifically designed.
In one embodiment of the application, the level of the first signal end Clock1 and second signal end Clock2 with it is described
When the level of tertiary voltage end V3 is identical, the first signal end Clock1 and second signal end Clock2 output voltage with it is described
Tertiary voltage end V3 output voltage is identical.
Wherein, in order to make the 8th transistor M8 or the 13rd transistor M13 cut-off when shutdown effect it is more preferable, and in order to
Keep the shutdown effect of the 7th transistor M7 or the 14th transistor M14 in cut-off more preferable, preferred first signal end of the application
When the level of Clock1 and second signal end Clock2 are identical as the level of the tertiary voltage end V3, i.e. voltage signal phase phase
Meanwhile first signal end Clock1 and second signal end Clock2 output voltage it is identical as tertiary voltage end V3 output voltage, into
And gate terminal voltage is identical with first end voltage when the 8th transistor M8 or the 13rd transistor M13 are turned off, and makes the
Gate terminal voltage is identical with first end voltage when the shutdown of seven transistor M7 or the 14th transistor M14, to improve shutdown effect.
Specifically for example, when the level signal that the first signal end Clock1 or second signal end Clock2 is exported is low level, and simultaneously
When the level signal of tertiary voltage end V3 output is low level, at this point, the first signal end Clock1 or second signal end Clock2
Output voltage is identical as the tertiary voltage end V3 output voltage, is such as -15V.
And the level of the clock signal terminal CK it is identical as the level of the 4th voltage end V4 when, clock letter
Number end CK output voltage it is identical as the 4th voltage end V4 output voltage.Wherein, due to scanning output module 500 in response to
The current potential of pull-up node P, and when controlling clock signal terminal CK and scanning output end Gout and connecting, it is connect with scanning output end Gout
Grid line current potential be clock signal terminal CK output current potential, so, in order to reach transistor connected to the gate line more
Good shutdown purpose, when the level of the preferred clock signal terminal CK of the application is identical as the level of the 4th voltage end V4, clock letter
Number end CK output voltage it is identical with the 4th voltage end V4 output voltage, e.g., clock signal terminal CK be failing edge output it is low
When level and the 4th voltage end V4 output low level, clock signal terminal CK selects the output of lower voltage value, i.e., with the 4th voltage
Hold the voltage of V4 output identical.
In one embodiment of the application, gate driving circuit can be the gate driving circuit of bilateral scanning, wherein in institute
When stating gate driving circuit along first direction scanning, the first control terminal SET exports open signal；
And when the gate driving circuit scans in a second direction, letter is opened in the second control terminal RESET output
Number, wherein the first direction and second direction are opposite.
That is, the first control terminal SET of shifting deposit unit is exported first when gate driving circuit is scanned along first direction
Open signal, so that shifting deposit unit is started to work, and after open signal output, the scanning of shifting deposit unit is defeated
(corresponding signal is upper level shift LD to the signal and cascaded-output end output corresponding signal of outlet output scanning grid line
The shutdown signal that unit provides and the open signal provided for next stage shifting deposit unit, wherein shutdown signal and unlatching letter
Number it is same signal) to the superior and the subordinate's shifting deposit unit, and in ending phase, the second control terminal RESET exports shutdown signal,
So that the scanning output end of shifting deposit unit no longer exports scanning signal；
And when gate driving circuit scans in a second direction, the second control terminal RESET of shifting deposit unit is first
Open signal is exported, so that shifting deposit unit is started to work, and after open signal output, shifting deposit unit is swept
(corresponding signal is upper level displacement to the signal and cascaded-output end output corresponding signal for retouching output end output scanning grid line
The shutdown signal that deposit unit provides and the open signal that is provided for next stage shifting deposit unit, wherein shutdown signal and open
Opening signal is same signal) to the superior and the subordinate's shifting deposit unit, and in ending phase, letter is closed in the first control terminal RET output
Number, so that the scanning output end of shifting deposit unit no longer exports scanning signal.
In addition, controlling the tertiary voltage end V3 and second drop-down in the pull-up control module 200 to meet
When node Q2 is connected, the current potential of the second pull-down node Q2 is the current potential of the tertiary voltage end V3, and, in the pull-up
When control module 200 controls the tertiary voltage end V3 and the first pull-down node Q1 connection, the first pull-down node Q1
Current potential be the tertiary voltage end V3 output current potential, the breadth length ratio of third transistor M3 provided by the embodiments of the present application is greater than
The breadth length ratio of 9th transistor, and, the breadth length ratio of the 4th transistor M4 is greater than the breadth length ratio of the 14th transistor M14.
In one embodiment of the application, due to the first drop-down generation module 401 and the second drop-down generation module 402 and first
The connection relationship of signal end Clock1 and second signal end Clock2 are on the contrary, and the first signal end Clock1 and second signal end
The output signal of Clock2 is complementary clock signal, so after shifting deposit unit is scanned, the first pull-down node Q1 and
Second pull-down node Q2 is alternately second signal end Clock2 and the significant level signal of the first signal end Clock1 output, in order to
Achieve the purpose that reduce power consumption, the preferred first signal end Clock1's and second signal end Clock2 of the embodiment of the present application
Output signal is frame reverse signal, that is, so that the first pull-down node Q1 and the second pull-down node Q2 are swept in shifting deposit unit
After retouching, significant level signal thereon is that frame picture alternating is primary.
Below with reference to driving method to all modules and composition of shifting deposit unit provided by the embodiments of the present application
The connection of each transistor of module and cut-off situation are further described.It should be noted that being believed below with high level
Number effective shifting deposit unit is described, that is, with the first transistor M1 to the 16th transistor M16 is N-type transistor
For be illustrated, and, using the output signal of tertiary voltage end V3 and the 4th voltage end V4 as low level signal, shift LD
The significant level of the output of the scanning output end Gout and cascaded-output end Gout_sub of unit be high level for be illustrated.
In conjunction with shown in Fig. 1, Fig. 2, Fig. 3 and Fig. 4, driving method provided by the embodiments of the present application is described in detail,
In, driving method provided by the embodiments of the present application, applied to above-mentioned shifting deposit unit, and driving method includes: the first rank
Section T1, second stage T2 and phase III T3.
Refering to what is shown in Fig. 3, for a kind of timing diagram along first direction scanning provided by the embodiments of the present application, wherein first
The output level of voltage end DIR1 is high level, and the output level of second voltage end DIR2 is low level, is swept along first direction
When retouching:
T1 in the first stage, input module 100 and control first voltage end in response to the current potential of the first control terminal SET
It is connected between DIR1 and pull-up node P, the current potential of pull-up node P is the high level of first voltage end DIR1 output；Wherein, it pulls up
Control module 200 in response to pull-up node P current potential, and control tertiary voltage end V3 respectively with the first pull-down node Q1 and second
It is connected between pull-down node Q2；And scanning output module 500 and cascaded-output module 600 are both responsive to the electricity of pull-up node P
Position, and control clock signal terminal CK and connected between scanning output end Gout and cascaded-output end Gout_sub respectively, this is constantly
Clock signal end CK output level is low level (i.e. output signal is shutdown signal).
It specifically combines shown in Fig. 2 and Fig. 3, in the first stage T1, the first control terminal SET output level is flat for high point, and controls
The first transistor M1 conducting processed, so that the current potential of pull-up node P is the high level of first voltage end DIR1 output.And then with pull-up
Third transistor M3, the 4th transistor M4, the 15th transistor M15 and the 16th transistor M16 of node P connection are both turned on,
So that the current potential of the first pull-down node Q1 and the second pull-down node Q2 are the low level of tertiary voltage end V3 output, and, make
The output signal for obtaining scanning output end Gout and cascaded-output end Gout_sub is the level of clock signal terminal CK output.Wherein,
Since the current potential of the first pull-down node Q1 and the second pull-down node Q2 are low level, so, so that the crystal being connected to the two
Pipe is off state.
In second stage T2, scans output module 500 and cascaded-output module 600 is both responsive to the current potential of pull-up node P,
And control clock signal terminal CK and connected between scanning output end Gout and cascaded-output end Gout_sub respectively, clock is believed at this time
Number end CK output level be high level.
It specifically combines shown in Fig. 2 and Fig. 3, in second stage T2, the current potential of a pole plate of capacitor C is clock signal terminal at this time
The high level of CK output, so, capacitor C will be by the high level for the pull-up node P connecting with its another pole plate, in the first stage
It is drawn high again on the basis of T1.Since the current potential of pull-up node P remains high level, thus the crystal being connected to pull-up node P
Pipe keeps the state of first stage T1 constant.And in second stage T2, clock signal terminal CK output level is high level, should
High level signal passes through the 15th transistor M15 and the 16th transistor M16 respectively, is transmitted to scanning output end Gout and cascade
Output end Gout_sub.
In phase III T3, input module 100 and controls second voltage end in response to the current potential of the second control terminal RESET
It is connected between DIR2 and pull-up node P, the current potential of pull-up node P is the low level of second voltage end DIR2 output；Wherein, first
Generation module 401 is pulled down in response to the current potential of second signal end Clock2, and controls the drop-down of second signal end Clock2 and first
It is connected between node Q1；Alternatively, current potential of the second drop-down generation module 402 in response to the first signal end Clock1, and control the
It is connected between one signal end Clock1 and the second pull-down node Q2.At this point, the first pull-down node Q1 control the first drop-down control mould
The work of block 301 or the second pull-down node Q2 control the work of the second pull-down control module 302, so that pull-up node P and tertiary voltage
It is connected between the V3 of end, connection and cascaded-output end Gout_sub and third electricity between scanning output end Gout and the 4th voltage end V4
It is connected before pressure side V3.
It specifically combines shown in Fig. 2 and Fig. 3, in phase III T3, the second control terminal RESET exports high level, and controls the
Two-transistor M2 conducting so that the current potential of pull-up node P be second voltage end DIR2 output low level, at this time with pull-up node
The transistor of P connection is turned off.Due to the high level of the first signal end Clock1 output, so, the first signal end Clock1 control
The 14th transistor M14 conducting is made, the first signal end Clock1 high level exported is transmitted to the second pull-down node Q2, and the
The current potential of one pull-down node Q1 is the low level of tertiary voltage end V3 output；At this point, the second pull-down node Q2 controls the tenth crystal
Pipe M10, the 11st transistor M11 and the tenth two-transistor M12 conducting, so that the current potential of scanning output end Gout is the 4th voltage
The current potential of the low level, pull-up node P of holding V4 output is the low level and cascaded-output end Gout_ of tertiary voltage end V3 output
The current potential of sub is the low level of tertiary voltage end V3 output.Wherein, since tertiary voltage end V3 output voltage is lower than the 4th voltage
Hold V4 output voltage, and the electricity of the 15th transistor M15 four voltage end V4 of voltage value-the of Vgs=tertiary voltage end V3 at this time
Pressure value, that is, Vgs is that negative so that the leakage current of the 15th transistor M15 is smaller improves shifting to the 15th transistor M15 at this time
The output stability of position deposit unit.Further, since cascaded-output end Gout_sub output voltage values are that tertiary voltage end V3 is defeated
Lower low level out, so, the transistor being accordingly connected in the superior and the subordinate's shifting deposit unit can be effectively closed, is avoided
It causes to mislead since voltage value is higher.
It should be noted that the first signal end Clock1 can also be set to output low level in phase III T3, and
Output high level is set by second signal end Clock2, this embodiment of the present application is not particularly limited.
And in conjunction with shown in Fig. 1, Fig. 2 and Fig. 4, Fig. 4 one kind provided by the embodiments of the present application scans in a second direction
Timing diagram, driving method equally include first stage T1, second stage T2 and phase III T3, wherein are swept with along first direction
Unlike retouching, when scanning in a second direction, first voltage end DIR1 exports low level, and DIR2 output in second voltage end is high
Level；And second control terminal RESET in the first stage T1 export high level, and the first control terminal SET is defeated in phase III T3
High level out scans the operational process of shift deposit unit in a second direction, sweeps with along first direction in addition to above-mentioned difference
Operational process when retouching is identical, therefore the application does not make extra repeat.
Correspondingly, the embodiment of the present application also provides a kind of gate driving circuit, including N grades of shifting deposit units, every grade
The shifting deposit unit is the shifting deposit unit that above-mentioned any one embodiment provides.
It is a kind of structural schematic diagram of gate driving circuit provided by the embodiments of the present application with specific reference to shown in Fig. 5,
In, define adjacent two-stage shifting deposit unit be i-stage shifting deposit unit 1i and i+1 grade shifting deposit unit 1 (i+1),
Wherein,
The cascaded-output end Gout_sub of the i-stage shifting deposit unit 1i is connected to the i+1 grade shift LD
First control terminal SET of unit 1 (i+1), and, the cascaded-output end Gout_ of the i+1 grade shifting deposit unit 1 (i+1)
Sub is connected to the second control terminal RESET of the i-stage shifting deposit unit 1i.
Wherein, the clock signal terminal of the shifting deposit unit of the preferred odd level of the embodiment of the present application is the same end, and even
The clock signal terminal of the shifting deposit unit of several levels is the same end.
Correspondingly, with specific reference to shown in Fig. 6, implementing the embodiment of the present application also provides a kind of display device for the application
The structural schematic diagram for a kind of display device that example provides, wherein the display device includes that there is above-mentioned any one embodiment to mention
The display panel 10 of the gate driving circuit of confession；
And when display device is liquid crystal display device, display device further includes providing backlight for display panel 10
The backlight source module 20 of (as shown by arrows).
It should be noted that the application is not particularly limited the type of the display device of offer, such as the application its
In his embodiment, display device can also be organic light-emitting display device.
The embodiment of the present application provides a kind of shifting deposit unit, gate driving circuit and display device, is applied to grid
Driving circuit, comprising: input module, pull-up node, pull-up control module, the first pull-down node, the first pull-down control module, the
One drop-down generation module, the second pull-down control module, the second drop-down generation module, scanning output module, is swept at the second pull-down node
Retouch output end, cascaded-output module, cascaded-output end and capacitor；Wherein, by the mutual cooperation between modules, so that sweeping
It retouches output end and exports scanning signal to grid line connected to it, meanwhile, so that cascaded-output end outputs signal to and is connected thereto
The superior and the subordinate's shifting deposit unit.As shown in the above, technical solution provided by the embodiments of the present application, by shifting deposit unit
Port connected to the gate line and the port connecting with the superior and the subordinate shifting deposit units are distinguished, that is, using scanning output end as company
The port of grid line is connect, and using cascaded-output end as the port of connection the superior and the subordinate's shifting deposit unit, meet gate driving electricity
The multifarious design on road.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (16)
1. a kind of shifting deposit unit, be applied to gate driving circuit characterized by comprising input module, pull-up node,
Pull up control module, the first pull-down node, the first pull-down control module, the first drop-down generation module, the second pull-down node, second
Pull-down control module, the second drop-down generation module, scanning output module, scanning output end, cascaded-output module, cascaded-output end
And capacitor；
Wherein, the input module in response to the first control terminal current potential and control connecing for first voltage end and the pull-up node
Logical state, and, in response to the second control terminal current potential and control the on-state at second voltage end Yu the pull-up node,
In, the output level polarity at the first voltage end and the second voltage end is opposite；
The pull-up control module in response to the pull-up node current potential and control tertiary voltage end respectively with described first under
Draw the on-state of node and second pull-down node；
First pull-down control module in response to first pull-down node current potential and control the 4th voltage end and swept with described
Retouch the on-state of output end, and, control the tertiary voltage end respectively with the pull-up node and the cascaded-output end
On-state, wherein the tertiary voltage end is identical with the 4th voltage end output level, and the tertiary voltage end is defeated
Voltage is lower than the 4th voltage end output voltage out；
Described first, which pulls down generation module, controls the tertiary voltage end and described first in response to the current potential of the first signal end
The on-state of pull-down node, and, in response to second signal end current potential and control the second signal end and described first
The on-state of pull-down node, wherein the output signal at first signal end and the second signal end is complementary clock letter
Number, and when the pull-up control module controls the tertiary voltage end and first pull-down node is connected, under described first
Draw the current potential of node for the output current potential at the tertiary voltage end；
Second pull-down control module in response to second pull-down node current potential and control the 4th voltage end and institute
The on-state of scanning output end is stated, and, it is defeated with the pull-up node and the cascade respectively to control the tertiary voltage end
The on-state of outlet；
It is described second drop-down generation module in response to the second signal end current potential and control the tertiary voltage end with it is described
The on-state of second pull-down node, and, in response to first signal end current potential and control first signal end with
The on-state of second pull-down node, wherein control the tertiary voltage end and described the in the pull-up control module
When two pull-down nodes are connected, the current potential of second pull-down node is the current potential at the tertiary voltage end；
The scanning output module in response to the pull-up node current potential and control connecing for clock signal terminal and scanning output end
Logical state；
The cascaded-output module in response to the pull-up node current potential and control connecing for clock signal terminal and cascaded-output end
Logical state；
And the capacitor is used for the ground of the scanning output end to the pull-up node.
2. shifting deposit unit according to claim 1, which is characterized in that the input module includes: the first transistor
And second transistor；
Wherein, the grid of the first transistor is connected to first control terminal, the first end connection of the first transistor
To the first voltage end, the second end of the first transistor is connected to the pull-up node；The grid of the second transistor
Pole is connected to second control terminal, and the first end of the second transistor is connected to the second voltage end, and described second is brilliant
The second end of body pipe is connected to the pull-up node.
3. shifting deposit unit according to claim 1, which is characterized in that the pull-up control module includes: third crystalline substance
Body pipe and the 4th transistor；
Wherein, the grid of the third transistor and the 4th transistor is connected to the pull-up node, the third transistor
It is connected to the tertiary voltage end with the first end of the 4th transistor, the second end of the third transistor is connected to described
The second end of one pull-down node, the 4th transistor is connected to second pull-down node.
4. shifting deposit unit according to claim 1, which is characterized in that first pull-down control module includes:
Five transistors, the 6th transistor and the 7th transistor；
Wherein, the grid of the 5th transistor, the 6th transistor and the 7th transistor is connected to first pull-down node,
The first end of 5th transistor is connected to the 4th voltage end, and the second end of the 5th transistor is connected to described sweep
Output end is retouched, the first end of the 6th transistor is connected to the tertiary voltage end, and the second end of the 6th transistor connects
It is connected to the pull-up node, the first end of the 7th transistor is connected to the tertiary voltage end, the 7th transistor
Second end is connected to the cascaded-output end.
5. shifting deposit unit according to claim 1, which is characterized in that the first drop-down generation module includes: the
Eight transistors and the 9th transistor；
Wherein, the grid of the 8th transistor is connected to first signal end, the first end connection of the 8th transistor
To the tertiary voltage end, the second end of the 8th transistor is connected to first pull-down node, the 9th transistor
Grid be connected to the second signal end, the first end of the 9th transistor is connected to the second signal end, described
The second end of nine transistors is connected to first pull-down node.
6. shifting deposit unit according to claim 1, which is characterized in that second pull-down control module includes:
Ten transistors, the 11st transistor and the tenth two-transistor；
Wherein, the grid of the tenth transistor, the 11st transistor and the tenth two-transistor is connected to second drop-down
Node, the first end of the tenth transistor are connected to the 4th voltage end, and the second end of the tenth transistor is connected to
The scanning output end, the first end of the 11st transistor are connected to the tertiary voltage end, the 11st transistor
Second end be connected to the pull-up node, the first end of the tenth two-transistor is connected to the tertiary voltage end, described
The second end of tenth two-transistor is connected to the cascaded-output end.
7. shifting deposit unit according to claim 1, which is characterized in that the second drop-down generation module includes: the
13 transistors and the 14th transistor；
Wherein, the grid of the 13rd transistor is connected to the second signal end, the first end of the 13rd transistor
It is connected to the tertiary voltage end, the second end of the 13rd transistor is connected to second pull-down node, and the described tenth
The grid of four transistors is connected to first signal end, and the first end of the 14th transistor is connected to first signal
End, the second end of the 14th transistor are connected to second pull-down node.
8. shifting deposit unit according to claim 1, which is characterized in that the scanning output module includes: the 15th
Transistor, the grid of the 15th transistor are connected to the pull-up node, the first end connection of the 15th transistor
To the clock signal terminal, the second end of the 15th transistor is connected to the scanning output end.
9. shifting deposit unit according to claim 1, which is characterized in that the cascaded-output module includes: the 16th
Transistor, the grid of the 16th transistor are connected to the pull-up node, the first end connection of the 16th transistor
To the clock signal terminal, the second end of the 16th transistor is connected to the cascaded-output end.
10. shifting deposit unit according to claim 1, which is characterized in that first signal end and second signal end
Level it is identical as the level at the tertiary voltage end when, first signal end and second signal end output voltage and described the
Three voltage end output voltages are identical.
11. shifting deposit unit according to claim 1, which is characterized in that the level of the clock signal terminal with it is described
When the level of 4th voltage end is identical, the clock signal terminal output voltage is identical as the 4th voltage end output voltage.
12. shifting deposit unit according to claim 1, which is characterized in that in the gate driving circuit along first party
To when scanning, first control terminal exports open signal；
And when the gate driving circuit scans in a second direction, second control terminal exports open signal, wherein
The first direction and second direction are opposite.
13. shifting deposit unit according to claim 1, which is characterized in that first signal end and second signal end
Output signal be frame reverse signal.
14. a kind of gate driving circuit, which is characterized in that including N grades of shifting deposit units, every grade of shifting deposit unit is equal
For shifting deposit unit described in claim 1~13 any one.
15. gate driving circuit according to claim 14, which is characterized in that defining adjacent two-stage shifting deposit unit is
I-stage shifting deposit unit and i+1 grade shifting deposit unit, wherein
The cascaded-output end of the i-stage shifting deposit unit is connected to the first control of the i+1 grade shifting deposit unit
End, and, the cascaded-output end of the i+1 grade shifting deposit unit is connected to the second of the i-stage shifting deposit unit
Control terminal.
16. a kind of display device, which is characterized in that the display device includes the electricity of gate driving described in claims 14 or 15
Road.
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| US20220375411A1 (en) * | 2021-05-19 | 2022-11-24 | Xiamen Tianma Micro-electronics Co.,Ltd. | Shift register and driving method thereof, and display panel |
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| CN110808015B (en) * | 2018-03-30 | 2021-10-22 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, display device and drive method |
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| CN106157923A (en) * | 2016-09-26 | 2016-11-23 | 合肥京东方光电科技有限公司 | Shift register cell and driving method, gate driver circuit, display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220375411A1 (en) * | 2021-05-19 | 2022-11-24 | Xiamen Tianma Micro-electronics Co.,Ltd. | Shift register and driving method thereof, and display panel |
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