CN106409211A - Gate drive circuit, array substrate and display device - Google Patents
Gate drive circuit, array substrate and display device Download PDFInfo
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- CN106409211A CN106409211A CN201611140481.1A CN201611140481A CN106409211A CN 106409211 A CN106409211 A CN 106409211A CN 201611140481 A CN201611140481 A CN 201611140481A CN 106409211 A CN106409211 A CN 106409211A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention provides a gate drive circuit, an array substrate and a display device. Under the control of a signal inputted by an input terminal, a shift register transmits a clock signal of a first electrical level inputted by a second clock signal terminal to an output terminal in the first period of time, and transmits a clock signal of a second electrical level inputted by the second clock signal terminal to the output terminal in the second period of time. Under the control of a signal inputted by a first clock signal terminal, the shift register transmits a pull-down signal of the second electrical level to the output terminal in the second and third periods of time. Under the control of a signal inputted by a first reset terminal, the shift register stops transmitting the clock signal inputted by the second clock signal terminal to the output terminal in the third period of time. On this basis, the electric potential of a gate line can be pulled down together by the clock signal of the second electrical level and the pull-down signal of the second electrical level in the second period of time. Therefore, fast pulldown of the gate line is guaranteed and the power-off capability of a thin film transistor of a pixel unit and the charging capability of the pixel unit are further improved.
Description
Technical field
The present invention relates to display device technical field, more particularly, it relates to a kind of gate driver circuit, array base palte and
Display device.
Background technology
A kind of existing display floater, including a plurality of gate line, a plurality of data lines, multiple pixel cell, raster data model electricity
Road data drive circuit.Wherein, gate driver circuit includes multiple shift registers, the output end of each shift register with
Article one, gate line is connected, and data drive circuit is connected with a plurality of data lines.Gate driver circuit is used for a plurality of gate line successively
Output scanning signal, data drive circuit is used for data wire output data drive signal, to drive pixel cell to carry out image
Display.
During progressive scan pixel cell, the gate line that shift register is first connected to corresponding line pixel cell is defeated
Enter scanning signal, so that the thin film transistor (TFT) of this row pixel cell is opened, drive this row pixel cell to carry out the display of image, afterwards
Input pulldown signal to this gate line, with the current potential of drop-down gate line, so that the thin film transistor (TFT) of this row pixel cell is closed.But
Be, existing shift register cannot quick pull-down gate line current potential, thus leading to the pass of the thin film transistor (TFT) of pixel cell
Cutting capacity is poor, and then affects charging ability and the display effect of pixel cell.
Content of the invention
In view of this, the invention provides a kind of gate driver circuit, array base palte and display device, to solve existing skill
In art shift register cannot quick pull-down gate line current potential, lead to the turn-off capacity of pixel cell thin film transistor (TFT) poor
Problem.
For achieving the above object, the present invention provides following technical scheme：
A kind of gate driver circuit, including the 1st grade of shift register cascading to n-th grade of shift register, n is more than 2
Integer；
Each described shift register all includes input, output end, the first reset terminal, the first clock signal terminal and second
Clock signal terminal；
Under the control of the signal of described input input, described shift register is in the first period by described second clock
The clock signal transmission of the first level of signal end input to described output end, in the second period by described second clock signal end
The clock signal transmission of the second electrical level of input is more than described second electrical level to described output end, described first level；
Under the control of the signal of described first clock signal terminal input, described shift register in described second period and
3rd period transmitted the pulldown signal of second electrical level to described output end；
Under the control of the signal of described first reset terminal input, described shift register stopped in described 3rd period will
The clock signal transmission of described second clock signal end input is to described output end.
A kind of array base palte, including a plurality of gate line and gate driver circuit；
Described gate driver circuit is gate driver circuit as above；
The 1st grade of shift register in described gate driver circuit to n-th grade of shift register output end respectively with institute
State a plurality of gate line and correspond and be connected.
A kind of display device, including array base palte as above.
Compared with prior art, technical scheme provided by the present invention has advantages below：
Gate driver circuit provided by the present invention, array base palte and display device, because shift register is when second
Section by the clock signal transmission of the second electrical level of second clock signal end input to output end, when stopping second the 3rd period
The clock signal transmission of the second electrical level of clock signal end input receives and resets to output end, i.e. the first reset terminal of shift register
The clock signal transmission of the second electrical level that second clock signal end is inputted by the time of signal and shift register is to output end
There is between time time interval, therefore, shift register can be in the second period by the clock signal of second electrical level and the
The current potential of the pulldown signal common pulldown gate line of two level, thereby may be ensured that the quick pull-down of gate line, and then can carry
The turn-off capacity of the thin film transistor (TFT) of high pixel cell and the charging ability of pixel cell.
Brief description
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Have technology description in required use accompanying drawing be briefly described it should be apparent that, drawings in the following description be only this
Inventive embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing providing obtains other accompanying drawings.
Fig. 1 is a kind of structural representation of existing gate driver circuit；
Fig. 2 is the signal timing diagram of the shift register shown in Fig. 1；
Fig. 3 is a kind of structural representation of gate driver circuit provided in an embodiment of the present invention；
Fig. 4 is the signal timing diagram of the shift register shown in Fig. 3；
Fig. 5 is the structural representation of another kind gate driver circuit provided in an embodiment of the present invention；
Fig. 6 is the structural representation of another kind gate driver circuit provided in an embodiment of the present invention；
Fig. 7 is the structural representation of another kind gate driver circuit provided in an embodiment of the present invention；
Fig. 8 is a kind of internal structure schematic diagram of shift register in gate driver circuit provided in an embodiment of the present invention；
Fig. 9 is the signal timing diagram of the shift register shown in Fig. 8；
Figure 10 is that another kind of internal structure of shift register in gate driver circuit provided in an embodiment of the present invention is illustrated
Figure；
Figure 11 is a kind of planar structure schematic diagram of array base palte provided in an embodiment of the present invention.
Specific embodiment
As described in background, existing shift register cannot quick pull-down gate line current potential, thus leading to picture
The turn-off capacity of the thin film transistor (TFT) of plain unit is poor, and then affects charging ability and the display effect of pixel cell.
With reference to Fig. 1, Fig. 1 is a kind of structural representation of existing gate driver circuit, and this gate driver circuit includes many
The shift register of individual cascade.Wherein, in two adjacent shift registers, the first clock signal terminal of a shift register
CK is connected with the first clock cable CK1, second clock signal end CKB is connected with second clock holding wire CKB1, another shifting
First clock signal terminal CK of bit register is connected with the 3rd clock cable CK2, second clock signal end CKB and the 4th clock
Holding wire CKB2 is connected.
And, output end OUT of the 1st shift register M1 is connected with the input SET of the 5th shift register M5,
Output end OUT of the 5th shift register M5 is connected with the reset terminal RESET of the 1st shift register M1, and the 2nd displacement is posted
Output end OUT of storage M2 is connected with the input SET of the 6th shift register M6, the output end of the 6th shift register M6
OUT is connected with the reset terminal RESET of the 2nd shift register M2, output end OUT of the 3rd shift register M3 and the 7th shifting
The input SET of bit register M7 is connected, and output end OUT of the 7th shift register M7 is answered with the 3rd shift register M3's
Position end RESET is connected, by that analogy.
With reference to Fig. 2, Fig. 2 is the signal timing diagram of the shift register shown in Fig. 1, taking the 1st shift register M1 as a example,
Under the control of the high level signal of input SET input, this shift register is in the first period T1 by second clock signal end
The clock signal of high level of CKB input is that scanning signal is transmitted to the gate line being connected with output end OUT so that with this grid
The thin film transistor (TFT) of the pixel cell that line is connected is opened, and drives this pixel cell to carry out the display of image；Defeated in reset terminal RESET
Under the control of the signal entering, shift register stops exporting low level to output end OUT in the second period T2 and the 3rd period T3
Clock signal；Under the control of the signal of the first clock signal terminal CK input, shift register is in the second period T2 and the 3rd
Period T3 transmits low level pulldown signal to output end OUT, and the current potential of this gate line is dragged down, and makes and this gate line phase
The thin film transistor (TFT) of pixel cell even cuts out.
But, due to shift register by low level clock signal transmission to output end OUT when, reset terminal RESET meeting
Receive the reset signal of the output end OUT output of the 5th shift register M5 simultaneously, control this shift register to stop low electricity
Flat clock signal transmission is to output end OUT, the reset signal that is, shift register receives and the low level clock exporting
No time interval between signal, therefore, can lead to shift register cannot quick pull-down gate line current potential, thus leading to pixel
The turn-off capacity of the thin film transistor (TFT) of unit is poor, and then affects charging ability and the display effect of pixel cell.
Based on this, the invention provides a kind of gate driver circuit, to overcome the problems referred to above of prior art presence, including
To n-th grade of shift register, n is the integer more than 2 to 1st grade of shift register of cascade；
Shift register described in every one-level all includes input, output end, the first reset terminal, the first clock signal terminal and the
Two clock signal terminals；
Under the control of the signal of described input input, described shift register is in the first period by described second clock
The clock signal transmission of the first level of signal end input to described output end, in the second period by described second clock signal end
The clock signal transmission of the second electrical level of input is more than described second electrical level to described output end, described first level；
Under the control of the signal of described first clock signal terminal input, described shift register in described second period and
3rd period transmitted the pulldown signal of second electrical level to described output end；
Under the control of the signal of described first reset terminal input, described shift register stopped in described 3rd period will
The clock signal transmission of described second clock signal end input is to described output end.
In the gate driver circuit that the present invention provides, the clock that shift register can be in the second period by second electrical level
The current potential of the pulldown signal common pulldown gate line of signal and second electrical level, thereby may be ensured that the quick pull-down of gate line, enters
And the turn-off capacity of the thin film transistor (TFT) of pixel cell and the charging ability of pixel cell can be improved.
It is more than the core concept of the present invention, for enabling the above objects, features and advantages of the present invention to become apparent from easily
Understand, below in conjunction with the accompanying drawings the specific embodiment of the present invention is described in detail.
Elaborate a lot of details in the following description in order to fully understand the present invention, but the present invention is acceptable
To be implemented different from alternate manner described here using other, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
Secondly, the present invention is described in detail with reference to schematic diagram, when describing the embodiment of the present invention in detail, for purposes of illustration only, table
Show that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, its here should not
Limit the scope of protection of the invention.Additionally, the three-dimensional space of length, width and depth should be comprised in actual fabrication.
Describe in detail below by several embodiments.
Embodiments provide a kind of gate driver circuit, with reference to Fig. 3, Fig. 3 is provided in an embodiment of the present invention one
Plant the structural representation of gate driver circuit, this gate driver circuit includes the 1st grade shift register M1 to the n-th grade shifting cascading
Bit register Mn, the first clock cable CK1, second clock holding wire CKB1, the 3rd clock cable CK2 and the 4th clock letter
Number line CKB2, wherein, n is the integer more than 2.And, every one-level shift register all include input SET, output end OUT,
First reset terminal RESET, the first clock signal terminal CK and second clock signal end CKB.The output end of every one-level shift register
OUT is connected with a gate line.
With reference to Fig. 4, Fig. 4 is the signal timing diagram of the shift register shown in Fig. 3, the signal inputting in input SET
Under control, the clock signal of the first level that second clock signal end CKB is inputted by shift register in the first period T1 is swept
Retouch signal transmission to output end OUT and its connected gate line, to control the thin film transistor (TFT) being connected with this gate line to open, should
After thin film transistor (TFT) is opened, the data wire that is connected with the source electrode of this thin film transistor (TFT) by data signal transmission extremely with this film crystal
The pixel electrode that the drain electrode of pipe is connected, to be charged to this pixel electrode, makes the pixel cell that this pixel electrode is located carry out
The display of image.
Under the control of the signal of input SET input, shift register is in the second period T2 by second clock signal end
To output end OUT and its connected gate line, the first level is more than the second electricity to the clock signal transmission of the second electrical level of CKB input
Flat, optionally, the first level is high level, and second electrical level is low level.And, the signal in the first clock signal terminal CK input
Control under, shift register transmits the pulldown signal of second electrical level to output end in the second period T2 and the 3rd period T3
OUT and its connected gate line.Because shift register can be in the second period by the clock signal and second of second electrical level
The current potential of the pulldown signal common pulldown gate line of level, therefore, it can the current potential of quick pull-down gate line, makes and this gate line
Connected thin film transistor (TFT) cuts out.After this thin film transistor (TFT) cuts out, the data wire being connected with the source electrode of this thin film transistor (TFT) is stopped
Charge to the pixel electrode being connected with the drain electrode of this thin film transistor (TFT).
Under the control of the signal of the first reset terminal RESET input, shift register stops second in the 3rd period T3
The clock signal transmission of clock signal terminal CKB input is to output end OUT and its connected gate line.Due to the first reset terminal
During RESET input reset signal, also in electronegative potential, therefore, output end OUT also will not export second clock signal end CKB by mistake
High level signal is scanning signal, thereby may be ensured that the progressive scan of each row pixel cell.
In the present embodiment, as shown in figure 3, output end OUT of 2m level shift register and 2m+4 level shift register
Input SET be connected, the first reset terminal RESET of 2m level shift register and the output end of 2m+5 level shift register
OUT is connected, and output end OUT of 2m-1 level shift register is connected with the input SET of 2m+3 level shift register, the
First reset terminal RESET of 2m-1 level shift register is connected with output end OUT of 2m+4 level shift register, wherein, 0 ＜
m≤(n-7)/2.
For example, m=1, the input SET of output end OUT of the 1st grade of shift register M1 and the 5th grade of shift register M5
It is connected, the first reset terminal RESET of the 1st grade of shift register M1 is connected with output end OUT of the 6th grade of shift register M6, the 2nd
Output end OUT of level shift register M2 is connected with the input SET of the 6th grade of shift register M6, the 2nd grade of shift register M2
The first reset terminal RESET be connected with output end OUT of the 7th grade of shift register M7；M=2,3rd level shift register M3's
Output end OUT is connected with the input SET of the 7th grade of shift register M7, first reset terminal of 3rd level shift register M3
RESET is connected with output end OUT of the 8th grade of shift register M8, output end OUT of the 4th grade of shift register M4 and the 8th grade shifting
The input SET of bit register M8 is connected, first reset terminal RESET and the 9th grade of shift register of the 4th grade of shift register M4
Output end OUT of M9 is connected, by that analogy.
And, output end OUT of the n-th -4 grades shift register Mn-4 and the input of the n-th -8 grades shift register Mn-8
SET is connected, output end OUT of first reset terminal RESET and the 1st grade of shift register M1 of the n-th -4 grades shift register Mn-4
It is connected, output end OUT of the n-th -3 grades shift register Mn-3 is connected with the input SET of the n-th -7 grades shift register Mn-7,
The first reset terminal RESET of the n-th -3 grades shift register Mn-3 is connected with output end OUT of the 2nd grade of shift register M2, n-th -
Output end OUT of 2 grades of shift register Mn-2 is connected with the input SET of the n-th -6 grades shift register Mn-6, the n-th -2 grades shiftings
The first reset terminal RESET of bit register Mn-2 is connected with output end OUT of 3rd level shift register M3, and (n-1)th grade of displacement is posted
Output end OUT of storage Mn-1 is connected with the input SET of the n-th -5 grades shift register Mn-5, (n-1)th grade of shift register
The first reset terminal RESET of Mn-1 is connected with output end OUT of the 4th grade of shift register M4, and n-th grade of shift register Mn's is defeated
Go out to hold OUT to be connected with the input SET of the n-th -4 grades shift register Mn-4, first reset terminal of n-th grade of shift register Mn
RESET is connected with output end OUT of the 5th grade of shift register M5.
In the present embodiment, by by the first reset terminal RESET of 2m level shift register and 2m+5 level shift LD
Output end OUT of device is connected, the first reset terminal RESET and 2m+4 level shift register of 2m-1 level shift register defeated
Go out to hold OUT to be connected, the time to realize the first reset terminal RESET reception reset signal of shift register will with shift register
The clock signal transmission of the second electrical level of second clock signal end CKB input had between the time to the time of output end OUT
Every so that shift register can be common by the clock signal of second electrical level and the pulldown signal of second electrical level in the second period T2
With the current potential of pulldown gate line, with the current potential of rapidly pulldown gate line, certainly, the present invention is not limited to this.
In another embodiment of the invention, with reference to Fig. 5, Fig. 5 is another kind raster data model provided in an embodiment of the present invention
The structural representation of circuit, output end OUT of 2m level shift register and the input SET phase of 2m+4 level shift register
Even, the first reset terminal RESET of 2m level shift register is connected with output end OUT of 2m+6 level shift register, 2m-
Output end OUT of 1 grade of shift register is connected with the input SET of 2m+3 level shift register, 2m-1 level shift LD
First reset terminal RESET of device is connected with output end OUT of 2m+5 level shift register, wherein, 0 ＜ m≤(n-7)/2.
For example, m=1, the input SET of output end OUT of the 1st grade of shift register M1 and the 5th grade of shift register M5
It is connected, the first reset terminal RESET of the 1st grade of shift register M1 is connected with output end OUT of the 7th grade of shift register M7, the 2nd
Output end OUT of level shift register M2 is connected with the input SET of the 6th grade of shift register M6, the 2nd grade of shift register M2
The first reset terminal RESET be connected with output end OUT of the 8th grade of shift register M8；M=2,3rd level shift register M3's
Output end OUT is connected with the input SET of the 7th grade of shift register M7, first reset terminal of 3rd level shift register M3
RESET is connected with output end OUT of the 9th grade of shift register M9 output end OUT of the 4th grade of shift register M4 and the 8th grade of shifting
The input SET of bit register M8 is connected, first reset terminal RESET and the 10th grade of shift LD of the 4th grade of shift register M4
Output end OUT of device M10 is connected.
And, output end OUT of the n-th -5 grades shift register Mn-5 and the input of the n-th -9 grades shift register Mn-9
SET is connected, output end OUT of first reset terminal RESET and the 1st grade of shift register M1 of the n-th -5 grades shift register Mn-5
It is connected, output end OUT of the n-th -4 grades shift register Mn-4 is connected with the input SET of the n-th -8 grades shift register Mn-8,
The first reset terminal RESET of the n-th -4 grades shift register Mn-4 is connected with output end OUT of the 2nd grade of shift register M2, n-th -
Output end OUT of 3 grades of shift register Mn-3 is connected with the input SET of the n-th -7 grades shift register Mn-7, the n-th -3 grades shiftings
The first reset terminal RESET of bit register Mn-3 is connected with output end OUT of 3rd level shift register M3, and the n-th -2 grades displacements are posted
Output end OUT of storage Mn-2 is connected with the input SET of the n-th -6 grades shift register Mn-6, the n-th -2 grades shift registers
The first reset terminal RESET of Mn-2 is connected with output end OUT of the 4th grade of shift register M4, (n-1)th grade of shift register Mn-1
Output end OUT be connected with the input SET of the n-th -5 grades shift register Mn-5, the first of (n-1)th grade of shift register Mn-1
Reset terminal RESET is connected with output end OUT of the 5th grade of shift register M5, output end OUT of n-th grade of shift register Mn with
The input SET of the n-th -4 grades shift register Mn-4 is connected, the first reset terminal RESET and the 6th of n-th grade of shift register Mn
Output end OUT of level shift register M6 is connected.
In this embodiment, by by the first reset terminal RESET of 2m level shift register and 2m+6 level shift LD
Output end OUT of device is connected, the first reset terminal RESET and 2m+5 level shift register of 2m-1 level shift register defeated
Go out to hold OUT to be connected, the time to realize the first reset terminal RESET reception reset signal of shift register will with shift register
The clock signal transmission of the second electrical level of second clock signal end CKB input had between the time to the time of output end OUT
Every so that shift register can be common by the clock signal of second electrical level and the pulldown signal of second electrical level in the second period T2
With the current potential of pulldown gate line, with the current potential of rapidly pulldown gate line, certainly, the present invention is not limited to this.
In another embodiment, with reference to Fig. 6, Fig. 6 is another kind gate driver circuit provided in an embodiment of the present invention
Structural representation, output end OUT of 2m level shift register is connected with the input SET of 2m+4 level shift register, the
First reset terminal RESET of 2m level shift register is connected with output end OUT of 2m+7 level shift register, and 2m-1 level is moved
Output end OUT of bit register is connected with the input SET of 2m+3 level shift register, and the of 2m-1 level shift register
One reset terminal RESET is connected with output end OUT of 2m+6 level shift register, wherein, 0 ＜ m≤(n-7)/2.
For example, m=1, the input SET of output end OUT of the 1st grade of shift register M1 and the 5th grade of shift register M5
It is connected, the first reset terminal RESET of the 1st grade of shift register M1 is connected with output end OUT of the 8th grade of shift register M8, the 2nd
Output end OUT of level shift register M2 is connected with the input SET of the 6th grade of shift register M6, the 2nd grade of shift register M2
The first reset terminal RESET be connected with output end OUT of the 9th grade of shift register M9；M=2,3rd level shift register M3's
Output end OUT is connected with the input SET of the 7th grade of shift register M7, first reset terminal of 3rd level shift register M3
RESET is connected with output end OUT of the 10th grade of shift register M10, output end OUT of the 4th grade of shift register M4 and the 8th grade
The input SET of shift register M8 is connected, and the first reset terminal RESET of the 4th grade of shift register M4 is posted with the 11st grade of displacement
Output end OUT of storage M11 is connected.
And, output end OUT of the n-th -6 grades shift register Mn-6 and the input of the (n-1)th 0 grades of shift register Mn-10
End SET is connected, the output end of first reset terminal RESET and the 1st grade of shift register M1 of the n-th -6 grades shift register Mn-6
OUT is connected, the input SET phase of output end OUT of the n-th -5 grades shift register Mn-5 and the n-th -9 grades shift register Mn-9
Even, the first reset terminal RESET of the n-th -5 grades shift register Mn-5 is connected with output end OUT of the 2nd grade of shift register M2,
Output end OUT of the n-th -4 grades shift register Mn-4 is connected with the input SET of the n-th -8 grades shift register Mn-8, and n-th -4
The first reset terminal RESET of level shift register Mn-4 is connected with output end OUT of 3rd level shift register M3, the n-th -3 grades shiftings
Output end OUT of bit register Mn-3 is connected with the input SET of the n-th -7 grades shift register Mn-7, the n-th -3 grades shift LDs
The first reset terminal RESET of device Mn-3 is connected with output end OUT of the 4th grade of shift register M4, the n-th -2 grades shift registers
Output end OUT of Mn-2 is connected with the input SET of the n-th -6 grades shift register Mn-6, the n-th -2 grades shift register Mn-2's
First reset terminal RESET is connected with output end OUT of the 5th grade of shift register M5, the output of (n-1)th grade of shift register Mn-1
End OUT is connected with the input SET of the n-th -5 grades shift register Mn-5, first reset terminal of (n-1)th grade of shift register Mn-1
RESET is connected with output end OUT of the 6th grade of shift register M6, output end OUT of n-th grade of shift register Mn and the n-th -4 grades
The input SET of shift register Mn-4 is connected, and the first reset terminal RESET of n-th grade of shift register Mn is posted with the 7th grade of displacement
Output end OUT of storage M7 is connected.
In this embodiment, by by the first reset terminal RESET of 2m level shift register and 2m+7 level shift LD
Output end OUT of device is connected, the first reset terminal RESET and 2m+6 level shift register of 2m-1 level shift register defeated
Go out to hold OUT to be connected, the time to realize the first reset terminal RESET reception reset signal of shift register will with shift register
The clock signal transmission of the second electrical level of second clock signal end CKB input had between the time to the time of output end OUT
Every so that shift register can be common by the clock signal of second electrical level and the pulldown signal of second electrical level in the second period T2
With the current potential of pulldown gate line, with the current potential of rapidly pulldown gate line, certainly, the present invention is not limited to this.
Additionally, in the gate driver circuit shown in Fig. 3, Fig. 5 and Fig. 6, adjacent two in all odd level shift registers
Level shift register the first clock signal terminal CK respectively with the first clock cable CK1 and second clock holding wire CKB1 phase
Even, in all odd level shift registers the second clock signal end CKB of adjacent two-stage shift register respectively with the 3rd clock
Holding wire CK2 and the 4th clock cable CKB2 is connected；Adjacent two-stage shift register in all even level shift registers
First clock signal terminal CK is connected with the first clock cable CK1 and second clock holding wire CKB1 respectively, and all even levels move
In bit register the second clock signal end CKB of adjacent two-stage shift register respectively with the 3rd clock cable CK2 and the 4th
Clock cable CKB2 is connected.
For example, in all odd level shift registers, adjacent two-stage shift register is the 1st grade of shift register M1 and the 3rd
Level shift register M3, the first clock signal terminal CK of the 1st grade of shift register M1 are connected with the first clock cable CK1, and the 3rd
The first clock signal terminal CK of level shift register M3 is connected with second clock holding wire CKB1, the 1st grade of shift register M1's
Second clock signal end CKB is connected with the 3rd clock cable CK2, the second clock signal end CKB of 3rd level shift register M3
It is connected with the 4th clock cable CKB2.
In all even level shift registers, adjacent two-stage shift register is the 2nd grade shift register M2 and the 4th grade shifting
The first clock signal terminal CK of bit register M4, the 2nd grade of shift register M2 is connected with the first clock cable CK1, the 4th grade of shifting
The first clock signal terminal CK of bit register M4 is connected with second clock holding wire CKB1, and the second of the 2nd grade of shift register M2
Clock signal terminal CKB is connected with the 3rd clock cable CK2, the second clock signal end CKB of the 4th grade of shift register M4 and
Four clock cable CKB2 are connected.
In another embodiment, with reference to Fig. 7, Fig. 7 is another kind gate driver circuit provided in an embodiment of the present invention
Structural representation, wherein, output end OUT of 2m level shift register and the input SET phase of 2m+2 level shift register
Even, the first reset terminal RESET of 2m level shift register is connected with output end OUT of 2m+3 level shift register, 2m-
Output end OUT of 1 grade of shift register is connected with the input SET of 2m+1 level shift register, 2m-1 level shift LD
First reset terminal RESET of device is connected with output end OUT of 2m+2 level shift register, wherein, 0 ＜ m≤(n-3)/2..
For example, the input SET of m=1, output end OUT of the 1st grade of shift register M1 and 3rd level shift register M3
It is connected, the first reset terminal RESET of the 1st grade of shift register M1 is connected with output end OUT of the 4th grade of shift register M4, the 2nd
Output end OUT of level shift register M2 is connected with the input SET of the 4th grade of shift register M4, the 2nd grade of shift register M2
The first reset terminal RESET be connected with output end OUT of the 5th grade of shift register M5.
And, output end OUT of the n-th -2 grades shift registers is connected with the input SET of the n-th -4 grades shift registers,
First reset terminal RESET of the n-th -2 grades shift registers is connected with output end OUT of the 1st grade of shift register, (n-1)th grade of shifting
Output end OUT of bit register is connected with the input SET of the n-th -3 grades shift registers, and the first of (n-1)th grade of shift register
Reset terminal RESET is connected with output end OUT of the 2nd grade of shift register, output end OUT of n-th grade of shift register and n-th -2
The input SET of level shift register is connected, the first reset terminal RESET of n-th grade of shift register and 3rd level shift register
Output end OUT be connected.
Additionally, the 1st grade of shift register is to the first clock signal terminal CK of n-th grade of shift register and the first clock signal
Line CK1 is connected, the second clock signal end CKB of the 1st grade of shift register to n-th grade of shift register and second clock holding wire
CKB1 is connected.
In gate driver circuit shown in Fig. 7, by by the first reset terminal RESET of 2m level shift register and
Output end OUT of 2m+3 level shift register is connected, the first reset terminal RESET of 2m-1 level shift register and 2m+2 level
Output end OUT of shift register is connected, and the first reset terminal RESET to realize shift register receives the time of reset signal
The clock signal transmission of second electrical level second clock signal end CKB being inputted with shift register to output end OUT time
Between there is time interval so that shift register in the second period T2 by the clock signal of second electrical level and second electrical level
The current potential of pulldown signal common pulldown gate line, thereby may be ensured that the quick pull-down of gate line, and then can improve pixel list
The turn-off capacity of thin film transistor (TFT) of unit and the charging ability of pixel cell.
Gate driver circuit shown in Fig. 7 is with the difference of the gate driver circuit shown in Fig. 3, Fig. 5 and Fig. 6,
Gate driver circuit shown in Fig. 7 can only carry out forward direction along the direction of the 1st grade of shift register M1 to n-th grade of shift register Mn
Scanning, and the gate driver circuit shown in Fig. 3, Fig. 5 and Fig. 6 not only can be posted along the 1st grade of shift register M1 to n-th grade of displacement
The direction of storage Mn carries out forward scan, and can be along the direction of n-th grade of shift register Mn to the 1st grade of shift register M1
Carry out reverse scan.
A kind of internal structure and signal timing diagram with reference to shift register are entered to the operation principle of shift register
Row explanation, with reference to Fig. 8 and Fig. 9, Fig. 8 is a kind of internal of shift register in gate driver circuit provided in an embodiment of the present invention
Structural representation, Fig. 9 is the signal timing diagram of the shift register shown in Fig. 8, taking the 1st grade of shift register M1 as a example, this shifting
Bit register includes first switch pipe K1 to the 7th switching tube K7, the first electric capacity C1 and the second electric capacity C2.
Wherein, the control end of first switch pipe K1 is connected with the input SET of shift register, and the of first switch pipe K1
One end is connected with first voltage end VGH；
The control end of second switch pipe K2 is connected with the first reset terminal RESET of shift register, second switch pipe K2's
First end is connected with second voltage end VGL, and second end of second switch pipe K2 is connected with second end of first switch pipe K1；
The first end of the 3rd switching tube K3 is connected with second voltage end VGL, and second end of the 3rd switching tube K3 is opened with second
The second end closing pipe K2 is connected, and the control end of the 3rd switching tube K3 is connected with second end of the 4th switching tube K4；
The control end of the 4th switching tube K4 is connected with second end of first switch pipe K1, the first end of the 4th switching tube K4 with
Second voltage end VGL is connected, and the second clock of the first electric capacity C1 and shift register is passed through at second end of the 4th switching tube K4
Signal end CKB is connected；
The control end of the 5th switching tube K5 is connected with second end of first switch pipe K1, the first end of the 5th switching tube K5 with
Second clock signal end CKB is connected, second end of the 5th switching tube K5 and output end OUT of shift register, and the 5th switch
The control end of pipe K5 is connected with second end of the 5th switching tube K5 by the second electric capacity C2；
The control end of the 6th switching tube K6 is connected with second end of the 4th switching tube K4, the first end of the 6th switching tube K6 with
Second voltage end VGL is connected, and second end of the 6th switching tube K6 is connected with output end OUT；
The control end of the 7th switching tube K7 is connected with the first clock signal terminal CK of shift register, the 7th switching tube K7's
First end is connected with second voltage end VGL, and second end of the 7th switching tube K7 is connected with output end OUT.
In embodiments of the invention, so that first switch pipe K1 to the 7th switching tube K7 is as PMOS transistor as a example said
Bright, but, the present invention is not limited to this.After the input SET input high level signal of shift register, first switch pipe K1
Conducting.
First period T1, first switch pipe K1 transmit the high level that first voltage end VGH inputs to node PU, and to
Two electric capacity C2 are charged, when the voltage of the second electric capacity C2 reaches the cut-in voltage of the 5th switching tube K5, the 5th switching tube K5
Open, by the clock signal transmission of the high level of second clock signal end CKB input to output end OUT, wherein, in the second electric capacity
In the charging process of C2, the bootstrap effect of the second electric capacity C2 can make the current potential of node PU be lifted further.
The low level clock signal transmission that second clock signal end CKB is inputted by the second period T2, the 5th switching tube K5
To output end OUT, meanwhile, the high level signal of the first clock signal terminal CK input controls the 7th transistor K7 to open, by second
The low level signal of voltage end VGL output is that pulldown signal is transmitted to output end OUT, in low level clock signal and low level
The collective effect of pulldown signal under, the current potential of gate line is by quick pull-down.
In the 3rd period T3, the first reset terminal RESET input high level signal of shift register, second switch pipe K2 leads
Logical, the low level of second voltage end VGL is transmitted to node PU, with the grid potential of drop-down 5th switching tube K5 so that the 5th
Switching tube K5 closes.
During due to the 5th switching tube K5 to the output end OUT low level clock signal of output, the first reset terminal RESET is also not
Receive reset signal, therefore, it can export low level clock signal and pulldown signal by output end OUT to gate line, come
The current potential of quick pull-down gate line, and then the turn-off capacity of the thin film transistor (TFT) of pixel cell and filling of pixel cell can be improved
Electric energy power.Simultaneously as first reset terminal RESET input reset signal when, second clock signal end CKB also in electronegative potential,
Therefore, output end OUT also will not export high level signal by mistake is scanning signal, thereby may be ensured that each row pixel cell line by line
Scanning.
Certainly, the present invention is not limited to this, and in other embodiments, with reference to Figure 10, Figure 10 carries for the embodiment of the present invention
For gate driver circuit in shift register another kind of internal structure schematic diagram, this shift register also includes the second reset
End IN, the 8th switching tube K8 and the 9th switching tube K9；Wherein, the control end of the 8th switching tube K8 is connected with the second reset terminal IN,
The first end of the 8th switching tube K8 is connected with second voltage end VGL, and second end of the 8th switching tube K8 is connected with output end OUT；
The control end of the 9th switching tube K9 is connected with the second reset terminal IN, the first end of the 9th switching tube K9 and second voltage end VGL phase
Even, second end of the 9th switching tube K9 is connected with second end of first switch pipe K1.
When the signal of the second reset terminal IN input is high level signal, the 8th switching tube K8 and the 9th switching tube K9 leads
Logical, and the low level of second voltage end VGL is transmitted to node PU, with the current potential of drop-down 5th switching tube K5 grid, and will be low
Level is exported to the gate line being connected with output end OUT, to carry out clearly to the grid of the 5th switching tube K5 and the current potential of gate line
Zero.
In the present embodiment, by by the first reset terminal RESET of 2m level shift register and 2m+5 level shift LD
Output end OUT of device is connected, the first reset terminal RESET and 2m+4 level shift register of 2m-1 level shift register defeated
Go out to hold OUT to be connected, to realize low level clock signal and the first reset terminal RESET input of second clock signal end CKB output
Reset signal between time interval, certainly, the present invention is not limited to this.
The embodiment of the present invention additionally provides a kind of array base palte, and with reference to Figure 11, Figure 11 is provided in an embodiment of the present invention one
The planar structure schematic diagram of kind of array base palte, this array base palte includes gate driver circuit that any of the above-described embodiment provides and many
Bar gate lines G 1～Gn, wherein, the 1st grade of shift register M1 to n-th grade of shift register Mn's in gate driver circuit is defeated
Go out to hold OUT to correspond with a plurality of gate lines G 1～Gn respectively to be connected, to be scanned one by one to gate lines G 1～Gn, so that right
Pixel unit array is progressively scanned.Certainly, the array base palte in the present embodiment also includes a plurality of data lines, multiple pixel list
The pixel unit array of unit's composition and driving chip etc., will not be described here.
The embodiment of the present invention additionally provides a kind of display device, and this display device includes the array base of above-described embodiment offer
Plate.
Gate driver circuit, array base palte and display device that the embodiment of the present invention is provided, because shift register exists
, to output end, stopping in the 3rd period will for the clock signal transmission of the second electrical level that second clock signal end is inputted by the second period
The clock signal transmission of the second electrical level of second clock signal end input is to output end, i.e. the first reset termination of shift register
The clock signal transmission of the second electrical level that second clock signal end is inputted by the time of receipts reset signal with shift register is extremely defeated
There is between the time going out end time interval, therefore, the clock letter that shift register can be in the second period by second electrical level
Number and second electrical level pulldown signal common pulldown gate line current potential, thereby may be ensured that the quick pull-down of gate line, and then
The turn-off capacity of the thin film transistor (TFT) of pixel cell and the charging ability of pixel cell can be improved.
In this specification, each embodiment is described by the way of going forward one by one, and what each embodiment stressed is and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.Upper to the disclosed embodiments
State bright, so that professional and technical personnel in the field is capable of or use the present invention.To multiple modifications of these embodiments to ability
Will be apparent from for the professional and technical personnel in domain, generic principles defined herein can be without departing from the present invention's
In the case of spirit or scope, realize in other embodiments.Therefore, the present invention be not intended to be limited to shown in this article these
Embodiment, and it is to fit to the wide scope consistent with principles disclosed herein and features of novelty.
Claims (11)
1. a kind of gate driver circuit it is characterised in that include cascade the 1st grade of shift register to n-th grade of shift register,
N is the integer more than 2；
Each described shift register all includes input, output end, the first reset terminal, the first clock signal terminal and second clock
Signal end；
Under the control of the signal of described input input, described shift register is in the first period by described second clock signal
Described second clock signal end, to described output end, is inputted by the clock signal transmission of the first level of end input in the second period
Second electrical level clock signal transmission to described output end, described first level is more than described second electrical level；
Under the control of the signal of described first clock signal terminal input, described shift register is in described second period and the 3rd
Period transmits the pulldown signal of second electrical level to described output end；
Under the control of the signal of described first reset terminal input, described shift register stopped in described 3rd period will be described
The clock signal transmission of second clock signal end input is to described output end.
2. circuit according to claim 1 is it is characterised in that the output end of 2m level shift register is moved with 2m+4 level
The input of bit register is connected, the first reset terminal of 2m level shift register and the output end of 2m+5 level shift register
It is connected, the output end of 2m-1 level shift register is connected with the input of 2m+3 level shift register, 2m-1 level shifts
First reset terminal of register is connected with the output end of 2m+4 level shift register；
The output end of the n-th -4 grades shift registers is connected with the input of the n-th -8 grades shift registers, the n-th -4 grades shift LDs
First reset terminal of device is connected with the output end of the 1st grade of shift register, the output end of the n-th -3 grades shift registers and n-th -7
The input of level shift register is connected, the output of the first reset terminal of the n-th -3 grades shift registers and the 2nd grade of shift register
End is connected, and the output end of the n-th -2 grades shift registers is connected with the input of the n-th -6 grades shift registers, and the n-th -2 grades displacements are posted
First reset terminal of storage is connected with the output end of 3rd level shift register, the output end of (n-1)th grade of shift register with n-th-
The input of 5 grades of shift registers is connected, the first reset terminal of (n-1)th grade of shift register and the 4th grade of shift register M4's
Output end is connected, and the output end of n-th grade of shift register is connected with the input of the n-th -4 grades shift registers, and n-th grade of displacement is posted
First reset terminal of storage is connected with output end OUT of the 5th grade of shift register；
Wherein, 0 ＜ m≤(n-7)/2.
3. circuit according to claim 1 is it is characterised in that the output end of 2m level shift register is moved with 2m+4 level
The input of bit register is connected, the first reset terminal of 2m level shift register and the output end of 2m+6 level shift register
It is connected, the output end of 2m-1 level shift register is connected with the input of 2m+3 level shift register, 2m-1 level shifts
First reset terminal of register is connected with the output end of 2m+5 level shift register；
The output end of the n-th -5 grades shift registers is connected with the input of the n-th -9 grades shift registers, the n-th -5 grades shift LDs
First reset terminal of device is connected with the output end of the 1st grade of shift register, the output end of the n-th -4 grades shift registers and n-th -8
The input of level shift register is connected, the output of the first reset terminal of the n-th -4 grades shift registers and the 2nd grade of shift register
End is connected, and the output end of the n-th -3 grades shift registers is connected with the input of the n-th -7 grades shift registers, and the n-th -3 grades displacements are posted
First reset terminal of storage is connected with the output end of 3rd level shift register, the output end of the n-th -2 grades shift registers with n-th -
The input of 6 grades of shift registers is connected, and the first reset terminal of the n-th -2 grades shift registers is defeated with the 4th grade of shift register
Go out end to be connected, the output end of (n-1)th grade of shift register is connected with the input of the n-th -5 grades shift registers, (n-1)th grade of displacement
First reset terminal of register is connected with the output end of the 5th grade of shift register, the output end of n-th grade of shift register with n-th-
The input of 4 grades of shift registers is connected, the output of the first reset terminal of n-th grade of shift register and the 6th grade of shift register
End is connected；
Wherein, 0 ＜ m≤(n-7)/2.
4. circuit according to claim 1 is it is characterised in that the output end of 2m level shift register is moved with 2m+4 level
The input of bit register is connected, the first reset terminal of 2m level shift register and the output end of 2m+7 level shift register
It is connected, the output end of 2m-1 level shift register is connected with the input of 2m+3 level shift register, 2m-1 level shifts
First reset terminal of register is connected with the output end of 2m+6 level shift register；
The output end of the n-th -6 grades shift registers is connected with the input of the (n-1)th 0 grades of shift registers, the n-th -6 grades shift LDs
First reset terminal of device is connected with the output end of the 1st grade of shift register, the output end of the n-th -5 grades shift registers and n-th -9
The input of level shift register is connected, the output of the first reset terminal of the n-th -5 grades shift registers and the 2nd grade of shift register
End is connected, and the output end of the n-th -4 grades shift registers is connected with the input of the n-th -8 grades shift registers, and the n-th -4 grades displacements are posted
First reset terminal of storage is connected with the output end of 3rd level shift register, the output end of the n-th -3 grades shift registers with n-th -
The input of 7 grades of shift registers is connected, and the first reset terminal of the n-th -3 grades shift registers is defeated with the 4th grade of shift register
Go out end to be connected, the output end of the n-th -2 grades shift registers is connected with the input of the n-th -6 grades shift registers, the n-th -2 grades displacements
First reset terminal of register is connected with the output end of the 5th grade of shift register, the output end of (n-1)th grade of shift register and the
The input of n-5 level shift register is connected, the first reset terminal of (n-1)th grade of shift register and the 6th grade of shift register
Output end is connected, and the output end of n-th grade of shift register is connected with the input of the n-th -4 grades shift registers, and n-th grade of displacement is posted
First reset terminal of storage is connected with the output end of the 7th grade of shift register；
Wherein, 0 ＜ m≤(n-7)/2.
5. the circuit according to any one of Claims 1-4 is it is characterised in that described gate driver circuit also includes first
Clock cable is to the 4th clock cable；
When in all odd level shift registers, the first clock signal terminal of adjacent two-stage shift register is respectively with described first
Clock holding wire is connected with second clock holding wire, in all odd level shift registers adjacent two-stage shift register second when
Clock signal end is connected with described 3rd clock cable and the 4th clock cable respectively；
When in all even level shift registers, the first clock signal terminal of adjacent two-stage shift register is respectively with described first
Clock holding wire is connected with second clock holding wire, in all even level shift registers adjacent two-stage shift register second when
Clock signal end is connected with described 3rd clock cable and the 4th clock cable respectively.
6. circuit according to claim 1 is it is characterised in that the output end of 2m level shift register is moved with 2m+2 level
The input of bit register is connected, the first reset terminal of 2m level shift register and the output end of 2m+3 level shift register
It is connected, the output end of 2m-1 level shift register is connected with the input of 2m+1 level shift register, 2m-1 level shifts
First reset terminal of register is connected with the output end of 2m+2 level shift register；
The output end of the n-th -2 grades shift registers is connected with the input of the n-th -4 grades shift registers, the n-th -2 grades shift LDs
First reset terminal of device is connected with the output end of the 1st grade of shift register, the output end of (n-1)th grade of shift register and n-th -3
The input of level shift register is connected, the output of the first reset terminal of (n-1)th grade of shift register and the 2nd grade of shift register
End is connected, and the output end of n-th grade of shift register is connected with the input of the n-th -2 grades shift registers, n-th grade of shift register
The first reset terminal be connected with the output end of 3rd level shift register；
Wherein, 0 ＜ m≤(n-3)/2.
7. circuit according to claim 6 is it is characterised in that described gate driver circuit also includes the first clock cable
With second clock holding wire；
Described 1st grade of shift register to n-th grade of shift register the first clock signal terminal and described first clock cable
It is connected, the second clock signal end of described 1st grade of shift register to n-th grade of shift register and described second clock holding wire
It is connected.
8. circuit according to claim 1 is it is characterised in that described 1st grade of shift register is to n-th grade of shift register
In any one shift register all include first switch Guan Zhi seven switching tube, the first electric capacity and the second electric capacity；
The control end of described first switch pipe is connected with the input of described shift register, the first end of described first switch pipe
It is connected with first voltage end；
The control end of described second switch pipe is connected with the first reset terminal of described shift register, and the of described second switch pipe
One end is connected with second voltage end, and the second end of described second switch pipe is connected with the second end of described first switch pipe；
The first end of described 3rd switching tube is connected with described second voltage end, the second end of described 3rd switching tube and described the
Second end of two switching tubes is connected, and the control end of described 3rd switching tube is connected with the second end of described 4th switching tube；
The control end of described 4th switching tube is connected with the second end of described first switch pipe, the first end of described 4th switching tube
It is connected with described second voltage end, and described first electric capacity and described shift register are passed through in the second end of described 4th switching tube
Second clock signal end be connected；
The control end of described 5th switching tube is connected with the second end of described first switch pipe, the first end of described 5th switching tube
It is connected with described second clock signal end, the second end of described 5th switching tube and the output end of described shift register, and institute
The control end stating the 5th switching tube is connected with the second end of described 5th switching tube by described second electric capacity；
The control end of described 6th switching tube is connected with the second end of described 4th switching tube, the first end of described 6th switching tube
It is connected with described second voltage end, the second end of described 6th switching tube is connected with described output end；
The described control end of the 7th switching tube is connected with the first clock signal terminal of described shift register, described 7th switching tube
First end be connected with described second voltage end, the second end of described 7th switching tube is connected with described output end.
9. circuit according to claim 8 it is characterised in that described shift register also include the second reset terminal, the 8th
Switching tube and the 9th switching tube；
The control end of described 8th switching tube is connected with described second reset terminal, the first end of described 8th switching tube and described the
Two voltage ends are connected, and the second end of described 8th switching tube is connected with described output end；
The control end of described 9th switching tube is connected with described second reset terminal, the first end of described 9th switching tube and described the
Two voltage ends are connected, and the second end of described 9th switching tube is connected with the second end of described first switch pipe.
10. a kind of array base palte is it is characterised in that include a plurality of gate line and gate driver circuit；
Described gate driver circuit is the gate driver circuit described in any one of claim 1 to 9；
The 1st grade of shift register in described gate driver circuit is many with described respectively to the output end of n-th grade of shift register
Bar gate line corresponds and is connected.
A kind of 11. display devices are it is characterised in that include the array base palte described in claim 10.
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