CN106407156A - A method and a system for BOOTROM guiding multi-core CPU boot - Google Patents
A method and a system for BOOTROM guiding multi-core CPU boot Download PDFInfo
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Abstract
The invention provides a method and a system for BOOTROM guiding multi-core CPU boot. The method comprises the steps of: A, setting a processor ID register for distinguishing a CPU in advance; B, when the CPU is electrified, tacitly approving that a main core executes an instruction and starting a main core operating system image; C, in an application program of the main core operating system image, copying a slave core operating system image code from NOR FLASH to a slave core memory boot address; D, setting a boot page translation register address to start slave cores. The system comprises a presetting module, a main core boot module, a copying module and a slave core boot module. Multiple cores of a CPU can be started only by compiling one copy of a BOOTROM code, and the multiple-core CPU can be started at the same time, so that the problem of complicated burn maintenance in an AMP system is solved and the problem that NOR FLASH is non-accessible after an SMP system starts slave cores.
Description
Technical field
The present invention relates to embedded system BSP technical field, more particularly, to one BOOTROM guiding multi-core CPU opens
Dynamic method and system.
Background technology
BSP is board suppot package, i.e. Board support package, is between motherboard hardware and operating system
One layer it should say the part being belonging to operating system, main purpose is to support operating system, enables preferably
Run on hardware mainboard.
Embedded system field, the application for multinuclear is divided into symmetric multi-processors（I.e. English：Symmetrical Multi-
Processing, abbreviation SMP）With asymmetric multiprocessing（I.e. English：Asymmetric-Multi-Processing, is abbreviated as
AMP, ASMP）, they adapt to various different applications.Although there is very big difference in them, will be many in processor
Individual core starts, and they can be executed and each instructs and work together.
In Linux system, with PowerPC double-core P1021 citing.Smp system, U-BOOT（I.e. Universal Boot
Loader）By the startup code compilation from core in a page（page）（4KB）Section in, address be _ _ secondary_start_
Page, and this section of Code copying has been arrived random access memory when U-BOOT starts（I.e. Random Access
Memory, RAM, also known as " random access memory）In.Main core will start when core, because E500 CPU starts address is all
The physical address being located from core code is therefore passed through MMU TLB by 0xffff-fffc（I.e. Memory Manage Unit
, memory management unit, Translation Lookaside Buffers, changes fast table）It is mapped to the virtual address of 4G-4K
Space, then starts from core.So the drawbacks of is exactly：If CPU is from local bus Nor Flash, and (Local Bus bus is again
Referred to as cpu bus) start（Major applications are all such）, the address space of the Nor Flash last 64MB in 4GB space（Nor
The size of flash）, start after core, the virtual address due to having reset last 4K is address ram, then Nor flash
Address space（Remove top 4KB）Will be unable to access, data access occurs and stops（I.e. Data Access abort）Abnormal.
In vxworks system, also illustrated with PowerPC double-core P1021.AMP system, principal and subordinate's core has each independent
BOOTROM and operation system image (i.e. OS image).So system is exactly to there are 2 BOOTROM, and programming is in Nor flash
Upper diverse location.Main core starts when core, and setting starts page translation register BPTR（I.e. Boot Page Translation
Register）It is the address being located from core BOOTROM, then start from core.So start stream from the flow process of core startup and main core
Journey is just the same.Such startup thinking is simple, easy-to-understand.But each burning BOOTROM wants burning 2, also will simultaneously
2 BOOTROM of compiling, burning is comparatively laborious with release maintenance.
Therefore, prior art has yet to be improved and developed.
Content of the invention
In view of in place of above-mentioned the deficiencies in the prior art, it is an object of the invention to provide a BOOTROM guides multi-core CPU
The method and system starting, it is intended to propose a kind of code maintenance simply, only can start multi-core CPU with a BOOTRM, and
Do not affect the scheme of BOOTROM space access, solve the problems, such as AMP system safeguards that burning is loaded down with trivial details, also solves smp system and opens
The dynamic problem that can not access NOR FLASH after core.
In order to achieve the above object, the technical scheme that present invention solution technical problem is adopted is as follows：
The method that one BOOTROM guides multi-core CPU to start, comprises the following steps：
A, pre-set distinguish CPU processor ID register；
After the upper electricity of B, CPU, give tacit consent to main core execute instruction, start main core operation system image；
C, in main core operation system image application program, will from core operation system image code from NOR FLASH copy to from
Core internal storage starting address；
D, setting start page translation register address, start from core.
A described BOOTROM guides the method that multi-core CPU starts, wherein, step A specifically, arranging processor ID
Register be when 0 based on core, processor ID register is to be from core during N, wherein, N be not equal to 0 numeral.
A described BOOTROM guides the method that multi-core CPU starts, and wherein, step B specifically includes：
B1, main core initialize internal register from 0xffff-fffc instruction fetch, are tentatively arranged；
B2, by access Double Data Rate synchronous DRAM, by whole BOOTROM Code copying to random access memory
Device ram space, address is RAM-HIGH-ADRS；
B3, by absolute jump instruction by program counter move on to random access memory ram space execute BOOTROM code,
Initialization network interface serial ports, peripheral hardware, setting start-up parameter, BOOT menu, automatic；
Operation system image is read RAM-LOW-ADRS from FLASH region with file mode by B4, main core；
B5, main core jump to RAM-LOW-ADRS, start main core operation system image.
A described BOOTROM guides the method that multi-core CPU starts, and wherein, step C is specially：Operate system in main core
In system image application program, will be copied to from NOR FLASH with file mode from core operation system image code and open from core internal memory
At the Double Data Rate synchronous DRAM initial address of dynamic address 512M+RAM-LOW-ADRS.
A described BOOTROM guides the method that multi-core CPU starts, and wherein, step D specifically includes：
It is 0xffff-fffc that D1, setting start page translation register address；
D2, execute among BOOTROM from core, and read first instruction execution from 0xffff-fffc；
D3, when reading processor ID register is from core, execution initialization is from the instruction of core；
D4, then directly definitely redirecting mode, jump to RAM-LOW-ADRS and run, enter and hold from core operation system image
OK.
A described BOOTROM guides the method that multi-core CPU starts, and wherein, step D3 specifically includes：
Execution initialization described in step D3 is specially from the instruction of core：The value of initialization internal register, and internal memory is set
Administrative unit changes the initial value of fast table, is entered as starting point in internal memory for the operation system image to program counter register
Location, makes the virtual address of the physical address map of 512M+RAM-LOW-ADRS to RAM-LOW-ADRS, and mapping size is 512M.
The system that one BOOTROM guides multi-core CPU to start, including：
Pre-set module, for pre-setting the processor ID register distinguishing CPU；
Main core starting module, after electricity on CPU, gives tacit consent to main core execute instruction, starts main core operation system image；
Copy module, in main core operation system image application program, will be from core operation system image code from NOR
FLASH copies to from core internal storage starting address；
From core starting module, start page translation register address for setting, start from core.
A described BOOTROM guides the system that multi-core CPU starts, and wherein, pre-sets module and is specially setting process
Device ID register be when 0 based on core, processor ID register is to be from core during N, wherein, N be not equal to 0 numeral.
A described BOOTROM guides the system that multi-core CPU starts, and wherein, main core starting module includes：
The preliminary arranging unit of main core, initializes internal register for main core from 0xffff-fffc instruction fetch, is tentatively set
Put；
Copied cells, for by access Double Data Rate synchronous DRAM, by whole BOOTROM Code copying to
Machine accesses memory RAM space, and address is RAM-HIGH-ADRS；
Redirect start unit, hold for program counter is moved on to by random access memory ram space by absolute jump instruction
Row BOOTROM code, initialization network interface serial ports, peripheral hardware, setting start-up parameter, BOOT menu, automatic；
Operation system image is read RAM-LOW- from FLASH region with file mode for main core by the first reading unit
ADRS；
Main core start unit, jumps to RAM-LOW-ADRS for main core, starts main core operation system image.
A described BOOTROM guides the system that multi-core CPU starts, and wherein, copy module is specially in the operation of main core
In system image application program, will be copied to from core internal memory from NOR FLASH with file mode from core operation system image code
Start at the Double Data Rate synchronous DRAM initial address of address 512M+RAM-LOW-ADRS；
Include from core starting module：
Address setting unit, starting page translation register address for setting is 0xffff-fffc；
Second reading unit, for executing in BOOTROM from core, and reads first instruction execution from 0xffff-fffc；
From core initialization unit, for when reading processor ID register is from core, execution initialization is from the instruction of core；
From core start unit, directly definitely to redirect mode, jump to RAM-LOW-ADRS and run, enter from core behaviour for then
Make system image execution.
Beneficial effect：Compared to prior art, the method for the BOOTROM guiding multi-core CPU startup that the present invention provides
And system, methods described includes：A, pre-set distinguish CPU processor ID register；After the upper electricity of B, CPU, give tacit consent to main core and hold
Row instruction, starts main core operation system image；C, in main core operation system image application program, will be from core operation system image
Code copies to from core internal storage starting address from NOR FLASH；D, setting start page translation register address, start from core.Institute
The system of stating includes：Pre-set module, main core starting module, copy module, from core starting module.In technical solution of the present invention
BOOTROM code only need to compile portion so that it may start multi-core CPU simultaneously, solve and safeguard loaded down with trivial details the asking of burning in AMP system
Topic, also solves the problems, such as that smp system starts and can not access NOR FLASH after core, is that a BOOTROM starts a CPU
In multiple cores core, start a CPU with multiple BOOTROM, and each CPU have the technical sides such as independent BOOTROM
Case is entirely different.
Brief description
Fig. 1 is 4GB double-core cpu address spatial distribution map in AMP system in prior art.
The flow chart that Fig. 2 guides the method preferred embodiment of multi-core CPU startup for the BOOTROM that the present invention provides.
Fig. 3 guides the cpu address spatial distribution map of double-core CPU startup for the BOOTROM that the present invention provides.
Fig. 4 guides the functional module of the system preferred embodiment of multi-core CPU startup for the BOOTROM that the present invention provides
Figure.
Specific embodiment
For making the objects, technical solutions and advantages of the present invention clearer, clear and definite, develop simultaneously embodiment pair referring to the drawings
The present invention further describes.It should be appreciated that specific embodiment described herein is only in order to explain the present invention, and without
In the restriction present invention.
Refer to Fig. 2, Fig. 2 is that the BOOTROM that the present invention provides guides the method preferred embodiment that multi-core CPU starts
Flow chart, including step：
S100, pre-set distinguish CPU processor ID register；
Pre-set processor ID register PIR, i.e. the Processor Identification Register distinguishing CPU,
Being used for distinguishing is which core of processor CPU, i.e. core.
When being embodied as, step S100 can specifically, setting processor ID register PIR be when 0 based on core, processor ID
Register PIR is to be from core during N, wherein, N be not equal to 0 numeral, such as CPU be double-core when, can arrange during PIR=0 based on
Core, is from core during PIR=1, if CPU is three cores, can arrange core based on PIR=0, and PIR=1 represents first from core, and PIR=2 represents
Second core, if CPU is four cores and with first-class, can the like.
Which CPU that BOOTROM judges according to PIR currently to run in running is, taking double-core as a example, such as
Core based on PIR=0, PIR=1 is from core, thus carrying out corresponding command operating.
After the upper electricity of S200, CPU, give tacit consent to main core execute instruction, start main core operation system image；
I.e. after electricity on CPU, give tacit consent to main core execute instruction, start main core operation system image, i.e. OS image；
Specifically, after the upper electricity of CPU, if based on current operation during core, as traditional Booting sequence, initialization is internal to deposit
Device, DDR SDRAM（I.e. Double Data Rate SDRAM, is abbreviated as DDR SDRAM, i.e. Double Data Rate synchronous dynamic random
Memory）, internal memory moves, a series of actions such as network interface initialization of (a) serial ports, and guides OS image to start.
, single BOOTROM starts more than 2 core processors taking AMP system as a example.Refer to Fig. 1, Fig. 1 is existing skill
2 core 4GB cpu address spatial distribution maps in AMP system in art：Principal and subordinate core BOOTROM is in FLASH ROM（ROM, that is,
Read Only Memory, read-only storage）Highest 1MB；Principal and subordinate's core version leaves the remaining 63MB of FLASH ROM in；Main
Core image takies 0 ~ 512MB DDR SDRAM space；Take 512M ~ 1024M DDR SDRAM space from core；Other spaces are
CPU internal register, the space such as CPLD, PCI, NAND FLASH.
Refer to Fig. 3, Fig. 3 guides the cpu address space that double-core CPU starts to divide for the BOOTROM that the present invention provides
Butut, specifically, Fig. 3 is whole BOOTROM guiding OS image and starts address space distribution map during core, whole
Individual DDR SDRAM size be 1GB, main core with each account for 512MB DDR SDRAM space from core AMP system.
See also Fig. 1, Fig. 2 and Fig. 3, further, in this step, step S200 specifically includes：
After the upper electricity of S210, CPU, give tacit consent to main core execute instruction, main core initializes internal register from 0xffff-fffc instruction fetch,
Tentatively arranged；
S220, by access Double Data Rate synchronous DRAM, whole BOOTROM Code copying is deposited to arbitrary access
Reservoir ram space, address is RAM-HIGH-ADRS；
S230, by absolute jump instruction by program counter move on to random access memory ram space execute BOOTROM generation
Code, initialization network interface serial ports, peripheral hardware, setting start-up parameter, BOOT menu, automatic；
Operation system image is read RAM-LOW-ADRS from FLASH region with file mode by S240, main core；
S250, main core jump to RAM-LOW-ADRS, start main core operation system image.
Specifically, that is, after the upper electricity of S210, CPU, give tacit consent to main core execute instruction, main core is from the beginning of 0xffff-fffc instruction fetch
Beginningization internal register, configures DDR sdram controller, adjusts MMU TLB（I.e. Memory Management Unit, storage
Device administrative unit, Translation Look-aside Buffers transmits posterior bumper, and that is, memory management unit conversion is fast
Table）, piece is set and selects the basic preparation such as attribute；
S220, now DDR SDRAM（I.e. Double Data Rate synchronous DRAM）Can access, by whole BOOTROM generation
Code all copies to ram space, and address is RAM-HIGH-ADRS；
S230, by absolute jump instruction by PC（I.e. program counter, is abbreviated as PC, program counter）Move on to RAM empty
Between execute, still carry out BOOTROM code, then initialization network interface serial ports, peripheral hardware, setting start-up parameter, BOOT menu, automatically
Start etc.；
S240, start the OS stage, main core is by operation system image（I.e. OS image）Read with file mode from FLASH region
RAM-LOW-ADRS；
S250, main core jump to RAM-LOW-ADRS, start main core operation system image, that is, start main core OS image.
S300, in main core operation system image application program, will copy from NOR FLASH from core operation system image code
Shellfish is to from core internal storage starting address；
I.e. in main core OS image application program, will be copied from NOR FLASH with file mode from the OS image code of core
To from core internal storage starting address；
Please continue to refer to Fig. 2 and Fig. 3, step S300 is specially：In main core operation system image application program, will operate from core
System image code is copied to double from core internal storage starting address 512M+RAM-LOW-ADRS with file mode from NOR FLASH
At times speed synchronous DRAM DDR SDRAM initial address；
I.e. in the operation of main core OS image application program, from the OS image of core, 512M+RAM- will be read with file mode
At the DDR SDRAM initial address of LOW-ADRS.
S400, setting start page translation register address, start from core；
I.e. setting starts page translation register BPTR address is 0xffff-fffc, and allows from core startup.
Please continue to refer to Fig. 2 and Fig. 3, step S400 specifically includes：
It is 0xffff-fffc that S410, setting start page translation register address；
S420, execute among BOOTROM from core, and read first instruction execution from 0xffff-fffc；
S430, when reading processor ID register is from core, execution initialization is from the instruction of core；
S440, then directly definitely redirecting mode, jump to RAM-LOW-ADRS and run, enter and hold from core operation system image
OK.
Specifically, that is, S420, this be from core execution, execute among BOOTROM from core, take from 0xffff-fffc from core
Article first, instruction execution；
S430, reading PIR register are when core, and execution initialization is from the instruction of core；
After i.e. reading PIR register is 1, execution initialization is from the instruction of core.
Execution initialization described in step S430 is specially from the instruction of core：The value of initialization internal register, and
Setting memory management unit changes the initial value of fast table MMU TLB, to program counter register PC（The full name of PC is Program
Counter）It is entered as initial address in internal memory for the operation system image, make the physical address of 512M+RAM-LOW-ADRS reflect
It is mapped to the virtual address of RAM-LOW-ADRS, mapping size is 512M, then the virtual address scope run from core remains as 0～
512MB.
S440, then directly definitely redirecting mode, jump to RAM-LOW-ADRS and run, enter and reflect from core operating system
As execution.
Specifically, take first instruction execution from core from 0xffff-fffc, that is, the code of BOOTROM, with double-core
As a example, after reading PIR=1, will not deinitialization DDR again, network interface serial ports etc., as long as and initialize the value of internal register, and
And some initial values of MMU TLB are set.Then carry out and redirect preparation, be OS image in internal memory to PC register assignment
Initial address, then directly definitely to redirect mode, jumps to RAM-LOW-ADRS and runs, just jump directly to OS from core
Image performs, and enters the OS image stage hence it is evident that faster much than main core start-up course this moment, simpler than main core.
Certainly, technique scheme is also similar in smp system, for smp system, from core from ROM instruction fetch, does not change
Become MMU TLB last 4KB page is remapped.
In technical solution of the present invention, BOOTROM code only need to compile portion so that it may start multi-core CPU simultaneously, solves AMP
Safeguard the loaded down with trivial details problem of burning in system, also solve the problems, such as that smp system starts and can not access NOR FLASH after core, be
One BOOTROM starts multiple cores core in a CPU.
Refer to Fig. 4, Fig. 4 guides the system preferred embodiment of multi-core CPU startup for the BOOTROM that the present invention provides
Functional block diagram, including：
Pre-set module 10, for pre-setting the processor ID register distinguishing CPU, as detailed above；
Main core starting module 20, after electricity on CPU, gives tacit consent to main core execute instruction, starts main core operation system image, specifically such as
Upper described；
Copy module 30, in main core operation system image application program, will be from core operation system image code from NOR
FLASH copies to from core internal storage starting address, as detailed above；
From core starting module 40, start page translation register address for setting, start from core, as detailed above.
A described BOOTROM guides the system that multi-core CPU starts, and wherein, pre-sets module 10 and is specially at setting
Reason device ID register be when 0 based on core, processor ID register is to be from core during N, wherein, N be not equal to 0 numeral, specifically
As mentioned above.
A described BOOTROM guides the system that multi-core CPU starts, and wherein, main core starting module 20 includes：
The preliminary arranging unit of main core, initializes internal register for main core from 0xffff-fffc instruction fetch, is tentatively set
Put, as detailed above；
Copied cells, for by access Double Data Rate synchronous DRAM, by whole BOOTROM Code copying to
Machine accesses memory RAM space, and address is RAM-HIGH-ADRS, as detailed above；
Redirect start unit, hold for program counter is moved on to by random access memory ram space by absolute jump instruction
Row BOOTROM code, initialization network interface serial ports, peripheral hardware, setting start-up parameter, BOOT menu, automatic, specifically as above institute
State；
Operation system image is read RAM-LOW- from FLASH region with file mode for main core by the first reading unit
ADRS, as detailed above；
Main core start unit, jumps to RAM-LOW-ADRS for main core, starts main core operation system image, specifically as above institute
State.
A described BOOTROM guides the system that multi-core CPU starts, and wherein, copy module 30 is specially in main core behaviour
Make in system image application program, will be copied in core from NOR FLASH with file mode from core operation system image code
Deposit and start at the Double Data Rate synchronous DRAM initial address of address 512M+RAM-LOW-ADRS, specifically as above institute
State；
Include from core starting module 40：
Address setting unit, starting page translation register address for setting is 0xffff-fffc；
Second reading unit, for executing in BOOTROM from core, and reads first instruction execution, tool from 0xffff-fffc
Body is as described above；
From core initialization unit, for when reading processor ID register is from core, execution initializes the instruction from core, specifically
As mentioned above；
From core start unit, directly definitely to redirect mode, jump to RAM-LOW-ADRS and run, enter from core behaviour for then
Make system image execution, as detailed above.
In sum, the method and system that an a kind of BOOTROM provided by the present invention guides multi-core CPU to start, institute
The method of stating includes：A, pre-set distinguish CPU processor ID register；After the upper electricity of B, CPU, give tacit consent to main core execute instruction, open
Move main core operation system image；C, in main core operation system image application program, will be from core operation system image code from NOR
FLASH copies to from core internal storage starting address；D, setting start page translation register address, start from core.Described system includes：
Pre-set module, main core starting module, copy module, from core starting module.In technical solution of the present invention, BOOTROM code only needs
Compiling portion, so that it may start multi-core CPU simultaneously, solves the problems, such as to safeguard in AMP system that burning is loaded down with trivial details, also solves SMP system
System starts the problem that can not access NOR FLASH after core, is multiple cores core that a BOOTROM starts in a CPU,
Start a CPU with multiple BOOTROM, and each CPU to have the technical schemes such as independent BOOTROM entirely different.
Certainly, one of ordinary skill in the art will appreciate that realizing all or part of flow process in above-described embodiment method,
Can be by computer program to instruct related hardware（As processor, controller etc.）To complete, described program can store
In the storage medium of an embodied on computer readable, this program may include upon execution as the flow process of above-mentioned each method embodiment.Its
Described in storage medium can be memory, magnetic disc, CD etc..
It should be appreciated that the application of the present invention is not limited to above-mentioned citing, for those of ordinary skills, can
To be improved according to the above description or to convert, all these modifications and variations all should belong to the guarantor of claims of the present invention
Shield scope.
Claims (10)
1. a BOOTROM guides the method for multi-core CPU startup it is characterised in that comprising the following steps：
A, pre-set distinguish CPU processor ID register；
After the upper electricity of B, CPU, give tacit consent to main core execute instruction, start main core operation system image；
C, in main core operation system image application program, will from core operation system image code from NOR FLASH copy to from
Core internal storage starting address；
D, setting start page translation register address, start from core.
2. a BOOTROM according to claim 1 guides the method for multi-core CPU startup it is characterised in that step A has
Body is, setting processor ID register be when 0 based on core, processor ID register is to be from core during N, and wherein, N is to be not equal to 0
Numeral.
3. a BOOTROM according to claim 1 guides the method for multi-core CPU startup it is characterised in that step B has
Body includes：
B1, main core initialize internal register from 0xffff-fffc instruction fetch, are tentatively arranged；
B2, by access Double Data Rate synchronous DRAM, by whole BOOTROM Code copying to random access memory
Device ram space, address is RAM-HIGH-ADRS；
B3, by absolute jump instruction by program counter move on to random access memory ram space execute BOOTROM code,
Initialization network interface serial ports, peripheral hardware, setting start-up parameter, BOOT menu, automatic；
Operation system image is read RAM-LOW-ADRS from FLASH region with file mode by B4, main core；
B5, main core jump to RAM-LOW-ADRS, start main core operation system image.
4. a BOOTROM according to claim 1 guides the method for multi-core CPU startup it is characterised in that step C has
Body is：In main core operation system image application program, will from core operation system image code with file mode from NOR FLASH
Copy the Double Data Rate synchronous DRAM initial address from core internal storage starting address 512M+RAM-LOW-ADRS to
Place.
5. a BOOTROM according to claim 1 guides the method for multi-core CPU startup it is characterised in that step D has
Body includes：
It is 0xffff-fffc that D1, setting start page translation register address；
D2, execute among BOOTROM from core, and read first instruction execution from 0xffff-fffc；
D3, when reading processor ID register is from core, execution initialization is from the instruction of core；
D4, then directly definitely redirecting mode, jump to RAM-LOW-ADRS and run, enter and hold from core operation system image
OK.
6. a BOOTROM according to claim 5 guides the method for multi-core CPU startup it is characterised in that step D3 has
Body includes：
Execution initialization described in step D3 is specially from the instruction of core：The value of initialization internal register, and internal memory is set
Administrative unit changes the initial value of fast table, is entered as starting point in internal memory for the operation system image to program counter register
Location, makes the virtual address of the physical address map of 512M+RAM-LOW-ADRS to RAM-LOW-ADRS, and mapping size is 512M.
7. a BOOTROM guides the system of multi-core CPU startup it is characterised in that including：
Pre-set module, for pre-setting the processor ID register distinguishing CPU；
Main core starting module, after electricity on CPU, gives tacit consent to main core execute instruction, starts main core operation system image；
Copy module, in main core operation system image application program, will be from core operation system image code from NOR
FLASH copies to from core internal storage starting address；
From core starting module, start page translation register address for setting, start from core.
8. a BOOTROM according to claim 7 guides the system of multi-core CPU startup it is characterised in that pre-seting mould
Block be specially arrange processor ID register be when 0 based on core, processor ID register is to be from core during N, wherein, N be
In 0 numeral.
9. a BOOTROM according to claim 7 guides the system of multi-core CPU startup it is characterised in that main core starts
Module includes：
The preliminary arranging unit of main core, initializes internal register for main core from 0xffff-fffc instruction fetch, is tentatively set
Put；
Copied cells, for by access Double Data Rate synchronous DRAM, by whole BOOTROM Code copying to
Machine accesses memory RAM space, and address is RAM-HIGH-ADRS；
Redirect start unit, hold for program counter is moved on to by random access memory ram space by absolute jump instruction
Row BOOTROM code, initialization network interface serial ports, peripheral hardware, setting start-up parameter, BOOT menu, automatic；
Operation system image is read RAM-LOW- from FLASH region with file mode for main core by the first reading unit
ADRS；
Main core start unit, jumps to RAM-LOW-ADRS for main core, starts main core operation system image.
10. a BOOTROM according to claim 7 guides the system of multi-core CPU startup it is characterised in that copying mould
Block be specially in main core operation system image application program, will from core operation system image code with file mode from NOR
FLASH copies to and initiates from the Double Data Rate synchronous DRAM of core internal storage starting address 512M+RAM-LOW-ADRS
At address；
Include from core starting module：
Address setting unit, starting page translation register address for setting is 0xffff-fffc；
Second reading unit, for executing in BOOTROM from core, and reads first instruction execution from 0xffff-fffc；
From core initialization unit, for when reading processor ID register is from core, execution initialization is from the instruction of core；
From core start unit, directly definitely to redirect mode, jump to RAM-LOW-ADRS and run, enter from core behaviour for then
Make system image execution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610844750.6A CN106407156B (en) | 2016-09-23 | 2016-09-23 | The method and system of one BOOTROM guidance multi-core CPU starting |
Applications Claiming Priority (1)
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| CN113282344B (en) * | 2021-05-25 | 2022-11-04 | 中国航空无线电电子研究所 | Method for realizing weather operating system on Feiteng asymmetric dual-core processor |
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| CN114090086A (en) * | 2021-11-23 | 2022-02-25 | 西安微电子技术研究所 | Embedded operating system quick starting method based on ZynqMP platform |
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| CN117251216A (en) * | 2023-09-15 | 2023-12-19 | 上海合芯数字科技有限公司 | Server firmware starting optimization method, system, server and storage medium |
| CN117251216B (en) * | 2023-09-15 | 2024-04-05 | 上海合芯数字科技有限公司 | Server firmware starting optimization method, system, server and storage medium |
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